Internal Use Only
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LED TV
SERVICE MANUAL
CHASSIS : LA48V
MODEL : 49UB8200 49UB8200-UH
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL68500704 (1406-REV00) Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 14
EXPLODED VIEW .................................................................................. 26
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder ES
on page 3 of this publication, always follow the safety precautions. devices.
Remember: Safety First. 4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board mod- 6. Do not remove a replacement ES device from its protective
ule or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads electri-
other electrical connection. cally shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material
installation of electrolytic capacitors may result in an explo- to the chassis or circuit assembly into which the device will be
sion hazard. installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or circuit,
high voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropriate
(by volume) isopropyl alcohol (90 % - 99 % strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand against
ily by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten-
tial shock reasons prior to applying power to the unit under test.
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed whenever
gently prying up on the lead with the soldering iron tip as the this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remaining good copper pattern. Solder the overlapped area and clip off
on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied to the LED TV used LA48V
2. Test condition
Each part is tested as below without special notice.
1) Temperature : 25 ºC ± 5 ºC(77±9ºF), CST : 40 ºC±5 ºC
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
Standard input voltage (100~240V@ 50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : UL, CSA, CE, IEC specification
- EMC : FCC, ICES, CE, IEC specification
- Wireless : Wireless HD Specification (Option)
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
4. General Specification
No Item Specification Remark
1 Market 1) North America
2 Receiving System ATSC / NTSC-M / 64 QAM / 256 QAM
3 Input Voltage AC 100 - 240V ~ 60Hz
4 Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
5) CADTV : 01~135
5 Input Voltage AC 100-240V ~50/60Hz
6 Screen Size 40 inch Wide(3840 × 2160) 40UB8000-UB
47 inch Wide(3840 × 2160) 49UB8300-UG, 49UB8200-UH
55 inch Wide(3840 × 2160) 55UB8300-UG, 55UB8200-UH
60 inch Wide(3840 × 2160) 60UB8300-UG, 60UB8200-UH
65 inch Wide(3840 × 2160) 65UB9200-UA
5 Aspect Ratio 16:9
6 Tuning System FS
7 LCD Module V400DK1-KS1 INX 40UB8000-UB,
LC490EQE-XGF2 LGD 49UB8300-UG,
LC490EQE-XGM1 LGD 49UB8200-UH,
LC550EQE-PGF2 LGD 55UB8300-UG,
LC550EQE-PGM1 LGD 55UB8200-UH,
LGD 60UB8300-UG,
LGD 60UB8200-UH,
LC650EQF-FGM1 LGD 65UB9200-UA
8 Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
9 Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. External input format
5.1. 2D Mode
5.1.1. Component input(Y, CB/PB, CR/PR)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
1 720*480 15.73 60 13.514 SDTV ,DVD 480I
2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3 720*480 31.50 60 27.027 SDTV 480P
4 720*480 31.47 59.94 27.0 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.500 60 148.50 HDTV 1080P
5.1.2. HDMI Input (PC/DTV)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed
HDMI-PC EGA
1 640*350 31.468 70.09 25.17 DOS Х
2 720*400 31.469 70.08 28.32 VESA(VGA) O
3 640*480 31.469 59.94 25.17 VESA(SVGA) O
4 800*600 37.879 60.317 40.00 VESA(XGA) O
5 1024*768 48.363 60.00 65.00 VESA O
6 1152*864 54.348 60.053 80.00 VESA (SXGA) O
7 1280*1024 63.981 60.020 108.00 VESA (WXGA) O
8 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9 1920*1080 67.5 60 148.5 WUXGA(Reduced Blanking) O
10 3840*2160 54 24.00 297.00 UDTV 2160P O
11 3840*2160 56.25 25.00 297.00 UDTV 2160P O
12 3840*2160 67.5 30.00 297.00 UDTV 2160P O
14 4096*2160 53.95 23.98 297.00 UDTV 2160P O
15 4096*2160 54.00 24.00 297.00 UDTV 2160P O
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
HDMI-DTV
1 640 * 480 31.469 59.94 SDTV 480P
2 640 * 480 31.5 60 SDTV 480P
3 720*480 31.469 59.94 27.00 SDTV 480P
4 720*480 31.50 60 27.027 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.500 60 148.50 HDTV 1080P
10 1920*1080 67.432 59.939 148.352 HDTV 1080P
11 1920*1080 27.000 24.000 74.25 HDTV 1080P
12 1920*1080 26.97 23.976 74.176 HDTV 1080P
13 1920*1080 33.75 30.000 74.25 HDTV 1080P
14 1920*1080 33.71 29.97 74.176 HDTV 1080P
15 3840*2160 67.5 30.00 297.00 UDTV 2160P
16 3840*2160 61.43 29.97 296.703 UDTV 2160P
17 3840*2160 56.25 25.00 297.00 UDTV 2160P
18 3840*2160 54.0 24.00 297.00 UDTV 2160P
19 3840*2160 53.95 23.976 296.703 UDTV 2160P
20 3840*2160 135 59.94 593.41 UDTV 2160P(8 bit / YCbCr 4:2:0 Only)
21 3840*2160 135 60 594.00 UDTV 2160P(8 bit / YCbCr 4:2:0 Only)
22 4096*2160 53.95 23.976 296.703 UDTV 2160P
23 4096*2160 54 24 297 UDTV 2160P
24 4096*2160 56.25 25 297 UDTV 2160P
25 4096*2160 61.43 29.97 296.703 UDTV 2160P
26 4096*2160 67.5 30 297 UDTV 2160P
27 4096*2160 135 59.94 593.41 UDTV 2160P(8 bit / YCbCr 4:2:0 Only)
28 4096*2160 135 60 594.00 UDTV 2160P(8 bit / YCbCr 4:2:0 Only)
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
5.2. 3D Mode
5.2.1. HDMI Input 1.4b (3D supported mode automatically)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock VIC 3D input proposed Proposed
(MHz) mode
1 640*480 31.469 / 31.5 59.94/ 60 25.175/25.2 1 Top-and-Bottom Secondary(SDTV 480P)
Side-by-side(half) Secondary(SDTV 480P)
Side-by-side(full)
62.938 / 63 59.94/ 60 50.35/50.4 1 Frame packing Secondary(SDTV 480P)
Line alternative (SDTV 480P)
2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 Top-and-Bottom Secondary(SDTV 480P)
Side-by-side(half) Secondary(SDTV 480P)
Side-by-side(full)
62.938 / 63 59.94 / 60 54/54.06 2,3 Frame packing Secondary(SDTV 480P)
Line alternative (SDTV 480P)
3 1280*720 44.96 / 45 59.94 / 60 74.18/74.25 4 Top-and-Bottom Primary(HDTV 720P)
Side-by-side(half) Primary(HDTV 720P)
Side-by-side(full)
89.91 / 90 59.94 / 60 148.35/148.5 4 Frame packing Primary(HDTV 720P)
Line alternative (HDTV 720P)
4 1920*1080 33.72 / 33.75 59.94 / 60 74.18/74.25 5 Top-and-Bottom Secondary(HDTV 1080I)
Side-by-side(half) Primary(HDTV 1080I)
Side-by-side(full)
67.432 / 67.5 59.94 / 60 148.35/148.5 5 Frame packing Primary(HDTV 1080I)
Field alternative (HDTV 1080I)
26.97 / 27 23.97 / 24 74.18/74.25 32 Top-and-Bottom Primary(HDTV 1080P)
Side-by-side(half) Primary(HDTV 1080P)
Side-by-side(full)
43.94 / 54 23.97 / 24 148.35/148.5 32 TFrame packing Primary(HDTV 1080P)
Line alternative (HDTV 1080P)
28.125 25 74.25 33 Top-and-Bottom Secondary(HDTV 1080P)
Side-by-side(half) Secondary(HDTV 1080P)
Side-by-side(full)
56.25 25 148.5 33 Frame packing Secondary(HDTV 1080P)
Line alternative (HDTV 1080P)
33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Top-and-Bottom Primary(HDTV 1080P)
Side-by-side(half) Secondary(HDTV 1080P)
Side-by-side(full)
67.432 / 67.5 29.976 / 30.00 148.35/148.5 34 Frame packing Primary(HDTV 1080P)
Line alternative (HDTV 1080P)
67.43 / 67.5 59.94 / 60 148.35/148.50 16 Top-and-Bottom Primary(HDTV 1080P)
Side-by-side(half) Secondary(HDTV 1080P)
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
5.2.2. HDMI 1.4/2.0(3D Supported mode manaually)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed 3D input proposed mode
(MHz)
1. 720*480 31.5 60 27.03 SDTV 480P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential,
2. 1280*720 45.00 60.00 74.25 HDTV 720P
Row Interleaving, Column Interleaving
3. 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half), Top & Bottom
4. 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving,
5. 1920*1080 28.12 25 74.25 HDTV 1080P
Column Interleaving
6. 1920*1080 33.75 30.00 74.25 HDTV 1080P
7. 1920*1080 67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential,
8. 3840*2160 53.95 23.976 296.703 HDTV 2160P
Row Interleaving, Column Interleaving
9. 3840*2160 54 24.00 297.00 HDTV 2160P
10. 3840*2160 56.25 25.00 297.00 HDTV 2160P
11. 3840*2160 61.43 29.970 296.703 HDTV 2160P
12. 3840*2160 67.5 30.00 297.00 HDTV 2160P
13. 4096*2160 53.95 23.976 296.703 HDTV 2160P
14. 4096*2160 54 24.00 297.00 HDTV 2160P
15. 4096*2160 56.25 25.00 297.00 HDTV 2160P
16. 4096*2160 61.43 29.970 296.703 HDTV 2160P
17. 4096*2160 67.5 30.00 297.00 HDTV 2160P
18. 3840*2160 135 60 594 HDTV 2160P 2D to 3D, Top & Bottom(half),
Side by Side(half), Port3 Only
19. 4096*2160 135 60 594 HDTV 2160P 2D to 3D, Top & Bottom(half),
Side by Side(half), Port3 Only
5.2.3. HDMI-PC Input (3D) (3D Supported Mode Manually)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed 3D input proposed mode
(MHz)
1. 1024*768 48.36 60 65 HDTV 768P 2D to 3D,
Side by Side(half), Top & Bottom
2. 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D,
Side by Side(half), Top & Bottom,
Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving
3. 3840*2160 54 24.00 296.703 HDTV 2160P 2D to 3D,
Top & Bottom, Side by Side(half),
56.25 25.00 297
67.5 30.00 296.703
4. 4096*2160 54 24.00 297.00 HDTV 2160P 2D to 3D,
Side by Side(half), Top & Bottom
5. Others - - - 2D to 3D,
Side by Side(half), Top & Bottom
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
5.2.4. RF Input(3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 DTV 74.25 HD/SD 2D to 3D, Side by Side, Top & Bottom
2 ATV 74.25 SD 2D to 3D, Side by Side, Top & Bottom
5.2.5. RF Input (3D supported mode automatically)
No. Signal 3D input proposed mode
1 Frame Compatible Side by Side(Half), Top & Bottom
5.2.6. USB, DLNA (Movie) Input (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 704x480 - - - 2D to 3D
2 Over 704x480 - - - 2D to 3D, Side by Side(Half), Top & Bottom
interlaced
3 Over 704x480 - 60 - 2D to 3D, Side by Side(Half), Top & Bottom,
progressive Checker Board, Row Interleaving, Column Interleaving,
Frame Sequential
4 Over 704x480 - others - 2D to 3D, Side by Side(Half), Top & Bottom,
progressive Checker Board, Row Interleaving, Column Interleaving
5 Over 2160P - 24/25/30 - 2D to 3D, Side by Side(Half), Top & Bottom, USB Only
5.2.7. USB, DLNA (Photo) Input (3D supported mode manually)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 320x240 - - - 2D to 3D
2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom
5.2.8. USB, DNLA Input (3D supported mode automatically) – not used
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1080P 33.75 30 - Side by Side(Half), Top & Bottom, Checker Board,
MPO(Photo)
2 2160p 67.5 30 297 MPO(Photo), JPS(Photo)
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
5.2.9. Component Input(3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D,
Side by Side(Half),
2 1280*720 44.96 59.94 74.176 HDTV 720P
Top & Bottom
3 1920*1080 33.75 60.00 74.25 HDTV 1080I
5 1920*1080 33.72 59.94 74.176 HDTV 1080I
5 1920*1080 27.00 24.00 74.25 HDTV 1080P
6 1920*1080 26.97 23.976 74.176 HDTV 1080P
7 1920*1080 28.12 25 74.25 HDTV 1080P
8 1920*1080 33.75 30.00 74.25 HDTV 1080P
9 1920*1080 33.71 29.97 74.176 HDTV 1080P
10 1920*1080 67.50 60.00 148.5 HDTV 1080P
11 1920*1080 67.432 59.94 148.352 HDTV 1080P
5.2.10. Miracast, Widi (3D supported mode manually)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1024X768p - 30 / 60 - 2D to 3D, Side by Side(Half), Top & Bottom
2 1280x720p - 30 / 60 -
3 1920X1080p 30 / 60
4 Others - 2D to 3D
**Remark: 3D Input mode
No. Side by Side Top & Bottom Checkerboard Single Frame Frame 2D to 3D Line Interleav- Column
Sequential Packing ing Interleaving
1
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 4. PCB assembly adjustment method
This spec. sheet applies to LA48V Chassis applied LED TV all 4.1. ADC Calibration : component using internal pattern
models manufactured in TV factory - An ADC calibration is needed to fine the optimum black level
and gain in Analog-to-Digital device
.
2. Specification. 4.1.1. Adj. method
(1) Because this is not a hot chassis, it is not necessary to use - Using RS-232C, adjust items listed in “4.1.2”
an isolation transformer. However, the use of isolation
transformer will help protect test instrument 4.1.2. Adj. protocol
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of Protocol Command Set ACK
25 ±5ºC of temperature and 65±10% of relative humidity if Enter adj. mode aa 00 00 a 00 OK00x
there is no specific designation Source change xb 00 40 b 00 OK04x (Adjust 480i, 1080p Comp1 )
(4) The input voltage of the receiver must keep 100~240V,
50/60Hz Begin adj. ad 00 10 OKx (Case of Success)
(5) The receiver must be operated for about 5 minutes prior to NGx (Case of Fail)
the adjustment when module is in the circumstance of over Read adj. data ad 00 20 000000000000000000000000007c007b-
15ºC 006dx
Confirm adj. ad 00 99 NG 01 00x (Fail)
▪ In case of keeping module is in the circumstance of 0°C, it OK 01 01x (Success)
should be placed in the circumstance of above 15°C for 2
hours End adj. ad 00 90 a 00 OK90x
▪ In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above 15°C 4.1.3. Adj. Order (TBD)
for 3 hours ▪ aa 00 00 [Enter adj. mode]
▪ xb 00 04 [Change input source to Component1(480i&1080p)]
* Caution) When still image is displayed for a period of 20 ▪ ad 00 10 [Adjust 480i&1080p Comp1]
minutes or longer (especially where W/B scale is ▪ aa 00 90 [End adj.]
strong. Digital pattern 13ch and/or Cross hatch
pattern 09ch), there can some afterimage in the 4.2. 4 .2.MAC Address, ESN Key and Wide-
black level area.
vine Key Download
4.2.1. Equipment & Condition
1) Play file: keydownload.exe
3. Adjustment items 2) Key Write: Com 1,2,3,4 and 115200 (Baudrate)
3.1. PCB assembly adjustment items 3) Barcode: Com 1,2,3,4 and 9600 (Baudrate)
1) MAC Address, ESN Key and Wide-vine Key D/L
2) LAN Test( Ping-Test )
3) Main S/W program download : Using USB Memory stick
4) Input Tool - Option
5) Download EDID
6) ADC Calibration – RGB & Component
7) Check SW Version
3.2. SET assembly adjustment items
1) Input Area option.
2) Adjustment of White Balance : Auto
3) Adjustment of White Balance : Manual
4) Intelligent Sensor Inspection Guide
5) LAN Inspection Guide
6) Widevine Key Inspection Guide
7) Model name & Serial number D/L
8) Wi-Fi MAC Address Check
9) Local Dimming Inspection Guide
10) Preset CH information
11) GND and Internal Pressure check
12) Motion Remote controller Inspection
13) 3D Function test
14) Outgoing Condition Configuration
15) Sound spec
16) Factoring Option Data input.
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Only for training and service purposes
4.2.2. Download process (14Y ULTRA HD TV + MAC
+ WIDEVINE + ESN)
1) Execute “keydownload.exe” on PC
2) Select the download items.
3) Mode check : Online only
4) Check the test process
-D
ETECT -> MAC_WRITE -> ESN_WRITE (only Colombia/
Panama) ->WIDEVINE_WRITE
5) Play: START
6) Check of result: Ready, Test, OK or NG
4.4. Main S/W program download
4.4.1. Using the Memory Stick
** USB DOWNLOAD : Service Mode
1) Insert the USB memory Stick to the USB port
2) Automatically detect the SW Version.
-> S/W download process is executed automatically.
3) Show the message “Copy the file from the Memory”
4.2.3. Inspection : InINSTART menu, check these keys
4.3. PING Test(LAN Operating Test)
4.3.1. Check PCBA
1) Connect LAN to PCBA& Power On.(Default IP can be set to
automatic setting. When power ON, IP can be Automatically
be achieved from the router)
2) Push ADJ key on Adjust remote-controller.
3) Enter “13. ACAP PING TEST” & check Network.
4.3.2. Check Set(Manufacturer)
1) C onnect TV-Set & PC with Cross LAN cable.(PC IP :
12.12.2.3)
2) E xecute “PINT Test program”, Check setting data of
program. (TV-Set IP : 12.12.2.2)
4) After Finished the Download, Automatically DC Off -> On
3) Push Power Only key on Adjust remote-controlle.
4) Click “RUN”, Check “OK” or “NG”
5) If the TV IS Turn On, Check the updated SW Version and
Tool Option.
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Only for training and service purposes
4.5. EDID D/L method ⓐ Product ID
Recommend that don’t connect HDMI and RGB(D-SUB) cable ⓑ Serial No: Controlled on production line.
when downloading the EDID. ⓒ Month, Year: Controlled on production line:
If not possible, recommend that connect the MSPG equipment. ex) Monthly : ‘01’ -> ‘01’
There are two methods of downloading the edid data Year : ‘2014’ -> ‘18
ⓓ Model Name(Hex): LGTV
It is a VESA regulation. A PC or a MNT will display an optimal ⓔ Checksum(LG TV): Changeable by total EDID data.
resolution through information ⓕ Vendor Specific(HDMI)
Sharing without any necessity of user input. It is a realization
of “Plug and Play” 4.5.4.1. EDID
#DTS HDMI1 (C/S: F7 82)
EDID Block 0, Bytes 0-127
4.5.1. 1st Method
EDID data’s are automatically downloaded when adjusting the
Tool Options.
Automatically downloaded when pushing the enter key in the
EDID D/L menu.
It takes about 2seconds
4.5.2. 2st Method
=> Caution : Must be checked that the tool option is right or
not. If tool option is wrong, HDMI edid data could
not be downloaded well.
1) Press the ADJ key
2) Move to the 13. EDID D/L and Press the right direction EDID Block 1, Bytes 128-255
key(►)
3) Press the right direction key(►) at Start.
4) After about a few seconds, appear “Waiting..” => “OK”, then
complete.
4.5.3. RS-232C command Method
1) Command : AE 00 10
=> Caution : D on’t connect HDMI and RGB(D-SUB) cable
when downloading the EDID. If the cables are
connected, Downloading of edid could be failed.
4.5.4. EDID DATA #DTS HDMI2 (C/S: E7 72)
▪ Reference EDID Block 0, Bytes 0-12
- HDMI1 ~ HDMI3
- In the data of EDID, bellows may be different by Input mode
EDID Block 1, Bytes 128-255
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Only for training and service purposes
#DTS HDMI3 (C/S: A1 81) # AC3 HDMI1 (C/S: E7 8B)
EDID Block 0, Bytes 0-127 EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255 EDID Block 1, Bytes 128-255
# DTS HDMI4 (C/S: E7 52) # AC3 HDMI2 (C/S: E7 7B)
EDID Block 0, Bytes 0-127 EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255 EDID Block 1, Bytes 128-255
Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
# AC3 HDMI3 (C/S: A1 8A) # PCM HDMI1 (C/S: F7 FD)
EDID Block 0, Bytes 0-127 EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255 EDID Block 1, Bytes 128-255
# AC3 HDMI4 (C/S: E7 5B) # PCM HDMI1(C/S: E7 ED)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
# PCM HDMI3 (C/S: A1 FC) 4.6. Camera Port Inspection
EDID Block 0, Bytes 0-127 (1) Objective : To check how it connects between Camera and
PCBA normally, and their Function
(2) Test Method : This Inspection is available only Power-Only
Status.
i) Push Camera Up
ii) Camera’s Preview picture appears on TV Set
iii) Push Camera Down
EDID Block 1, Bytes 128-255
(3) RS-232C Command
RS-232C COMMAND
Explanation
CMD DATA ID
Ai 00 23 Camera Function Start.
Ai 00 24 Camera Function End.
5. SET assembly adjustment method
# PCM HDMI4 (C/S: E7 CD) 5.1. Input Area-Option
(1) Profile : Must be changed the Area option value because
being different of each Country’s Language and
signal Condition.
(2) Equipment : adjustment remote control.
(3) Adjustment method
- T he input methods are same as other chassis.(Use
IN-START Key on the Adjust Remocon.)
Refer to Job Expression of each main chassis ass’y
(EBTxxxxxxxx) for Option value.
5.2. Adjustment of White Balance
▪ In case of keeping module is in the circumstance of 0°C, it
should be placed in the circumstance of above 15°C for 2
hours
▪ In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above 15°C
for 3 hours.
- Purpose : A djust the color temperature to reduce the
deviation of the module color temperature.
- Principle : To adjust the white balance without the saturation,
* Checksum (HDMI 1/2/3/4) Fix the one of R/G/B gain to 192 (default data) and
Input DTS FFh AC3 FFh PCM FFh decrease the others.
- Adjustment mode : Three modes – Cool / Medium / Warm
HDMI1 E7 82 E7 8B E7 FD
HDMI2 E7 72 E7 7B E7 ED
HDMI3 A1 81 A1 8A A1 FC
HDMI4 E7 52 E7 5B E7 CD
Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
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* Required Equipment 5.2.2. Adjustment of White Balance
▪ Remote controller for adjustment (For Automatic Adjustment)
▪ Color Analyzer : CA100+ or CA-210 or same product (should 5.2.2.1. Adj. condition and cautionary items
be used in the calibrated ch by CS-1000) 1) Lighting condition in surrounding area surrounding lighting
- LCD TV : CH-9 should be lower 10 lux. Try to isolate adj. area into dark
- PDP TV : CH-10 surrounding.
- White LED TV : CH-14 2) Probe location: Color Analyzer (CA-210) probe should be
- ALEF : CH-18 within 10cm and perpendicular of the module surface (90+/-
- RGB LED(MNT) : CH-16 2.5°)
▪ Auto W/B adjustment instrument(only for Auto adjustment) 3) Aging time
A. After Aging Start, Keep the Power ON status during 5
5.2.1. Adjustment of White Balance : Minutes.
(For Automatic Adjustment) B. In case of LCD, Back-light on should be checked using
Connecting diagram of equipment for measuring (For no signal or Full-white pattern.
Automatic Adjustment)
5.2.2.2. Equipment
1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
CH14)
2) A dj. Computer (During auto adj., RS-232C protocol is
needed)
3) Adjust Remocon
4) V ideo Signal Generator MSPG-925F 720p/216-Gray
(Model: 217, Pattern: 78)
5.2.2.3. Adjustment
1) Set TV in Adj. mode using POWER ON
1) Set TV in ADJ mode using P-ONLY key (or POWER ON 2) Zero Calibrate the probe of Color Analyzer, then place it on
key) the center of LCD module within 10cm of the surface.
2) Place optical probe on the center of the display 3) Press ADJ key -> EZ adjust using adj. R/C > 6. White-
- It need to check probe condition of zero calibration before Balance then press the cursor to the right (KEY►). When
adjustment. KEY(►) is pressed 216 Gray internal pattern will be
3) Connect RS-232C Cable displayed.
4) Select mode in ADJ Program and begin a adjustment. 4) One of R Gain / G Gain / B Gain should be fixed at 192, and
5) W hen WB adjustment is completed with OK message, the rest will be lowered to meet the desired value.
check adjustment status of pre-set mode (Cool, Medium, 5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of
Warm) color temperature.
6) Remove probe and RS-232C cable.
▪ If internal pattern is not available, use RF input. In EZ Adj.
▪ W/B Adj. must begin as start command “wb 00 00” , and menu 6.White Balance, you can select one of 2 Test-pattern:
finish as end command “wb 00 ff”, and Adj. offset if need ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.
(1) RS-232C Command used during auto-adj.
** R-fix adjustment
RS-232C COMMAND
Explanation Adjust modes (Cool), Fix the R gain to 210 (default data) and
CMD DATA ID change the others (G/B Gain ).
wb 00 00 Begin White Balance adj. - Adjust the R gain more than 210 ( If G gain or B gain is less
than 0 , R gain can adjust more than 210 ) and change the
wb 00 10 Gain adj.(internal white pattern)
others ( G/B Gain ). Adjust two modes(Medium / Warm), Fix
wb 00 1f Gain adj. completed the one of R/G/B gain to 192 (default data) and decrease the
wb 00 20 Offset adj.(internal white pattern) others.
wb 00 2f Offset adj. completed
wb 00 Ff End White Balance adj.
(internal pattern disappears )
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Only for training and service purposes
5.2.3. LED White balance table ▪ S tandard color coordinate and temperature using
5.2.3.1. Cool Mode CA-210(CH-14) – by aging time
1) Purpose : E specially G-gain fix adjust leads to the (2) Normal line in Korea (From March to December) : : LGD
luminance enhancement. Adjust the color (UB98xxx, UB95/93xxx, UB85xxx, UB83xxx, UC97 Series
temperature to reduce the deviation of the models)
module color temperature.
2) Principle : To adjust the white balance without the * Normal line in Mexico : LGD (UB98xxx, UB95/93xxx, UB85xxx,
saturation, Adjust the G gain more than 172 ( If R UB83xxx ,UC97 Series models)
gain or G gain is more than 255 , G gain can Cool Medium Warm
adjust less than 172 ) and change the others (R/B Aging time
Gain). X Y X Y X Y
(Min)
3) Adjustment mode : mode – Cool 271 270 286 289 313 329
1 0-2 282 289 297 308 324 348
5.2.3.2. Medium / Warm Mode
1) Purpose : A djust the color temperature to reduce the 2 3-5 281 287 296 306 323 346
deviation of the module color temperature. 3 6-9 279 284 294 303 321 343
2) Principle : To adjust the white balance without the 4 10-19 277 280 292 299 319 339
saturation, Fix the one of R/G/B gain to 192
(default data) and decrease the others. 5 20-35 275 277 290 296 317 336
3) Adjustment mode : Two modes – Medium / Warm 6 36-49 274 274 289 293 316 333
7 50-79 273 272 288 291 315 331
▪ Luminance: 204 Gray
▪ Standard color coordinate and temperature using CS-1000 8 80-119 272 271 287 290 314 330
(over 26 inch) 9 Over 120 271 270 286 289 313 329
Coordinate
Mode Temp △uv (3) O/S Module(AUO, INX, Sharp, CSOT, BOE)
X Y
Cool Medium Warm
Cool 0.271 0.270 13,000K 0.0000
X Y X Y X Y
Medium 0.286 0.289 9,300K 0.0000
spec 271 270 286 289 313 329
Warm 0.313 0.329 6,500K 0.0000
target 278 280 293 299 320 339
* Change reason : When vivid mode, more detail than other
company set. -. To check the Coordinates of White Balance, you have to
measure at the below conditions.
▪ S tandard color coordinate and temperature using Picture Mode : select Vivid and change
CA-210(CH-14) – by aging time Dynamic Contrast : Off ,
(1) N ormal line in Korea (From January to February) : LGD Dynamic Colour : Off,
(UB98xxx, UB95/93xxx, UB85xxx, UB83xxx, UC97 Series Clear White : Off
models) -> Picture Mode change : Vidid -> Vivid(User)
(If you miss the upper condition, the coordinates of W/B can be
Cool Medium Warm
lower than the spec.)
Aging time
X Y X Y X Y
(Min)
271 270 286 289 313 329
1 0-2 286 295 301 314 328 354
2 3-5 284 290 299 309 326 349
3 6-9 282 287 297 306 324 346
4 10-19 279 283 294 302 321 342
5 20-35 276 278 291 297 318 337
6 36-49 274 275 289 294 316 334
7 50-79 273 272 288 291 315 331
8 80-119 272 271 287 290 314 330
9 Over 120 271 270 286 289 313 329
Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only
Only for training and service purposes
5.3. Model name & Serial number D/L 5.4.2. Check the menu on in-start
5.3.1. Notice
1) Serial number D/L is using of scan equipment.
2) S etting of scan equipment operated by Manufacturing
Technology Group.
3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
4) C heck the model name In-start menu -> Factory name
displayed (ex 42LV5500-DD)
5) Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LV5500-DD)
5.3.2. Method : Auto
1) P ress “Power on” key of service remocon.(Baud rate :
115200 bps)
2) Connect RS232 Signal Cable to RS-232 Jack
3) Write Serial number by use RS-232.
4) Must check the serial number at Instart menu.
5.3.3. Method : Manual 5.5. LAN Inspection
* I f the TV set is downloaded By OTA or Service man, 5.5.1. LAN Port connection with PCB
Sometimes model name or serial number is initialized. 1) Network setting at MENU Mode of TV
(Not always) It is impossible to download by bar code scan, 2) Setting automatic IP
so It need Manual download. 3) Setting state confirmation
4) If automatic setting is finished, you confirm IP and MAC
1) Press the ‘instart’ key of ADJ remote controller. Address
2) Go to the menu ‘6.Model Number D/L’ like below photo.
3) Input the Factory model name or Serial number like photo.
5.4. Wi-Fi MAC Address Check 5.6. WIDEVINE Key Inspection
5.4.1. Using RS232 Command 1) Confirm Key input Data at the “IN START” MENU Mode
Command Set ACK
Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]
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Only for training and service purposes
5.7. Local Dimming Inspection (Optional) (C) Don’t wear a 3D Glasses, Check the picture like below.
1) Press ‘TILT” key of the Adj. R/C and check moving patterns.
The black bar patterns moves from top left to bottom right. If
local dimming function does not work, a whole screen
shows full white.
5.10. HDMI ARC Function Inspection
5.8. Motion Remote controller Inspection 5.10.1. Test equipment
1) E quipment : Motion remote controller for test, IR-KEY- - Optic Receiver Speaker
CODE remote controller for test Check battery before test. - MSHG-600 (SW: 1220 ↑)
(Recommend : Change battery for every Lot.) - HDMI Cable (for 1.4 version)
2) Process
- If you select the ‘start key(wheel)’ on the controller, you can 5.10.2. Test method
pairing with the TV SET. (1) Insert the HDMI Cable to the HDMI ARC port from the
- You can check the cursor on the TV Screen, when select the master equipment (HDMI1)
‘Wheel Key’ on the controller
- You must remove the pairing with the TV Set by select ‘Back
+ Home Key’ on the controller
5.9. 3D function test
1) Equipment : Pattern Generator MSHG-600, MSPG-6100
[SUPPORT HDMI1.4, HDMI mode 872, pattern No. 83
2) Process
(A) P
lease input 3D test pattern like below (HDMI mode NO.
872 , pattern No.83) (2) Check the sound from the TV Set
(3) Check the Sound from the Speaker or using AV & Optic
(B) W
hen 3D OSD appear automatically , then select green TEST program (It’s connected to MSHG-600)
button.
* Remark: Inspect in Power Only Mode and check SW version
in master equipment
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Only for training and service purposes
5.11. Eye-Q Green Inspection Guide 5.13. Camera Function Inspection
(Change to Motion EYE care) (1) Objective : To check how it connects between Camera and
1) Turn on the TV set. PCBA normally, and their Function
2) Press “EYE” button on the Adjustment remote controller. (2) Test Method : This Inspection is available only Power-Only
Status.
i) Slide Camera Up
ii) Camera’s Preview picture appears on TV Set
iii) Slide Camera Down
3) Block the Intelligent Sensor module on the front C/A about 6
seconds. When the “Sensor Data” is lower than 20, you can
see the “OK” message
=> If it doesn’t show “OK” message, the Sensor Module is
defected one. You have to replace that with a good one. 5.14. PIP/ W&R Function Inspection
4) After check the “OK” message come out, take out your hand
from the Sensor module. (1) Objective : To check the connection between sub tuner and
=> Check “Sensor Data” value change from “0” to “300” or not. PCBA, and their Function
If it doesn’t change the value, the sensor is also defected (2) Test Method : This Inspection is available only Power-Only
one. You have to replace it. Status.
1) Press exit key of the Adj. R/C and Press PIP key.
2) C
heck that the SUB TUNER pop up window on the TV
5.12. AUDIO Set.
No Item Min Typ Max Unit Remark 3) C
heck that the normal operation (picture, sound) of DTV
1 Audio practical 9.0 10.0 12.0 W Measurement on the TV Set.
max Output, L/R condition
(Distortion=10% 8.5 8.9 9.8 Vrms
max Output)
2 Speaker 10.0 15.0 W Measurement
(8Ω Impedance) condition
*Measurement condition:
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)
Copyright © LG Electronics. Inc. All rights reserved. - 24 - LGE Internal Use Only
Only for training and service purposes
5.15. Manual ADC Calibration(Optional) 5.16.3. Check point
5.15.1. Adjust method 1) Test voltage
(1) Enter Service Mode by pushing “ADJ” key (A) 3 Poles
(2) E nter ADC Calibration by pushing “►” key at “9. ADC - GND: 1.5KVac/min at 100mA
Calibration” - SIGNAL: 3KVac/min at 100mA
(3) Select [Reset] button by pressing Enter key 2) TEST time: 1 second
(4) Change “OTP” to “Internal” by pushing “►” key 3) TEST POINT
(5) Select [Start] button by pressing Enter key, then it will (B) 3 Poles
operate ADC adjustment. -G ND Test = POWER CORD GND and SIGNAL CABLE
GND.
- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
4) LEAKAGE CURRENT: At 0.5mArms
5.16. GND and Hi-Pot test
5.16.1. GND & HI-POT auto-check preparation
1) Check the POWER CABLE and SIGNAL CABE insertion
condition
5.16.2. GND & HI-POT auto-check
1) Pallet moves in the station. (POWER CORD / AV CORD is
tightly inserted)
2) Connect the AV JACK Tester.
3) Controller (GWS103-4) on.
4) GND Test (Auto)
- If Test is failed, Buzzer operates.
- I f Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)
5) HI-POT test (Auto)
- If Test is failed, Buzzer operates.
- I f Test is passed, GOOD Lamp on and move to next
process automatically.
Copyright © LG Electronics. Inc. All rights reserved. - 25 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
900
400
410
503
522
521
540
121
530
LV1
120
820
Set + Stand
A10
A2
200
Copyright © LG Electronics. Inc. All rights reserved. - 26 - LGE Internal Use Only
Only for training and service purposes
NVRAM +3.3V_NORMAL
IC102
AT24C256C-SSHL-T C103
EAN61133501 0.1uF
Write Protection
IC100 IC100
A0 VCC
- Low : Normal Operation LGE4331 LGE4331
1 8 - High : Write Protection
A1 WP EB_DATA[0-7]
2 7
F10 AE32
A2 A0’h 6 SCL
PWM_DIM
F9
PWM0/GPIO150 B0M
AF30
V-BY-ONE EB_DATA[0] AL21
PCMDATA[0]/GPIO145 TS1DATA_[0]/GPIO194
AJ18 TPI_DATA[0] TPI_DATA[0-7]
3 R113 33 I2C_SCL1 PWM_DIM2 PWM1/GPIO151 B0P EB_DATA[1] AK22 AH19 TPI_DATA[1]
RF_SWITCH_CTL
E11
PWM2/GPIO152 B1M
AF32 MSB/LSB swap EB_DATA[2] AK21
PCMDATA[1]/GPIO146 TS1DATA_[1]/GPIO193
AJ20 TPI_DATA[2]
GND SDA F12 AF31 PCMDATA[2]/GPIO147 TS1DATA_[2]/GPIO192
4 5 R114 33 I2C_SDA1 AMP_RESET_N PWM3/GPIO153 B1P EB_DATA[3] AH11 AG20 TPI_DATA[3]
E9 AG32 TXVBY1_7N PCMDATA[3]/GPIO117 TS1DATA_[3]/GPIO191
PWM_PM PWM_PM/GPIO7 B2M/VBY7N EB_DATA[4] AH10 AH21 TPI_DATA[4]
AG31 TXVBY1_7P PCMDATA[4]/GPIO118 TS1DATA_[4]/GPIO190
B2P/VBY7P EB_DATA[5] AG13 AH18 TPI_DATA[5]
I2C for AMP&MODULE AG30 PCMDATA[5]/GPIO119 TS1DATA_[5]/GPIO189
TXVBY1_6N AJ9 AG21 TPI_DATA[6]
BCKM/VBY6P EB_DATA[6]
H6 AH31 TXVBY1_6P PCMDATA[6]/GPIO120 TS1DATA_[6]/GPIO188
I2C_SCL7 SAR0/GPIO43 BCKP/VBY6P EB_DATA[7] AJ12 AJ21 TPI_DATA[7]
G5 AJ31 TXVBY1_5N PCMDATA[7]/GPIO121 TS1DATA_[7]/GPIO187
I2C_SDA7 SAR1/GPIO44 B3M/VBY5P EB_ADDR[0-14] AG19
G4 AJ32 TXVBY1_5P EB_ADDR[0] TS1CLK/GPIO184 TPI_CLK
+3.3V_NORMAL SAR2/GPIO45 B3P/VBY5P AM23 AH20
CHIP CONFIG B3 AJ30 TXVBY1_4N EB_ADDR[1] PCMADR[0]/GPIO144 TS1VALID/GPIO186 TPI_VAL
CVBS_OUT_SEL SAR3/GPIO46 B4M/VBY4N AK17 AG18
G6 AK32 TXVBY1_4P EB_ADDR[2] PCMADR[1]/GPIO143 TS1SYNC/GPIO185 TPI_SOP
SAR5 B4P/VBY4P AM20
PCMADR[2]/GPIO141 FE_DEMOD1_TS_DATA[0-7]
EB_ADDR[3]
4.7K
4.7K
4.7K
AL20 AH13 FE_DEMOD1_TS_DATA[0]
4.7K
Place capacitor PCMADR[3]/GPIO140 TS0DATA_[0]/GPIO173
Close to the wafer EB_ADDR[4] AK19 AG17 FE_DEMOD1_TS_DATA[1]
OPT
A5 AK31 PCMADR[4]/GPIO139 TS0DATA_[1]/GPIO174
OPT
TXVBY1_3N EB_ADDR[5] AM19 AJ17 FE_DEMOD1_TS_DATA[2]
SPI_CK/GPIO1 A0M/VBY3N
C5 AK30 TXVBY1_3P EB_ADDR[6] PCMADR[5]/GPIO137 TS0DATA_[2]/GPIO175
R157
SPI_DI AL22 AH14 FE_DEMOD1_TS_DATA[3]
R161
R163
R165
SPI_DI/GPIO2 A0P/VBY3P
A4 AL31 TXVBY1_2N EB_ADDR[7] PCMADR[6]/GPIO136 TS0DATA_[3]/GPIO176
SPI_DO/GPIO3 A1M/VBY2N AM17 AG14 FE_DEMOD1_TS_DATA[4]
B5 AL30 TXVBY1_2P EB_ADDR[8] PCMADR[7]/GPIO135 TS0DATA_[4]/GPIO177
SPI_CZ0/GPIO0 A1P/VBY2P AL15 AG16 FE_DEMOD1_TS_DATA[5]
B6 AM30 EB_ADDR[9] PCMADR[8]/GPIO129 TS0DATA_[5]/GPIO178
LED1 SPI_CZ1/GPIO_PM6/GPIO16 A2M/VBY1N AK15 AG15 FE_DEMOD1_TS_DATA[6]
+3.3V_NORMAL C6 AL29 EB_ADDR[10] PCMADR[9]/GPIO127 TS0DATA_[6]/GPIO179
SPI_DI SPI_CZ2/GPIO_PM10/GPIO20 A2P/VBY1P AG11 AH15 FE_DEMOD1_TS_DATA[7]
AM29 HTPDAn_Video EB_ADDR[11] PCMADR[10]/GPIO123 TS0DATA_[7]/GPIO180
LED0 ACKM/VBY0N AG12 AJ15
R181 AK28 EB_ADDR[12] PCMADR[11]/GPIO125 TS0CLK/GPIO183 FE_DEMOD1_TS_CLK
PWM_PM ACKP/VBY0P HTPDAn_OSD AM22 AH17
4.7K
10K
4.7K
4.7K
4.7K
AM28 EB_ADDR[13] PCMADR[12]/GPIO134 TS0VALID/GPIO181 FE_DEMOD1_TS_VAL
OPT A3M/LOCKN LOCKAn_Video AL16 AH16
FRC_FLASH_WP H4 AL28 EB_ADDR[14] PCMADR[13]/GPIO130 TS0SYNC/GPIO182 FE_DEMOD1_TS_SYNC
OPT
DDCA_CK AM16
OPT
DDCA_CK/UART0_RX/GPIO8 A3P/HTTPDN HTPDAn_Video
R182 H5 AK27 PCMADR[14]/GPIO131
10K DDCA_DA DDCA_DA/UART0_TX/GPIO9 A4M LOCKAn_OSD AJ26
R158
R162
R164
AL27 TS2DATA_[0]/GPIO207
R166
A4P HTPDAn_OSD AL17 AG26
CAM_IREQ_N PCMIRQA/GPIO133 TS2CLK/GPIO210
R125 R126 AG10 AH26
E6 10K 10K EB_OE_N PCMOEN/GPIO124 TS2SYNC/GPIO209
SOC_TX TX1/GPIO60 AJ14 AG25
D6 EB_BE_N1 PCMIORD/GPIO126 TS2VALID/GPIO208
SOC_RX RX1/GPIO61 AK18
F7 F5 /PCM_CE1 PCMCEN/GPIO122
I2C_SCL6 TX2/GPIO62 EJ_RSTZ/GPIO53 TRST_N0 AK16
E7 F4 EB_WE_N PCMWEN/GPIO132
I2C_SDA6 RX2/GPIO63 EJ_TRSTZ/GPIO54 AH12 Close to MSTAR
D7 D5 CAM_CD1_N PCMCD/GPIO149
CHIP_CONFIG[3:0] TX3/GPIO64 EJ_TCK/GPIO55 TCK0 AL18 IF_P
47K
R177
{LED1, SPI_DI,LED0, PWM_PM} E8 F6 PCM_RESET PCMRST/GPIO148 R140 100 C118 0.1uF
MUX_EN RX3/GPIO65 EJ_TMS/GPIO56 TMS0 AK20
OPT
Value Mode Description BIT5
D9 D4
TDI0
CAM_REG_N
AJ11
PCMREG/GPIO142
AL7 DTV_IF
TX4/GPIO69 EJ_TDI/GPIO57 C122
4’b1000 SB51_ExtSPI 51 boot from SPI F8 E5 EB_BE_N0 PCMIOWR/GPIO128 VIFP
BIT6 RX4/GPIO70 EJ_TDO/GPIO58 TDO0 AL19 AM7
4’b1001 HEMCU_ExtSPI ARM boot from SPI T6 E4 CAM_WAIT_N PCMWAIT/GPIO138 VIFM IF_N
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC BIT7 TX5/GPIO87 EJ_DINT/GPIO59 R141 100 C119 0.1uF OPT
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND T5 C123
BIT8 RX5/GPIO88 AL6 33pF
4’b1100 DBUS for test only SIFP OPT
AK7
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication SIFM C126
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication 33pF
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; B4 AG22
/TU_RESET1 GPIO66 PCM2_CEN/GPIO112 SIL9617_INT AM5
A3 AH22 IF_AGC
/TU_RESET2 GPIO67 PCM2_IRQA/GPIO113 AV1_CVBS_DET AK24
AG23 EMMC_RST EMMC_RSTN/GPIO204
PCM2_WAIT/GPIO114 HP_DET AK23
AH23 EMMC_CMD EMMC_CMD/GPIO206 C120 0.1uF R144 47 TU_SIF
PCM2_RESET/GPIO115 SC_DET AL24 AM8
AG29 EMMC_CLK EMMC_CLK/GPIO205 TGPIO0/GPIO169 /USB_OCD2 C121 0.1uF R145 47
AL8 R146
BIT0 TCON0/GPIO155 EMMC_DATA[0-7] C124 300
AH29 TGPIO1/GPIO170 USB_CTL2 1000pF
+3.3V_NORMAL BIT1 TCON1/GPIO156 EMMC_DATA[1] AL26 AL5 ANALOG SIF OPT OPT
AJ29 NAND_ALE/GPIO201 TGPIO2/GPIO171 /USB_OCD3
BIT2 TCON2/GPIO157 EMMC_DATA[2] AG24 AK6 Close to MSTAR
AG28 NAND_WPZ/GPIO200 TGPIO3/GPIO172 USB_CTL3
R188 BIT3 TCON3/GPIO158 EMMC_DATA[6] AK26
10K AH28 J5 NAND_CEZ/GPIO195
BIT4 TCON4/GPIO159 GPIO_PM0/GPIO10 COMP1_DET EMMC_DATA[5] AM26
OPT +3.3V_NORMAL
LM14 HW Option URSA9_CONNECT
R180 0
AJ28
AH27
SPI1_CK/GPIO104 GPIO_PM2/GPIO12
R6
P4
EMMC_DATA[4] AM25
NAND_CLE/GPIO197
NAND_REZ/GPIO198
R189 L_DIM_EN EMMC_DATA[3] AL25 L100
10K VSYNC_LIKE/GPIO103 GPIO_PM3/GPIO13 R190
AJ27 N6 0 R175 NAND_WEZ/GPIO199 BLM18PG121SN1D
+3.3V_NORMAL OPT SPI1_DI/GPIO105 GPIO_PM4/GPIO14 PCM_5V_CTL
22 EMMC_DATA[0] AK25
N5 NAND_RBZ/GPIO202
GPIO_PM7/GPIO17 TCON_I2C_EN EMMC_DATA[7] AH25
J6 NAND_CE1Z/GPIO196
Don’t use! LM14+URSA9: GPIO AH27/AJ27 U4 GPIO_PM8/GPIO18 5V_DET_HDMI_1 AH24 C125
R176
K4 NAND_DQS/GPIO203 R142 0.1uF
10K
I2C_SCL_MICOM_SOC GPIO81/SCK0 GPIO_PM9/GPIO19 5V_DET_HDMI_2 AJ24 10K
U5 L5 HDMI_MUX_SEL PCM2_CD/GPIO116
I2C_SDA_MICOM_SOC GPIO82/SDA0 GPIO_PM13/GPIO23 R9531_RESET R143
A10 L6 0
10K
10K
10K
10K
10K
10K
10K
10K
10K
DDCR_CK/GPIO52 5V_DET_HDMI_3
BIT2_1
I2C_SCL1 GPIO_PM17/GPIO27
BIT0_1
BIT1_1
BIT3_1
BIT4_1
BIT5_1
BIT6_1
BIT7_1
BIT8_1
C10 L4 IF_AGC
I2C_SDA1 DDCR_DA/GPIO51 GPIO_PM18/GPIO28 R9531_FLASH_WP
V6 C127
I2C_SCL4 GPIO83/SCK4
R108
R110
R112
R116
R118
R120
R122
R124
V5 0.047uF
R104
I2C_SDA4 GPIO84/SDA4 25V
U6
I2C_SCL5 GPIO85/SCK5 +3.3V_NORMAL
BIT0 T4
I2C_SDA5 GPIO86/SDA5
W5
BIT1 I2C_SCL2
I2C_SDA2
W6
GPIO89/SCK2
P5
/USB_OCD1
Jtag I/F
GPIO90/SDA2 GPIO_PM1/GPIO11
BIT2
GPIO_PM5/GPIO15
P6
K6
USB_CTL1 C102 For Main
R102 JTAG
R105 JTAG
R106 JTAG
BIT3 URSA_RESET_SoC 0.1uF
GPIO_PM11/GPIO21
E12 K5 JTAG
VID0 VID0/GPIO48 GPIO_PM12/GPIO22 SIL9617_RESET
BIT4
1K
1K
1K
1K
D12
R100
VID1 VID1/GPIO49
E13 P100
BIT(0/1) DVB ATSC JP LED0 LED0/GPIO29 12505WS-10A00
BIT5 F13 JTAG
LED1 LED1/GPIO30
00 TW/COL US F11 1
TRST_N0
BIT6 M_RFModule_RESET WOL/GPIO50
R5
01 CN/HK KR JP AV_LINK
2
TDI0
BIT7 G7
TEST 3
TDO0
10 EU BR
BIT8 4
TMS0
11 AJJA CI
5
TCK0
6
SOC_RESET
BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP
7
JTAG
1K
ATV_INT ATV_INT
00 T/C T/C Default ATSC_PIP ATSC_PIP Default
R101
DTV_EXT DTV_INT 8
01 T2/C/S2/ATV_EXT T2/C_PIP ATV_SOC ATV_SOC 9
10K
10K
10K
10K
10K
10K
10K
10
URSA9 VIDEO/OSD LOCKn
10K
10K
10 T2/C T2/C ATV_EXT ATV_EXT
R121BIT7_0
R123BIT8_0
R107BIT1_0
BIT2_0
BIT0_0
11
BIT3_0
BIT4_0
BIT5_0
BIT6_0
11 T2/C/S2/AT T2/C/S2
R111
R103
R115
R117
R119
R109
Low High Low High LOCKAn_Video LOCKAn_Video
10K
Vx1 Division 2-Division +3.3V_NORMAL
BIT4 Non-Division BIT6 MODEL LM14+URSA9 LM14 ONLY
R191
BIT5 Resolution FHD UHD BIT7 Reserved
VBY1_LOCK_LED
R173
22
BIT8 Reserved
VBY1_LOCK_LED
* BIT4: LM14 TX Division OPT
(LM14+URSA9: Non Division)
SML-512UW
VBY1_LOCK_LED
LD100
Mstart Debug RS232C_Debug I2C PULL UP I2C_SDA_MICOM
33 R137
I2C_SDA_MICOM_SOC
GPIO PULL UP
R174
33
220
R138
I2C_SCL_MICOM I2C_SCL_MICOM_SOC
+3.3V_LNA_TU +3.3V_NORMAL
E Q100
+3.3V_TUNER +3.3V_NORMAL MMBT3906(NXP)
MSTAR_DEBUG_OLD UART_4PIN_WAFER +3.5V_ST
B VBY1_LOCK_LED
P101 P102
MSTAR_DEBUG_NEW 12507WS-04L C
12505WS-04A00
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
P103
10K
R147
1.8K
R148
1.8K
R127
1.8K
R128
1.8K
R129
1.8K
R130
1.8K
R133
1.8K
R134
1.8K
R135
1.8K
R136
1.8K
R131
1.8K
R132
1.8K
R183
1.8K
R184
1.8K
R185
1.8K
R186
1.8K
OPT
12507WS-04L
OPT
LOCKAn_OSD LOCKAn_OSD
R171
1
R149
R151
R153
1
R150
R152
R154
R169
R159
R160
10K
R170
+3.3V_NORMAL
I2C_SDA8 /TU_RESET1
1 I2C for SIL9617
2 2 SOC_RX I2C_SCL8 /TU_RESET2
R192
VBY1_LOCK_LED
R139
I2C_SDA7
I2C for Main Amp & LCD Module
22
2
VBY1_LOCK_LED
I2C_SCL7 RF_SWITCH_CTL
DDCA_CK 3 3
I2C_SDA6
SML-512UW
I2C for R9531AN AMP_RESET_N
VBY1_LOCK_LED
LD101
3 I2C_SCL6
TCON_I2C_EN
4 4 SOC_TX I2C_SDA1
DDCA_DA I2C for NVRAM /USB_OCD2
I2C_SCL1 USB_CTL2
R172
220
4 5
5 I2C_SDA_MICOM_SOC /USB_OCD3
I2C_SCL_MICOM_SOC USB_CTL3
5 E Q101
I2C_SDA4 M_RFModule_RESET
I2C for URSA9 (URSA9 Only) MMBT3906(NXP)
I2C_SCL4
PCM_5V_CTL VBY1_LOCK_LED
B
I2C_SDA5
I2C_SCL5 I2C for tuner C
I2C_SDA2
I2C for tuner&LNB
I2C_SCL2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14 SYSTEM 01
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
IC100
IC100 LGE4331
LGE4331
+1.1V_VDDC
N15 AA11
K10
K11
VDDC_1 GND_1
A14
A17
N16
GND_141
GND_142
GND_271
GND_272
AA12 +1.1V_Bypass Cap
VDDC_2 GND_2 N17 AA14
L10 A20 GND_143 GND_273
VDDC_3 GND_3 N18 AA16 +1.1V_VDDC +1.1V_AVDDL_MOD
L11 A23 GND_144 GND_274 +1.1V_CORE +1.1V_VDDC
VDDC_4 GND_4 N23 AA17
M10 A26 GND_145 GND_275
VDDC_5 GND_5 N24 AA18 L201 L208
M11 A29
VDDC_6 GND_6 GND_146 GND_276 MLB-201209-0120P-N2 BLM18SG700TN1D
T10 B12 N25 AA19
VDDC_7 GND_7 GND_147 GND_277
T11 B14 N26 AA25
0.1uF
0.1uF
VDDC_8 GND_8 GND_148 GND_278
U10 B31 P8 AA26
5A 4A
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDDC_9 GND_9 GND_149 GND_279
U11 C3 P9 AB8
VDDC_10 GND_10 C221 C228
V10 C11 GND_150 GND_280
VDDC_11 GND_11
P10 AB9 10uF 10uF
V11 C12 GND_151 GND_281 10V
C275
C277
P11 AB12 10V
C232
C235
C242
C248
C254
C258
C262
C266
C270
C273
VDDC_12 GND_12
AB10 C13 GND_152 GND_282
VDDC_14 GND_13 P12 AB13
AB11 C14 GND_153 GND_283
VDDC_15 GND_14 P13 AB14
AC10 C31 GND_154 GND_284
VDDC_17 GND_15 P14 AB17
+1.1V_DVDD_DDR AC11 C32
VDDC_18 GND_16 GND_155 GND_285
AA15 D17 P15 AB18
VDDC_13 GND_17 GND_156 GND_286
AB15 D20 P16 AB19 +1.1V_DVDD_DDR
VDDC_16 GND_18 GND_157 GND_287
AC15 D24 P17 AB25
+1.1V_AVDDL_MOD VDDC_19 GND_19 GND_158 GND_288 +1.15V_CPU +1.1V_VDDC_CPU
AB16 D27 P18 AB26
AVDDV_DVI GND_20 GND_159 GND_289
D31 P23 AB27 L202
GND_21 GND_160 GND_290 L207
W21 D32 BLM18SG700TN1D
AVDDL_MOD_1 GND_22 P24 AB28 BLM18PG121SN1D
W20 E1 GND_161 GND_291
AVDDL_MOD_2 GND_23 P25 AB29
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
E29 GND_162 GND_292
GND_24 P26 AB30
4A
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
M12
AVDDL_SSUSB_1 GND_25
E30
P29
GND_163 GND_293
AC7 2A
1uF
M13 E31 C284 C229
AVDDL_SSUSB_2 GND_26 GND_164 GND_294
F21 P32 AC8 10uF 10uF
GND_165 GND_295
C276
C278
C279
C280
C281
C282
C283
GND_27 10V
F23 R8 AC9 10V
C233
C236
C243
C249
C255
C259
C263
C267
C271
C274
GND_28 GND_166 GND_296
+1.1V_VDDC_CPU F24 R9 AC12
GND_29 GND_167 GND_297
F25 R10 AC13
GND_30 GND_168 GND_298
Y20 F26 R11 AC14
VDDC_CPU_1 GND_31 GND_169
Y21 F27 GND_299
VDDC_CPU_2 GND_32 R12 AC16
Y22 F28 GND_170 GND_300
VDDC_CPU_3 GND_33 R13 AC17
Y23 G8 GND_171 GND_301
VDDC_CPU_4 GND_34 R14 AC18
Y24 G9 GND_172 GND_302
VDDC_CPU_5 GND_35 R15 AC19
AA20 G10
VDDC_CPU_6 GND_36 GND_173 GND_303
AA21 G11 R16 AC20
VDDC_CPU_7 GND_37 GND_174 GND_304
AA22 G12 R17 AC25
VDDC_CPU_8 GND_38 GND_175 GND_305
AA23 G13 R18 AC26
VDDC_CPU_9 GND_39 GND_176 GND_306
AA24 G14 R19 AC27
VDDC_CPU_10 GND_40 GND_177 GND_307
AB20 G15 R20 AC28
VDDC_CPU_11 GND_41 GND_178
AB21 G16 GND_308
VDDC_CPU_12 GND_42 R23 AC29
AB22 G17 GND_179 GND_309
AB23
VDDC_CPU_13
VDDC_CPU_14
GND_43
GND_44
G18
R24
R25
GND_180 GND_310
AC30
AC31
+3.3V_Bypass Cap
AB24 G19 GND_181 GND_311
VDDC_CPU_15 GND_45 R26 AD7
AC21 G20
VDDC_CPU_16 GND_46 GND_182 GND_312 +3.3V_NORMAL +3.3V_AVDD_DMPLL
AC22 G22 T7 AD8
VDDC_CPU_17 GND_47 GND_183 GND_313
AC23 G23 T8 AD9
VDDC_CPU_18 GND_48 GND_184 GND_314
AC24 G24 T9 AD10
VDDC_CPU_19 GND_49 GND_185 GND_315
G25 T12 AD11 L206
GND_50 GND_186 GND_316 BLM18PG121SN1D
L7 G26 T13 AD12
DVDD_NODIE GND_51 GND_187
C210 G27 GND_317
GND_52 T14 AD13
1uF G30 GND_188 GND_318
25V Y19
VSENSE
GND_53
GND_54
H3
T15
T16
GND_189 GND_319
AD14
AD15
2A C237
C250 C253
0.1uF 0.1uF
H7 GND_190 GND_320 C222 10uF
+1.1V_DVDD_DDR GND_55
H8 T17 AD16 10uF 10V
GND_56 GND_191 GND_321 10V
H9 T18 AD17
GND_57 GND_192 GND_322
N19 H10 T19 AD18
DVDD_DDR_1 GND_58 GND_193 GND_323
N20 H11 T20 AD19
DVDD_DDR_2 GND_59 GND_194 GND_324
P19 H12 T23 AD20
DVDD_DDR_3 GND_60 GND_195 GND_325
P20 H13 T24 AD21
DVDD_DDR_4 GND_61 +3.3V_AVDD33
H14 GND_196 GND_326
GND_62 T25 AD22
H15 GND_197 GND_327
+3.3V_AVDD33 GND_63 T26 AD23 L203
H16 GND_198 GND_328 BLM18PG121SN1D
GND_64 U8 AD24
H17 GND_199 GND_329
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
GND_65 U9 AD25
P7 H18
AVDD_NODIE GND_66 GND_200 GND_330
U12 AD26
R7
U7
AVDDP3P_ETH GND_67
H19
H20 U13
GND_201 GND_331
AD27 2A
AVDDP3P_USB GND_68 GND_202 GND_332
V7 H21 U14 AD28
C251
C256
C260
C264
C268
C272
C238
C244
AVDDP3P_DVI_1 GND_69 GND_203 GND_333
W7 H22 U15 AD29
+3.3V_AVDD_AU33 AVDDP3P_DVI_2 GND_70 GND_204 GND_334
AA7 H23 U16 AD30
AVDDP3P_DADC GND_71 GND_205
AB7 H24 GND_335
AVDDP3P_ADC GND_72 U17 AE8
+3.3V_AVDD_DMPLL AF7 H25 GND_206 GND_336
AVDD_AU33 GND_73 U18 AE9
AE7 H26 GND_207 GND_337
AVDD_EAR33 GND_74 U19 AE10
AF10 H27 GND_208 GND_338
AVDD_DMPLL GND_75 U20 AE11
J7 +3.3V_AVDD_AU33
GND_76 GND_209 GND_339
+3.3V_VDDP33 J8 U21 AE12
GND_77 GND_210 GND_340
J9 U22 AE13 L204
GND_78 GND_211 GND_341 BLM18PG121SN1D
J10 U23 AE15
GND_79 GND_212 GND_342
0.1uF
0.1uF
AF15 J11 U24 AE16
AVDD_MOD GND_80 GND_213 GND_343
AF14 J12 U25 AE17
AE14
AVDD_PLL
AVDD_LPLL
GND_81
GND_82
J13
U26
GND_214 GND_344
AE18
2A
AF12 J14 GND_215 GND_345
VDDP_1 GND_83 U29 AE19
C239
C245
J15 GND_216 GND_346
DVDD18_EMMC GND_84 U32 AE20
J16 GND_217 GND_347
+3.3V_VDDP33 GND_85 V8 AE21
J17
GND_86 GND_218 GND_348
AF17 J18 V9 AE22
VDDP_3318_A GND_87 GND_219 GND_349
AF18 J19 V12 AE23
VDDP_2 GND_88 GND_220 GND_350
J20 V13 AE24
GND_89 GND_221 GND_351
VDDC15_M0 J21 V14 AE25 +3.3V_VDDP33
GND_90 GND_222 GND_352
J22 V15 AE26
GND_91 GND_223 GND_353
L19 J23 L205
AVDD_DDR0_1 GND_92 V16 AE27
L20 J24 GND_224 GND_354 BLM18PG121SN1D
AVDD_DDR0_2 GND_93 V17 AE28
L21 J25 GND_225 GND_355
0.1uF
AVDD_DDR0_3 GND_94 V18 AE29
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
M19 J26 GND_226 GND_356
M20
AVDD_DDR0_4
AVDD_DDR0_5
GND_95
GND_96
K7 V19
V20
GND_227 GND_357
AF1
AF2
2A C240
M21 K8 10uF
AVDD_DDR0_6 GND_97 GND_228 GND_358
K9 V21 AF8 10V
C246
C252
C257
C261
C265
C269
GND_98 GND_229 GND_359
L22 K12 V22 AF9
AVDD_DDR1_1 GND_99 GND_230 GND_360
M22 K13 V23 AF13
AVDD_DDR1_2 GND_100 GND_231 GND_361
N21 K14 V24 AF19
AVDD_DDR1_3 GND_101 GND_232
N22 K15 GND_362
AVDD_DDR1_4 GND_102 V25 AF20
P21 K16 GND_233 GND_363
AVDD_DDR1_5 GND_103 V26 AF21
P22 K18 GND_234 GND_364
AVDD_DDR1_6 GND_104 W8 AF22
K19 GND_235 GND_365
AVDD5V_MHL GND_105 W9 AF23
K21
GND_106 GND_236 GND_366
AF6 K23 W10 AF24
AVDD_HDMI_5V_PC GND_107 GND_237 GND_367
K24 W11 AF25
GND_108 GND_238 GND_368
K25 W12 AF26
GND_109 GND_239 GND_369
D3 K26 W13 AF27
VDDC15_M0 GND_EFUSE GND_110 GND_240 GND_370
L8 W14 AF28
GND_111 GND_241 GND_371
L9
GND_112 W15 AF29
L12 GND_242 GND_372
0.22uF C211 GND_113 W16 AG1
L13 GND_243 GND_373
0.1uF C200 A11
GND_114
L14
W17
GND_244 GND_374
AG2 GND JIG POINT
AVDD04_DDR_A_1 GND_115 W18 AG3
B11 L15
0.1uF C201 0.22uF C212 AVDD04_DDR_A_2 GND_116 GND_245 GND_375
0.22uF C202
A13
B13
AVDD11_DDR_A_1 GND_117
L16
L24
W19
W22
GND_246 GND_376
AG7
AG8
+1.5V_Bypass Cap
AVDD11_DDR_A_2 GND_118 GND_247 GND_377
L25 W23 AG9 JP202
JP203
JP204
JP205
0.1uF C203 0.22uF C213 GND_119 GND_248 GND_378
L26 W24 AG27
0.1uF C204 GND_120 GND_249 GND_379
AB31 L29 W25 AH3
AVDD04_DDR_B_1 GND_121 GND_250
C205 AB32 L32 GND_380
0.22uF 0.22uF C214 AVDD04_DDR_B_2 GND_122 W26 AH4
AD31 M7 GND_251 GND_381 +1.5V_DDR VDDC15_M0
AVDD11_DDR_B_1 GND_123 Y7 AH5
0.22uF C206 AD32 M8 GND_252 GND_382
AVDD11_DDR_B_2 GND_124 Y8 AH6
M9 GND_253 GND_383
0.22uF C207 GND_125 Y9 AH7
M14 L200
GND_126 GND_254 GND_384
M17 M15 Y10 AH8
AVDD04_DDR_A_3 GND_127 GND_255 GND_385
0.22uF C215 M18 M16 Y11 AH9 BLM18PG121SN1D
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AVDD04_DDR_A_4 GND_128 GND_256 GND_386
L17 M23 Y12 AH30
0.22uF C216 AVDD11_DDR_A_3 GND_129 GND_257 GND_387
L18 M24 Y13 AJ6
AVDD11_DDR_A_4 GND_130 GND_258 GND_388
0.22uF C217 M25 Y14 AJ7
GND_131 GND_259 GND_389
C223
C224
C225
C226
C227
C230
C231
C234
C241
C247
M26
GND_132 Y15 AJ8
R22 N7 GND_260 GND_390
0.22uF C218 AVDD04_DDR_B_3 GND_133 Y16 AJ23
T22 N8 GND_261 GND_391
AVDD04_DDR_B_4 GND_134 Y17 AK5
R21 N9 GND_262 GND_392 5V_HDMI_3 AVDD5V_MHL
0.22uF C219 AVDD11_DDR_B_3 GND_135 Y18 AK8
T21 N10
AVDD11_DDR_B_4 GND_136 GND_263 GND_393
0.22uF C220 N11 Y25 AK29
+1.1V_AVDDL_MOD GND_137 GND_264 GND_394
N12 Y26 AL2
GND_138 GND_265 GND_395 R200
AE31 N13 Y29 AL3 10
AVDDL_MOD_3 GND_139 GND_266 GND_396
AE30 N14 Y32 AL4
AVDDL_MOD_4 GND_140 GND_267 GND_397
0.1uF C208 AA8 AL23
GND_268 GND_398
0.1uF C209 AA9 AM14
GND_269 GND_399
AA10
GND_270
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14 POWER 02
11/05/31
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
R336
100
Clock for MSD808KWD
HP_LOUT HP_LOUT_MAIN
R333
OPT C335 MAIN Clock(24Mhz)
22K
X-TAL_1
0.01uF
OPT
10pF
GND_1
XIN_MAIN
C330
2
1
R324
R335
24MHz
X300
1M
100
HP_ROUT HP_ROUT_MAIN
OPT
R334
3
4
C334
22K
0.01uF
X-TAL_2
GND_2
OPT
10pF
XOUT_MAIN
C331
System Clock for Analog block(24Mhz)
Close to Main soc
IC100
IC100
LGE4331
LGE4331
HDMI Input from URSA9
V2
HDMI_RX0- RXA0N R312 68 0.047uF C316 AC2 AM13
W3 RIN0M TN EPHY_TDN
HDMI_RX0+ RXA0P R313 33 0.047uF C317 AC3 AK13
W2 AJ2 SC_R
R314 68 C318 RIN0P TP EPHY_TDP
HDMI_RX1- RXA1N LINE_IN_0L COMP1/AV1/DVI_L_IN 0.047uF AB2 AK12
Y3 AJ1 2.2uF C302 33 C319 GIN0M RN EPHY_RDN
HDMI_RX1+ RXA1P LINE_IN_0R COMP1/AV1/DVI_R_IN R315 0.047uF AB3 AL13
Y2 AK3 2.2uF C303 SC_G GIN0P RP EPHY_RDP
HDMI_RX2- RXA2N LINE_IN_2L SC_L_IN R316 68 0.047uF C320 AA1
Y1 AK1 2.2uF C304 BIN0M
HDMI_RX2+ RXA2P LINE_IN_2R SC_R_IN R317 33 0.047uF C321 AA3
V3 2.2uF C305 SC_B BIN0P
HDMI_CLK- RXACKN C322 AA2
V1 1000pF
SOGIN0
HDMI_CLK+ RXACKP AE5 AM11
R300 22 AC4 AH2 SC_ID HSYNC0 ET_TX_CLK/GPIO76
HDMI_TX_DDC_CLK DDCDA_CK/GPIO35 LINE_OUT_0L SCART_Lout AD6 AL9
R301 22 AE4 AJ3 SC_FB VSYNC0 ET_COL/GPIO72
HDMI_TX_DDC_SDA DDCDA_DA/GPIO36 LINE_OUT_0R SCART_Rout AK9
AD5 AJ4 ET_MDC/GPIO78
HOTPLUGA/GPIO31 EAR_OUT_L HP_LOUT R318 68 0.047uF C323 AF3 AL12
AJ5 RIN1M ET_TX_EN/GPIO75
EAR_OUT_R HP_ROUT R319 33 0.047uF C324 AE2 AL11
R2 COMP1_Pr 68 0.047uF RIN1P ET_TXD[0]/GPIO74
RXB0N R320 C325 AE3 AK11
T3 33 0.047uF GIN1M ET_TXD[1]/GPIO73
RXB0P R321 C326 AD2 AM10
T2 COMP1_Y
R322 68 0.047uF GIN1P ET_RXD[0]/GPIO77
RXB1N C327 AD3 AK10
U3 Y6 BIN1M ET_RXD[1]/GPIO80
RXB1P ARC0 HDMI_ARC R323 33 0.047uF C328 AC1 AL10
U2 COMP1_Pb BIN1P ET_MDIO/GPIO79
RXB2N 1000pF C329 AD1
U1 SOGIN1
RXB2P
R3
RXBCKN
R1 AK2
RXBCKP AUVAG H2
AC6 AK4 C332 HWRESET SOC_RESET
I2C_SCL8 DDCDB_CK/GPIO37 AUVRM 1uF
AB4 10uF
C333
I2C_SDA8 DDCDB_DA/GPIO38 10V AM3
AC5 XIN XIN_MAIN
HOTPLUGB/GPIO32 AM4
BLM18PG121SN1D XOUT XOUT_MAIN
J2 L300
RXC0N H1
K3 IRIN
RXC0P
K2 B10
RXC1N I2S_IN_BCK/GPIO92
L3 C9
RXC1P I2S_IN_SD/GPIO93 R325
L2 B9
RXC2N I2S_IN_WS/GPIO91 G2 2.2
L1 R326 USB_DM3
R304 USB0_DM 2.2
RXC2P G3 R327
J3 A7 22 R308 68 USB0_DP USB_DP3
R306 AUD_SCK C312 0.047uF AE6 AL14 2.2
RXCCKN I2S_OUT_BCK/GPIO98 22 R328
J1 C7 R305 VCOM USB1_DM WIFI_DM
RXCCKP I2S_OUT_MCK/GPIO97 AUD_MASTER_CLK AK14 2.2
Y4 A8 22 R329 WIFI_DP
R307 AUD_LRCK USB1_DP 2.2
DDCDC_CK/GPIO39 I2S_OUT_WS/GPIO96 R309 33 C313 0.047uF AF4 F2 R330
Y5 B8 22 TU_CVBS CVBS0 USB2_DM USB_DM2
DDCDC_DA/GPIO40 I2S_OUT_SD/GPIO99 AUD_LRCH R310 33 C314 0.047uF AF5 F3 2.2
AA5 C8 SC_CVBS_IN CVBS1 USB2_DP USB_DP2
HOTPLUGC/GPIO33 I2S_OUT_SD1/GPIO100 R311 33 C315 0.047uF AG5 E3
B7 C307 C309 AV1_CVBS_IN CVBS2 USB3_DM
I2S_OUT_SD2/GPIO101 F1
M2 C4 22pF 22pF USB3_DP
RXD0N I2S_OUT_SD3/GPIO102
N3
RXD0P C308 C310 C311
N2 22pF 22pF 1000pF
RXD1N 50V B2
P3 OPT USB_SSTXP
RXD1P C2 R331
P2 USB_SSTXN
RXD2N C1 2.2
P1 R332
USB_DM 2.2 USB_DM1
RXD2P D2
M3 USB_DP USB_DP1
RXDCKN AG6 D1
M1 DTV/MNT_V_OUT CVBSOUT1 USB_SSRXP
RXDCKP E2
AA6 USB_SSRXN
DDCDD_CK/GPIO41
AB6
DDCDD_DA/GPIO42
AB5 N4
HOTPLUGD/GPIO34 GPIO_PM14/GPIO24 MHL_DET_LM14
M5
GPIO_PM15/GPIO25
W4 M6
CEC/GPIO5 GPIO_PM16/GPIO26 /MHL_OCP
D10
SPDIF_IN/GPIO94
E10
SPDIF_OUT SPDIF_OUT/GPIO95
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14 INPUT 03
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
M0_DDR_VREFDQ M0_1_DDR_VREFDQ M1_DDR_VREFDQ M1_1_DDR_VREFDQ
IC400 IC401 IC403 IC404
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC
EAN63053201 EAN63053201 EAN63053201 EAN63053201
N3 DDR3 M8 M0_DDR_A0
N3
A0
DDR3 VREFCA
M8 N3 DDR3 M8 M1_DDR_A0
N3
A0
DDR3 VREFCA
M8
M0_DDR_A0 A0 VREFCA P7 M1_DDR_A0 A0 VREFCA P7
M0_DDR_A1
P7
4Gbit M0_DDR_A1 A1
4Gbit P7
4Gbit M1_DDR_A1 A1
4Gbit
A1 P3 M1_DDR_A1 A1 P3
M0_DDR_A2
P3
A2 (x16) M0_DDR_A2 A2 (x16) M1_DDR_A2
P3
A2 (x16) M1_DDR_A2 A2 (x16)
N2 H1 N2 H1 N2 H1 N2 H1
M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ M1_DDR_A3 M1_DDR_A3 A3 VREFDQ
P8 A3 VREFDQ P8
P8 M0_DDR_A4 P8 M1_DDR_A4
M0_DDR_A4 A4 A4 M1_DDR_A4 A4 A4
P2 P2 P2 P2
M0_DDR_A5 A5 M0_DDR_A5 A5 M1_DDR_A5 M1_DDR_A5 A5
R8 L8 R403 A5 R8 L8 R419
R8 L8 R400 240 M0_DDR_A6 240 R8 L8 R404 240 M1_DDR_A6 240
M0_DDR_A6 A6 ZQ A6 ZQ M1_DDR_A6 A6 ZQ A6 ZQ
R2 R2 R2 R2
M0_DDR_A7 VDDC15_M0 M0_DDR_A7 A7 VDDC15_M0 M1_DDR_A7 VDDC15_M0 M1_DDR_A7 A7 VDDC15_M0
A7 T8 A7 T8
T8 M0_DDR_A8 T8 M1_DDR_A8
M0_DDR_A8 A8 A8 M1_DDR_A8 A8 A8
R3 B2 R3 B2 R3 B2 R3 B2
M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1 M1_DDR_A9 M1_DDR_A9 A9 VDD_1
L7 D9 A9 VDD_1 L7 D9
L7 D9 M0_DDR_A10 L7 D9 M1_DDR_A10
M0_DDR_A10 A10/AP VDD_2 A10/AP VDD_2 M1_DDR_A10 A10/AP VDD_2 A10/AP VDD_2
R7 G7 R7 G7
DDR3 1.5V bypass Cap - Place these caps near Memory
R7 G7
DDR3 1.5V bypass Cap - Place these caps near Memory
R7 G7
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3 1.5V bypass Cap - Place these caps near Memory
M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 M1_DDR_A11 M1_DDR_A11 A11 VDD_3
N7 K2 A11 VDD_3 N7 K2
N7 K2 M0_DDR_A12 N7 K2 M1_DDR_A12
M0_DDR_A12 A12/BC VDD_4 A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4 A12/BC VDD_4
T3 K8 T3 K8 T3 K8 T3 K8
M0_DDR_A13 A13 VDD_5 M0_DDR_A13 A13 VDD_5 M1_DDR_A13 M1_DDR_A13 A13 VDD_5
T7 N1 A13 VDD_5 T7 N1
T7 N1 M0_DDR_A14 T7 N1 M1_DDR_A14
M0_DDR_A14 A14 VDD_6 A14 VDD_6 M1_DDR_A14 A14 VDD_6 A14 VDD_6
M7 N9 M7 N9 M7 N9 M7 N9
M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7 M1_DDR_A15 M1_DDR_A15 NC_5 VDD_7
R1 NC_5 VDD_7 R1
R1 R1
VDD_8 VDD_8 VDD_8 VDD_8
M2 R9 M2 R9 M2 R9 M2 R9
M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 M1_DDR_BA0 BA0 VDD_9
N8 BA0 VDD_9 N8
N8 M0_DDR_BA1 N8 M1_DDR_BA1
M0_DDR_BA1 BA1 BA1 M1_DDR_BA1 BA1 BA1
M3 M3 M3 M3
M0_DDR_BA2 BA2 M0_DDR_BA2 BA2 M1_DDR_BA2 M1_DDR_BA2 BA2
A1 BA2 A1
A1 A1
VDDQ_1 VDDQ_1 VDDQ_1 VDDQ_1
J7 A8 J7 A8 J7 A8 J7 A8
M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 M1_D_CLK M1_D_CLK CK VDDQ_2
K7 C1 CK VDDQ_2 K7 C1
K7 C1 M0_D_CLKN K7 C1 M1_D_CLKN
M0_D_CLKN CK VDDQ_3 CK VDDQ_3 M1_D_CLKN CK VDDQ_3 CK VDDQ_3
K9 C9 K9 C9 K9 C9 K9 C9
M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 M1_DDR_CKE M1_DDR_CKE CKE VDDQ_4
D2 CKE VDDQ_4 D2
D2 D2
VDDQ_5 VDDQ_5 VDDQ_5 VDDQ_5
L2 E9 L2 E9 L2 E9 L2 E9
M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 M1_DDR_CS1 M1_DDR_CS2 CS VDDQ_6
K1 F1 CS VDDQ_6 K1 F1
K1 F1 M0_DDR_ODT K1 F1 M1_DDR_ODT
M0_DDR_ODT ODT VDDQ_7 ODT VDDQ_7 M1_DDR_ODT ODT VDDQ_7 ODT VDDQ_7
J3 H2 J3 H2 C440 0.1uF J3 H2 J3 H2 C490 0.1uF
C410 0.1uF M0_DDR_RASN RAS VDDQ_8 C468 0.1uF M1_DDR_RASN RAS VDDQ_8
M0_DDR_RASN RAS VDDQ_8 K3 H9 M1_DDR_RASN RAS VDDQ_8 K3 H9
K3 H9 C411 0.1uF C441 0.1uF K3 H9 C469 0.1uF C491 0.1uF
M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 M1_DDR_CASN M1_DDR_CASN CAS VDDQ_9
L3 CAS VDDQ_9 L3
L3 M0_DDR_WEN L3 M1_DDR_WEN
M0_DDR_WEN WE WE M1_DDR_WEN WE WE
J1 J1 J1 J1
NC_1 NC_1 NC_1 NC_1
T2 J9 T2 J9 T2 J9 T2 J9
M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N RESET NC_2 M1_DDR_RESET_N M1_DDR_RESET_N RESET NC_2
L1 RESET NC_2 L1
L1 L1
NC_3 NC_3 NC_3 NC_3
L9 L9 L9 L9
NC_4 NC_4 NC_4 NC_4
F3 F3 F3 F3
M0_DDR_DQS0 DQSL M0_DDR_DQS2 DQSL M1_DDR_DQS0 M1_DDR_DQS2 DQSL
G3 DQSL G3
G3 M0_DDR_DQS_N2 G3 M1_DDR_DQS_N2
M0_DDR_DQS_N0 DQSL DQSL M1_DDR_DQS_N0 DQSL DQSL
C7 A9 C7 A9 C7 A9 C7 A9
M0_DDR_DQS1 DQSU VSS_1 M0_DDR_DQS3 DQSU VSS_1 M1_DDR_DQS1 M1_DDR_DQS3 DQSU VSS_1
B7 B3 DQSU VSS_1 B7 B3
B7 B3 M0_DDR_DQS_N3 B7 B3 M1_DDR_DQS_N3
M0_DDR_DQS_N1 DQSU VSS_2 DQSU VSS_2 M1_DDR_DQS_N1 DQSU VSS_2 DQSU VSS_2
E1 E1 E1 E1
VSS_3 VSS_3 VSS_3 VSS_3
E7 G8 E7 G8 E7 G8 E7 G8
M0_DDR_DM0 DML VSS_4 M0_DDR_DM2 DML VSS_4 M1_DDR_DM0 M1_DDR_DM2 DML VSS_4
D3 J2 DML VSS_4 D3 J2
D3 J2 M0_DDR_DM3 D3 J2 M1_DDR_DM3
M0_DDR_DM1 DMU VSS_5 DMU VSS_5 M1_DDR_DM1 DMU VSS_5 DMU VSS_5
J8 J8 J8 J8
VSS_6 VSS_6 VSS_6 VSS_6
E3 M1 E3 M1 E3 M1 E3 M1
M0_DDR_DQ0 DQL0 VSS_7 M0_DDR_DQ16 DQL0 VSS_7 M1_DDR_DQ0 M1_DDR_DQ16 DQL0 VSS_7
F7 M9 DQL0 VSS_7 F7 M9
F7 M9 M0_DDR_DQ17 F7 M9 M1_DDR_DQ17
M0_DDR_DQ1 DQL1 VSS_8 DQL1 VSS_8 M1_DDR_DQ1 DQL1 VSS_8 DQL1 VSS_8
F2 P1 F2 P1 F2 P1 F2 P1
M0_DDR_DQ2 DQL2 VSS_9 M0_DDR_DQ18 DQL2 VSS_9 M1_DDR_DQ2 M1_DDR_DQ18 DQL2 VSS_9
F8 P9 DQL2 VSS_9 F8 P9
F8 P9 M0_DDR_DQ19 F8 P9 M1_DDR_DQ19
M0_DDR_DQ3 DQL3 VSS_10 DQL3 VSS_10 M1_DDR_DQ3 DQL3 VSS_10 DQL3 VSS_10
H3 T1 H3 T1 H3 T1 H3 T1
M0_DDR_DQ4 DQL4 VSS_11 M0_DDR_DQ20 DQL4 VSS_11 M1_DDR_DQ4 M1_DDR_DQ20 DQL4 VSS_11
H8 T9 DQL4 VSS_11 H8 T9
H8 T9 M0_DDR_DQ21 H8 T9 M1_DDR_DQ21
M0_DDR_DQ5 DQL5 VSS_12 DQL5 VSS_12 M1_DDR_DQ5 DQL5 VSS_12 DQL5 VSS_12
G2 G2 G2 G2
M0_DDR_DQ6 DQL6 M0_DDR_DQ22 DQL6 M1_DDR_DQ6 M1_DDR_DQ22 DQL6
H7 DQL6 H7
H7 M0_DDR_DQ23 H7 M1_DDR_DQ23
M0_DDR_DQ7 DQL7 DQL7 M1_DDR_DQ7 DQL7 DQL7
B1 B1 B1 B1
VSSQ_1 VSSQ_1 VSSQ_1 VSSQ_1
D7 B9 D7 B9 D7 B9 D7 B9
M0_DDR_DQ8 DQU0 VSSQ_2 M0_DDR_DQ24 DQU0 VSSQ_2 M1_DDR_DQ8 M1_DDR_DQ24 DQU0 VSSQ_2
C3 D1 DQU0 VSSQ_2 C3 D1
C3 D1 M0_DDR_DQ25 C3 D1 M1_DDR_DQ25
M0_DDR_DQ9 DQU1 VSSQ_3 DQU1 VSSQ_3 M1_DDR_DQ9 DQU1 VSSQ_3 DQU1 VSSQ_3
C8 D8 C8 D8 C8 D8 C8 D8
M0_DDR_DQ10 DQU2 VSSQ_4 M0_DDR_DQ26 DQU2 VSSQ_4 M1_DDR_DQ10 M1_DDR_DQ26 DQU2 VSSQ_4
C2 E2 DQU2 VSSQ_4 C2 E2
C2 E2 M0_DDR_DQ27 C2 E2 M1_DDR_DQ27
M0_DDR_DQ11 DQU3 VSSQ_5 DQU3 VSSQ_5 M1_DDR_DQ11 DQU3 VSSQ_5 DQU3 VSSQ_5
A7 E8 A7 E8 A7 E8 A7 E8
M0_DDR_DQ12 DQU4 VSSQ_6 M0_DDR_DQ28 DQU4 VSSQ_6 M1_DDR_DQ12 M1_DDR_DQ28 DQU4 VSSQ_6
A2 F9 DQU4 VSSQ_6 A2 F9
A2 F9 M0_DDR_DQ29 A2 F9 M1_DDR_DQ29
M0_DDR_DQ13 DQU5 VSSQ_7 DQU5 VSSQ_7 M1_DDR_DQ13 DQU5 VSSQ_7 DQU5 VSSQ_7
B8 G1 B8 G1 B8 G1 B8 G1
M0_DDR_DQ14 DQU6 VSSQ_8 M0_DDR_DQ30 DQU6 VSSQ_8 M1_DDR_DQ14 M1_DDR_DQ30 DQU6 VSSQ_8
A3 G9 DQU6 VSSQ_8 A3 G9
A3 G9 M0_DDR_DQ31 A3 G9 M1_DDR_DQ31
M0_DDR_DQ15 DQU7 VSSQ_9 DQU7 VSSQ_9 M1_DDR_DQ15 DQU7 VSSQ_9 DQU7 VSSQ_9
+1.5V_Bypass Cap +1.5V_Bypass Cap +1.5V_Bypass Cap +1.5V_Bypass Cap
Close to DDR Power Pin Close to DDR Power Pin Close to DDR Power Pin Close to DDR Power Pin
VDDC15_M0 VDDC15_M0
VDDC15_M0 VDDC15_M0
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
OPT OPT OPT
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
OPT OPT OPT OPT OPT OPT OPT OPT OPT C4003
C4000 C4001 C4005 C4007 C4008
C4004 C4011 C4010 C4002 C4006 C4009 4th layer 10uF 1uF 0.1uF
10uF 1uF 0.1uF 10uF 1uF 0.1uF 4th layer 10uF 10V 4th layer
C475
C476
C480
C481
C484
C485
C486
C487
C488
C489
1uF 0.1uF 25V 16V
C412
C413
C415
C416
C418
C419
C420
C423
C438
C439
10V 10V 25V
C400
C401
C402
C403
C404
C405
C406
C407
C408
C409
4th layer
C444
C445
C446
C447
C448
C449
C450
C451
C452
C467
25V 16V 16V 10V 25V 16V
IC100 DDR_VTT DDR_VTT
LGE4331
AR400 AR407
100 100
1/16W 1/16W
F16 G28 C424 0.1uF C453 0.1uF
M0_DDR_A0 A_DDR3_A0 B_DDR3_A0 M1_DDR_A0 M0_DDR_A14 M1_DDR_A14
C16 J31
M0_DDR_A1 A_DDR3_A1 B_DDR3_A1 M1_DDR_A1 M0_DDR_A8 M1_DDR_A8
E16 H29
M0_DDR_A2 A_DDR3_A2 B_DDR3_A2 M1_DDR_A2 M0_DDR_A11 M1_DDR_A11
F17 J27 C425 0.1uF C454 0.1uF
M0_DDR_A3 A_DDR3_A3 B_DDR3_A3 M1_DDR_A3 M0_DDR_A6 M1_DDR_A6
B17 J30
M0_DDR_A4 A_DDR3_A4 B_DDR3_A4 M1_DDR_A4 AR401 AR408
E17 H28
M0_DDR_A5 A_DDR3_A5 B_DDR3_A5 M1_DDR_A5 100 100
A16 J32 1/16W 1/16W
M0_DDR_A6 A_DDR3_A6 B_DDR3_A6 M1_DDR_A6 C426 0.1uF C455 0.1uF
D16 G31 M0_DDR_A1 M1_DDR_A1
M0_DDR_A7 A_DDR3_A7 B_DDR3_A7 M1_DDR_A7
C15 H32 M0_DDR_A4 M1_DDR_A4
M0_DDR_A8 A_DDR3_A8 B_DDR3_A8 M1_DDR_A8
E15 F30 M0_DDR_A12 M1_DDR_A12
M0_DDR_A9 A_DDR3_A9 B_DDR3_A9 M1_DDR_A9 C427 0.1uF C456 0.1uF
B18 K30 M0_DDR_BA1 M1_DDR_BA1
M0_DDR_A10 A_DDR3_A10 B_DDR3_A10 M1_DDR_A10
B16 H30
M0_DDR_A11 A_DDR3_A11 B_DDR3_A11 M1_DDR_A11 AR402 AR409
D19 K29 100 100
M0_DDR_A12 A_DDR3_A12 B_DDR3_A12 M1_DDR_A12 1/16W 1/16W
F15 F31
M0_DDR_A13 A_DDR3_A13 B_DDR3_A13 M1_DDR_A13 C428 0.1uF C457 0.1uF
B15 H31 M0_DDR_RESET_N M1_DDR_RESET_N
M0_DDR_A14 A_DDR3_A14 B_DDR3_A14 M1_DDR_A14
E19 L28 M0_DDR_A13 M1_DDR_A13
M0_DDR_A15 A_DDR3_A15 B_DDR3_A15 M1_DDR_A15
E18 K28 M0_DDR_A7 M1_DDR_A7
M0_DDR_BA0 A_DDR3_BA0 B_DDR3_BA0 M1_DDR_BA0 C429 0.1uF C458 0.1uF
C17 K31 M0_DDR_A9 M1_DDR_A9
M0_DDR_BA1 A_DDR3_BA1 B_DDR3_BA1 M1_DDR_BA1
F18 J28 AR403 AR410
M0_DDR_BA2 A_DDR3_BA2 B_DDR3_BA2 M1_DDR_BA2
F20 M27 100 100 VDDC15_M0 M1_DDR_CKE
M0_DDR_RASN A_DDR3_RASZ B_DDR3_RASZ M1_DDR_RASN 1/16W 1/16W VDDC15_M0 M0_DDR_CKE
F19 L27 C430 0.1uF C459 0.1uF
M0_DDR_CASN A_DDR3_CASZ B_DDR3_CASZ M1_DDR_CASN M0_DDR_A5 M1_DDR_A5
E20 K27
M0_DDR_WEN A_DDR3_WEZ B_DDR3_WEZ M1_DDR_WEN M0_DDR_A2 M1_DDR_A2 R418 R433
G21 M28 R405
M0_DDR_ODT A_DDR3_ODT B_DDR3_ODT M1_DDR_ODT M0_DDR_A3 M1_DDR_A3 10K R422 10K
C18 L31 C431 0.1uF C460 0.1uF 10K
M0_DDR_CKE A_DDR3_CKE B_DDR3_CKE M1_DDR_CKE M0_DDR_A0 M1_DDR_A0 10K
F14 F32
M0_DDR_RESET_N A_DDR3_RST B_DDR3_RST M1_DDR_RESET_N
A19 M32 AR404 AR411 M0_DDR_RESET_N
M0_D_CLK A_DDR3_MCLK B_DDR3_MCLK M1_D_CLK 100 100 M1_DDR_RESET_N
B19 L30 1/16W 1/16W
M0_D_CLKN A_DDR3_MCLKZ B_DDR3_MCLKZ M1_D_CLKN
E14 F29 C432 0.1uF C461 0.1uF
M0_DDR_CS1 A_DDR3_CSB1 B_DDR3_CSB1 M1_DDR_CS1 M0_DDR_BA0 M1_DDR_BA0
D14 E32
M0_DDR_CS2 A_DDR3_CSB2 B_DDR3_CSB2 M1_DDR_CS2 M0_DDR_BA2 M1_DDR_BA2
M0_DDR_A15 M1_DDR_A15
C433 0.1uF C462 0.1uF M0_D_CLK M1_D_CLK
M0_DDR_A10 M1_DDR_A10 R412 R427
C22 R31 56 C477 C497
M0_DDR_DQ0 A_DDR3_DQ[0] B_DDR3_DQ[0] M1_DDR_DQ0 AR405 AR412 0.01uF 56 0.01uF
B21 N30 1% 1% 50V
M0_DDR_DQ1 A_DDR3_DQ[1] B_DDR3_DQ[1] M1_DDR_DQ1 100 100 50V
B23 R30 1/16W 1/16W
M0_DDR_DQ2 A_DDR3_DQ[2] B_DDR3_DQ[2] M1_DDR_DQ2 C434 0.1uF C463 0.1uF R413 R428
C20 N31 M0_DDR_WEN M1_DDR_WEN
M0_DDR_DQ3 A_DDR3_DQ[3] B_DDR3_DQ[3] M1_DDR_DQ3 56 56
B24 T30 M0_DDR_CASN M1_DDR_CASN 1% 1%
M0_DDR_DQ4 A_DDR3_DQ[4] B_DDR3_DQ[4] M1_DDR_DQ4
C19 M31 M0_DDR_RASN M1_DDR_RASN
M0_DDR_DQ5 A_DDR3_DQ[5] B_DDR3_DQ[5] M1_DDR_DQ5 C435 0.1uF C464 0.1uF
C23 T31 M0_DDR_ODT M1_DDR_ODT M0_D_CLKN M1_D_CLKN
M0_DDR_DQ6 A_DDR3_DQ[6] B_DDR3_DQ[6] M1_DDR_DQ6
C21 P31
M0_DDR_DQ7 A_DDR3_DQ[7] B_DDR3_DQ[7] M1_DDR_DQ7 AR406 AR413
B20 M30 100 100
M0_DDR_DM0 A_DDR3_DQM[0] B_DDR3_DQM[0] M1_DDR_DM0 1/16W 1/16W
A22 R32
M0_DDR_DQS0 A_DDR3_DQS[0] B_DDR3_DQS[0] M1_DDR_DQS0 C436 0.1uF C465 0.1uF
B22 P30 M0_DDR_CKE M1_DDR_CKE
M0_DDR_DQS_N0 A_DDR3_DQSB[0] B_DDR3_DQSB[0] M1_DDR_DQS_N0
M0_D_CLKN M1_D_CLKN
C437 0.1uF C466 0.1uF
F22 P28 M0_D_CLK M1_D_CLK
M0_DDR_DQ8 A_DDR3_DQ[8] B_DDR3_DQ[8] M1_DDR_DQ8
E24 T28
M0_DDR_DQ9 A_DDR3_DQ[9] B_DDR3_DQ[9] M1_DDR_DQ9
E21 N28
M0_DDR_DQ10 A_DDR3_DQ[10] B_DDR3_DQ[10] M1_DDR_DQ10
E25 U28
M0_DDR_DQ11 A_DDR3_DQ[11] B_DDR3_DQ[11] M1_DDR_DQ11
D22 N27
M0_DDR_DQ12 A_DDR3_DQ[12] B_DDR3_DQ[12] M1_DDR_DQ12 * DDR_VTT
D26 T27
M0_DDR_DQ13 A_DDR3_DQ[13] B_DDR3_DQ[13] M1_DDR_DQ13
D21 N29
M0_DDR_DQ14 A_DDR3_DQ[14] B_DDR3_DQ[14] M1_DDR_DQ14
D25 T29
M0_DDR_DQ15 A_DDR3_DQ[15] B_DDR3_DQ[15] M1_DDR_DQ15
E23 R28
M0_DDR_DM1 A_DDR3_DQM[1] B_DDR3_DQM[1] M1_DDR_DM1
D23 R27
M0_DDR_DQS1 A_DDR3_DQS[1] B_DDR3_DQS[1] M1_DDR_DQS1
E22 P27 VDDC15_M0
M0_DDR_DQS_N1 A_DDR3_DQSB[1] B_DDR3_DQSB[1] M1_DDR_DQS_N1 +3.3V_NORMAL
R401 IC402
C27 Y31 10K 1% TPS51200DRCR [EP] L401
M0_DDR_DQ16 A_DDR3_DQ[16] B_DDR3_DQ[16] M1_DDR_DQ16
C25 V31 UBW2012-121F
M0_DDR_DQ17 A_DDR3_DQ[17] B_DDR3_DQ[17] M1_DDR_DQ17 R402 C421
B28 Y30 10K 1000pF
M0_DDR_DQ18 A_DDR3_DQ[18] B_DDR3_DQ[18] M1_DDR_DQ18 REFIN VIN
A25 V32 1% 1 10
M0_DDR_DQ19 A_DDR3_DQ[19] B_DDR3_DQ[19] M1_DDR_DQ19
THERMAL
C28 AA30
M0_DDR_DQ20 A_DDR3_DQ[20] B_DDR3_DQ[20] M1_DDR_DQ20
11
C24 U31 VLDOIN PGOOD C443
M0_DDR_DQ21 A_DDR3_DQ[21] B_DDR3_DQ[21] M1_DDR_DQ21 2 9 VDDC15_M0 VDDC15_M0 VDDC15_M0
A28 AA31 4700pF VDDC15_M0
M0_DDR_DQ22 A_DDR3_DQ[22] B_DDR3_DQ[22] M1_DDR_DQ22
B26 V30 DDR_VTT M0_1_DDR_VREFDQ M1_1_DDR_VREFDQ
M0_DDR_DQ23 A_DDR3_DQ[23] B_DDR3_DQ[23] M1_DDR_DQ23 C422 VO GND
B25 U30 3 8 M0_DDR_VREFDQ M1_DDR_VREFDQ
M0_DDR_DM2 A_DDR3_DQM[2] B_DDR3_DQM[2] M1_DDR_DM2 22uF
B27 W30 10V
R431
1K 1%
R416
1K 1%
R425
1K 1%
M0_DDR_DQS2 A_DDR3_DQS[2] B_DDR3_DQS[2] M1_DDR_DQS2
R410
1K 1%
C26 W31 L400 PGND EN
M0_DDR_DQS_N2 A_DDR3_DQSB[2] B_DDR3_DQSB[2] M1_DDR_DQS_N2 4 7
UBW2012-121F
VOSNS REFOUT C479
D28 V28 5 6 C472 C470 C473
1%
1%
M0_DDR_DQ24 M1_DDR_DQ24 0.1uF
1%
A_DDR3_DQ[24] B_DDR3_DQ[24] 0.1uF 0.1uF
1%
C29 Y27 0.1uF C483 C478
R432
C414 C417 C442 R417 C471
R426
M0_DDR_DQ25 A_DDR3_DQ[25] B_DDR3_DQ[25] M1_DDR_DQ25 C474
R411
E26 U27 0.1uF 100uF 0.1uF 1000pF 1000pF 1000pF
M0_DDR_DQ26 M1_DDR_DQ26 1000pF 50V 50V
A_DDR3_DQ[26] B_DDR3_DQ[26] 50V
1K
1K
1K
D29 AA28 50V
1K
M0_DDR_DQ27 A_DDR3_DQ[27] B_DDR3_DQ[27] M1_DDR_DQ27
E28 W28
M0_DDR_DQ28 A_DDR3_DQ[28] B_DDR3_DQ[28] M1_DDR_DQ28
D30 AA29 Close to REFOUT pin
M0_DDR_DQ29 A_DDR3_DQ[29] B_DDR3_DQ[29] M1_DDR_DQ29
E27 V27
M0_DDR_DQ30 A_DDR3_DQ[30] B_DDR3_DQ[30] M1_DDR_DQ30
C30 AA27
M0_DDR_DQ31 A_DDR3_DQ[31] B_DDR3_DQ[31] M1_DDR_DQ31
B30 W27
M0_DDR_DM3 A_DDR3_DQM[3] B_DDR3_DQM[3] M1_DDR_DM3
A30 Y28
M0_DDR_DQS3 A_DDR3_DQS[3] B_DDR3_DQS[3] M1_DDR_DQS3
B29 W29
M0_DDR_DQS_N3 A_DDR3_DQSB[3] B_DDR3_DQSB[3] M1_DDR_DQS_N3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-10-28
UB83
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14 DDR 04
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+12V
PANEL_POWER TYP 6000mA Power_DET
MMBT3906(NXP)
+3.5V_ST
L509 L510
MLB-201209-0120P-N2 +12V +3.5V_ST R550
MLB-201209-0120P-N2 100K +3.5V_ST
PANEL_VCC
R501
1
10K PD_+12V PD_+3.5V
R500 R534 R545 R555
C521 C525 IC505
Q500
RL_ON 10K C523 0 10K
10uF Q503 2.7K
0.1uF 0.01uF AO4423
1% 5% APX803D29 OPT
25V 50V
2
EBK61313101
+3.3V_NORMAL 25V
EAG63590902 OPT POWER_DET
3
S1 D4
P500 1 AO4423 8 VCC 3 2 RESET
G+ SMAW200-H24S5 R509 S2 D3
R568 1K R525 C527 C528 2 7
C547 1
33 10K 10uF 10uF S3 D2
PD_+12V 0.1uF
3 6
R528 R531 GND
PWM_TOUT 25V 25V C531 C534 R535 16V
NON_G+ PWR ON INV CTL R507 100 INV_CTL G
4 5
D1 2K 2K 10uF 0.1uF 1.2K
1 2
L502 100 OPT OPT 25V 25V 1% C557
+3.5V_ST R561 100 PDIM#1 3 4 PDIM#2 R562
UBW2012-121F PWM_DIM PWM_DIM2 OPT 0.1uF
3.5V 5 6 GND OPT 16V
R569 R526
3.5V 3.5V 1.8K R556 not to RESET
C502 33 7 8 0 at 8kV ESD
0.1uF PWM_TIN GND 9 10 GND C529 5%
16V G+ C 10uF EBK61313102
PD_20_24V
12V 11 12 12V R518
Q503-*1
R549
25V AO4447A +24V
+12V 12V 12V 10K B Q502 100K
UBW2012-121F 13 14 PANEL_CTL OPT C533
L507 +24V 2SC3052 S_1
1 8
D_4
12V 15 16 GND AO4447
0.1uF
UBW2012-121F PD_20_24V
GND 24V E
S_2 D_3 16V
R516
2 7
17 18
OPT
C505 L503 PD_20V PD_24V IC506
24V 24V S_3 D_2
PD_UHD_24V
0.1uF 19 20 C518 3 6
R542-*2 R542-*1 R542 APX803D29
0
UBW2012-121F L508 5.6K 8.2K
50V 24V 21 22 24V 0.1uF 9.1K
UBW2012-121F G
4 5
D_1
1% 1%
GND GND 50V 1% R557 0 POWER_DET_1
23 24 VCC 3 2 RESET
L504
1 OPT
PD_UHD_24V PD_20V PD_24V C548 5%
25 GND
R543-*2 R543-*1 R543 0.1uF
1.6K 1.3K 1.5K 16V 24V-->3.48V
1% 1% 1% PD_20_24V 20V-->3.51V
+12V
12V-->3.58V
ST_3.5V-->3.5V
C515 C516 C517
10uF 10uF 10uF
16V 16V 16V
’14 UHD POWER +12V
+12V
Core 1.1V or 1.15V DDR +1.5V +1.5V_DDR
+1.15V_CPU L511 POWER_ON/OFF2_3
BLM18PG121SN1D
L514 POWER_ON/OFF2_4
BLM18PG121SN1D
C568
eMMC POWER C537 C567 IC504
C519
10uF
16V
0.1uF
10uF
IC507
0.1uF
+3.3V_NORMAL 3.3V_EMMC +1.8V DVDD18_EMMC 16V TPS54327DDAR R521
TPS54327DDAR [EP]GND
+3.3V_NORMAL EAN61832901 10K
R560
VBY1_LOCK_LED [EP]GND
10K
EN VIN
VBY1_LOCK_LED
1 8
L501 L505 R510 16V
THERMAL
EN VIN
ZD503
BLM18PG121SN1D BLM18PG121SN1D 10K 1 8 0.1uF
C553
5V
C526
R515
R1
11K
R517 R519 VFB VBST
9
THERMAL
0.1uF 2 7
R2-1.15V R547 16V
VBY1_LOCK_LED 10K VFB VBST R1 18K 3.6K L512
9
2 7
B
C504 C509 LD500 1% 1% 3.6uH
C506 C510 VREG5 SW
+3.5V_ST
0.1uF 0.1uF 1% L516 3 6
22uF 22uF
C542
16V 16V R539 3.6uH C520
100pF
10V 10V VREG5 SW 100pF SM-8040
50V
120K 3 6
C
E
R508 22 R514 1.5K 50V
Q501 1% SS GND
2SC3052
VBY1_LOCK_LED VBY1_LOCK_LED VBY1_LOCK_LED
+3.3V_NORMAL
SS GND
SM-8040
C555 R520
4
3A 5 C530
22uF
C532
22uF
R540
100K
R2-1.1V R558
4
3A 5
22uF
10V
C558
22uF
10V
22K
1%
C522 C524
10V 10V
1% 1uF 3300pF
16K C543 C545 10V 50V
R570 1% 1uF 3300pF
10K D 10V 50V Switching freq: 700K R2
2N7002A
R536
+1.8V - eMMC 4.51(LG1311-B0) VID0
G
R559
Vout=0.765*(1+R1/R2)=1.516V
Q504
0 5% 5.6K
1%
& Vx1 pull-up S
Vout=0.765*(1+R1/R2)=1.119V
Switching freq: 700K Vout=0.765*(1+R1/R2)=1.154V
+1.8V
+3.3V_NORMAL
IC501
AZ1117EH-ADJTRG1
EAN62868801
+5.0V normal & USB
1%
R544 150K 1%
R2
16K 1%
IN OUT C544
R506 2200pF C546 C549
16K
ADJ/GND
1 +24V 50V 100pF 0.047uF R552
ZD500
R504 6.8K
2.5V
50V 25V
OPT
75 R546
1%
R537
R541
1% 10K OPT
C511 C513
C569 C570 C556
10uF 10uF
RSET2
RSET1
R505 22uF 22uF 10uF
[EP]
AGND
RLIM
COMP
33 10V 10V
C551 R1 10V 10V 10V
FB
SS
1% L513
+1.1V or +1.13V _CORE 120-ohm 82pF
50V R553
28
27
26
25
24
23
22
51K
VIN_1 1 21 LX_3 L515 1%
THERMAL 4.7uH
VIN_2 2 29 20 LX_2
+1.1V_CORE VIN_3 LX_1 C550
C536
10uF
C538
10uF
C540
0.1uF
3 19
R548 0.047uF +5V_NORMAL
50V PGND_1 IC503 BST 0 25V
+12V 35V 35V 4 18
OPT
PGND_2
SN1302001(TPS65286RHDR)
SW_IN2
IC502 L518 5 17
BD86106EFJ
EAN62911501 C552
L517 2uH PGND_3 SW_IN1 R551 R554
MAX A BLM18PG121SN1D
EAN62653301 [EP] 6 16
100K 100K
1uF
PGND
1 8
SW_2
V7V 7 6A 15 NFAULT1 5% 5%
10V
+3.3V_NORMAL
/USB_OCD3
THERMAL
25V
1uF
10
11
12
13
14
C539
Placed on SMD-TOP
8
9
VIN SW_1 R533
9
2 7
+3.3V_NORMAL R565
C563 C566 C564 10K R1 0
MODE/SYNC
EN
SW_OUT2
SW_OUT1
SW_EN2
SW_EN1
NFAULT2
AGND EN
3 6 0.0068uF 10uF 1% 5%
C559 C560 C561 R563 50V 100uF
+12V 10uF 10uF 0.1uF 10V C565
6.8K
IC500 L506
16V 16V 16V
OPT
FB
4
6A 5
COMP
47pF
50V
L500 BD86106EFJ 2uH
ZD502
EAN62653301 [EP]
BLM18PG121SN1D
5V
/USB_OCD2
C541
+5V_USB_2
+5V_USB_3
USB_CTL2
USB_CTL3
PGND SW_2 POWER_ON/OFF2_4
10K
0.0068uF
R2-1.13V
R538
1 8
POWER_ON/OFF1
R564
THERMAL
R566 50V
Placed on SMD-TOP VIN SW_1 R511 C562 10K 10K
9
2 7
AGND EN
C508 C535 C512 C514
1.5K
1% R1
0.1uF
16V R573
1% Vout=0.6*(1+R1/R2)
3 6 0.0068uF 10uF 47pF
C500 C501 C503 R502 100uF 150K
10uF 10uF 0.1uF 50V 10V 50V R512 R567
20K OPT R2
16V 16V 16V
OPT
FB
4
6A 5
COMP
30K
1% +3.3V_NORMAL
1% 13K
1%
ZD501
R574
5V
180K
R2 1%
C507
R503
10K
POWER_ON/OFF2_1 R513 Vout=0.8*(1+R1/R2) R572
R2-1.1V
10K 10K D
2N7002A
0.1uF 1% R571
16V G
VID1
Q505
R1:10K/R2:23K, V=1.148V Voltage drop 0.042V 0 5%
S
R1:10K/R2:21.5K, V=1.172V Voltage drop 0.042V
Vout=0.8*(1+R1/R2)
POWER UP SEQUENCE
5V/3.3V->1.5V/1.1V->1.0V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 05
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Renesas MICOM
For Debug
+3.5V_ST
CAM_PWR_ON_CMD
12pF
12pF
MICOM_DEBUG
1K
10K
LOGO_LIGHT
Don’t remove R612,
MICOM_DEBUG
C602
C603
MICOM_DEBUG
LOGO_LIGHT
R611
MICOM_RESET
P600 not making float P40
R608
12507WS-04L
X600
1
32.768KHz +3.5V_ST
2
MICOM_DEBUG HDMI_WAUP:HDMI_INIT R616
3
4.7M
4
MICOM_RESET MHL_DET_LM14 OPT
TP601
5
10K
MHL_DET_LM14
10K
R615
POWER_DET_1
MICOM_RESET_SW
R618
GND SW600
JTP-1127WEM
2 1
22
270K
CAM_PWR_ON_CMD
OPT
C604
R619
P124/XT2/EXCLKS
0.47uF
+3.5V_ST 0.1uF
4 3
16V
P122/X2/EXCLK
P41/TI07/TO07
R617
C601
P137/INTP0
P120/ANI19
P40/TOOL0
CAM_RESET CAM_RESET
P123/XT1
C600
0.1uF
P121/X1
RESET
+3.5V_ST
REGC
VDD
VSS
R614
10K
LM14 Power SEQUENCE
48
47
46
45
44
43
42
41
40
39
38
37
P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
I2C_SCL_MICOM
POWER_ON/OFF!(5V) P61/SDAA0 P00/TI00/TXD1
I2C_SDA_MICOM
2 35 SCART_MUTE SCART_MUTE
P62 3 34 P01/TO00/RXD1 POWER_ON/OFF2_4
MODEL1_OPT_4 POWER_ON/OFF2_4
POWER_ON/OFF2_1(3.3V)
P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC600 P20/ANI0/AVREFP
POWER_ON/OFF2_1
WOL/WIFI_POWER_ON 5 32 KEY2
IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM
KEY1
POWER_ON/OFF2_3(1.5V)
P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2 R623
HDMI_CEC_MICOM EAN62632101 0
P73/KR3/SO01 8 29 P23/ANI3 OPT
MODEL1_OPT_5
POWER_ON/OFF2_4(1.1V) P72/KR2/SO21 P24/ANI4
POWER_ON/OFF2_3 9 28 MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5 MODEL1_OPT_3
EYE_SDA SIDE_HP_MUTE
SOC_RESET P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MODEL1_OPT_2
CAM_SLEEP CAM_SLEEP
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
TP600 MODEL1_OPT_1
13
14
15
16
17
18
19
20
21
22
23
24
R612
3.3K
R613
3.3K
EYE_Q
EYE_Q
+3.5V_ST
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION
MICOM MODEL OPTION
+3.5V_ST
0 1
MODEL_OPT_0 MICOM_NON_LOGO_LIGHT MICOM_LOGO_LIGHT
MICOM_LOGO_LIGHT
10K
10K
10K
10K
10K
10K
MICOM_LM14
MODEL_OPT_1
MICOM_GED
Reserved
OPT
OPT
OPT
R626
R600
R602
R604
R606
R609
MODEL_OPT_2 Reserved
22
22
MODEL_OPT_3
LM14
OPT
OPT
R629
R627
MODEL_OPT_4
MODEL1_OPT_0 Reserved
MODEL1_OPT_1 MODEL_OPT_5 NON_GED GED
MODEL1_OPT_2
MODEL1_OPT_3 POWER_DET
SOC_RX
AMP_MUTE
URSA_RESET_MICOM
URSA_RESET_MICOM
SOC_TX
INV_CTL
EDID_WP
MODEL1_OPT_4
POWER_ON/OFF1
LED_R
MODEL1_OPT_5
MICOM_NON_LOGO_LIGHT
MICOM_NON_GED
10K
10K
10K
10K
10K
10K
OPT
OPT
OPT
OPT
R631
R601
R603
R605
R607
R610
R630 For CEC
10K
LED_R
MICOM_LM14
EDID_WP
SOC_RESET
+3.5V_ST
LM14 : Active high reset
H13 : Active low reset R620 R621
27K 120K
G
D600
BAT54_SUZHO
HDMI_CEC HDMI_CEC_MICOM
D
S
Q600
RUE003N02
G
HDMI_CEC_FET_ROHM
Q600-*1
SI1012CR-T1-GE3
D
S
HDMI_CEC_FET_VISHAY
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 06
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
R9531 +1.0V
HDMI (HDMI1 HDCP2.2 / HDMI2 ARC / HDMI4 MHL) POWER_ON/OFF2_4
+3.3V_NORMAL IC3204
else : Max 0.7A
+1.0V_R9531
SPI FLASH (2MBit)
R3915
10K
AP2132MP-2.5TRG1 [EP]
1.8K
R3280
+3.3V_NORMAL
R3279 1 8 R2 IC3203
W25X20CLSNIG
THERMAL
PG GND
S3200 OPT10K C3239
R3281
1.2K
9
RAC33437501 2 7 R1 0.1uF
C3243
HDMI1 With HDCP2.2 DVDD10_R9531
0.1uF EN ADJ
SPI_CS_R9531
CS
1 8
VCC
R3278
3 6
VA3200 S3201
10K
5V_DET_HDMI_1 R3275 C3281
5V_HDMI_1 RAC33437501 R3297
CK-_HDMI_TX_R9531
VOUT 33 DO[IO1] HOLD
D2+_HDMI_TX_R9531
CK+_HDMI_TX_R9531
VIN
D0-_HDMI_TX_R9531
D0+_HDMI_TX_R9531
D1-_HDMI_TX_R9531
D1+_HDMI_TX_R9531
D2-_HDMI_TX_R9531
ESD_HDMI 120K C3240 2 7
SPI_DO_R9531
AR3208
SPI_CS_R9531 X3201
0.1uF
16V +5V_NORMAL
4 2A 5 0.1uF
SPI_DI_R9531
R3298 S3202 SPI_DO_R9531 27MHz VCTRL NC WP CLK
33 X-TAL_1 GND_2 3 6
33 RAC33437501 C3262 R9531_FLASH_WP SPI_CK_R9531
HDMI_HPD_1 R9531_XTAL_IN 1 4 EAN61387601 ZD3202
10uF
GND_1 X-TAL_2 10V 2.5V
2 3 R9531_XTAL_OUT OPT GND DIO[IO0]
C3267 4 5
S3203 AVDD33_R9531 CVDD10_R9531 DVDD10_R9531 SPI_DI_R9531
BODY_SHIELD VA3203 18pF
RAC33437501 50V C3241
ESD_HDMI AR3207 C3270
20 18pF 1uF
33
1/16W 50V
19 DDC_SDA_1_R9531 S3204
HOT_PLUG_DETECT RAC33437501
DDC_SCL_1_R9531
SDI_GPIO11
SDO_GPIO10
18
VDD[+5V] R3206
Vout=0.6*(1+R1/R2)
RSVDNC_36
RSVDNC_35
RSVDNC_34
RSVDNC_33
RSVDNC_32
RSVDNC_31
RSVDNC_30
RSVDNC_29
RSVDNC_28
1.8K R3220
SS_GPIO8
ARCRX_TX
CVDD10_3
17 3.3K
VA3207
IOVCC33
TDVDD10
TPVDD10
DDC/CEC_GND VA3204
OPT OPT
16
T0X2+
T0X2-
T0X1+
T0X1-
T0X0+
T0X0-
T0XC+
T0XC-
SDA
[EP]
15 Solder Preform +1.0V_R9531
CVDD10_R9531
SCL
14
Attach at R9531 thermal pad
L3210
RESERVED
HDMI_CEC BLM18PG121SN1D
13
CEC D3202
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
12 IP4294CZ10-TBR R3204 C3246 C3279 C3284 C3289
TMDS_CLK- 33 SCLK_GPIO9 1 75 XTALGND 10uF 10uF 0.1uF 0.1uF
11 SPI_CK_R9531 10V 10V 16V 16V
TMDS_CLK_SHIELD 1 10 GPIO5 2 74 XTALIN
10 CK-_HDMI1_R9531 THERMAL R9531_XTAL_IN
TMDS_CLK+ 2 9 SD0_IN_SPDIF0_IN 3 101 73 XTALOUT
9 CK+_HDMI1_R9531 R9531_XTAL_OUT
TMDS_DATA0- 3 8 GPIO6 4 72 XTALVCC33
XTAL_VCC33_R9531 APLL10_R9531
8 OPT
TMDS_DATA0_SHIELD 4 7 RSVDL_1 5 71 APLL10 L3207
D0-_HDMI1_R9531 APLL10_R9531
7 BLM18PG121SN1D
TMDS_DATA0+ 5 6 R0XC- RSVD_9 +5V_NORMAL
D0+_HDMI1_R9531 CK-_HDMI1_R9531 6 70
6 R3257 5.1
TMDS_DATA1- R0XC+ 7 69 TX_HPD0 4.7K R3284 C3244 C3282
5 D3203 CK+_HDMI1_R9531 10uF 0.1uF
R3263 5.1
TMDS_DATA1_SHIELD R0X0- TX_DSCL0 4.7K R3285
4
TMDS_DATA1+
IP4294CZ10-TBR D0-_HDMI1_R9531
D0+_HDMI1_R9531
R3264 5.1
R0X0+
8
9
IC3202 68
67 TX_DSDA0 1.8K R3293
10V 16V
3 1 10 R3273 5.1 1.8K R3296
TMDS_DATA2- D1-_HDMI1_R9531 R0X1- 10 66 RSVDNC_27 OPT DVDD10_R9531
2
1
TMDS_DATA2_SHIELD
2
3
9
8
D1+_HDMI1_R9531
D1-_HDMI1_R9531
D1+_HDMI1_R9531
R3274 5.1
R0X1+ 11 R9531AN 65 RSVDNC_26 R3912 0
DDC_SDA_1
DDC_SCL_1
L3211
BLM18PG121SN1D
R3276 5.1
TMDS_DATA2+
OPT R0X2- 12 64 RSVD_8 R3913 0
4 7 D2-_HDMI1_R9531 OPT
R3277 5.1 C3257 C3278 C3280 C3288 C3245 C3266
D2-_HDMI1_R9531 R0X2+ 13 63 RSVD_7 4.7K R3286
10uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF
5 6 D2+_HDMI1_R9531
05008WR-H19C. R3299 5.1 10V 10V 16V 16V 16V 16V
D2+_HDMI1_R9531 CVDD10_1 14 62 RSVD_6 4.7K R3287
JK3200 CVDD10_R9531
ESD_HDMI AVDD10_1 15 61 RSVDNC_25 AVDD33_R9531
VA3205 DVDD10_R9531
AVDD33_1 16 60 RSVD_5
AVDD33_R9531
RSVDNC_1 17 59 RSVD_4 4.7K R3288
RSVDNC_2 18 58 RSVD_3 4.7K R3290
RSVDNC_3 19 57 RSVDNC_24 HDMI_3.3V AVDD33_R9531
RSVDNC_4 20 56 RSVD_2 L3215
BLM18PG121SN1D
RSVDNC_5 21 55 RSVD_1 4.7K R3291
RSVDNC_6 22 54 CSDA 4.7K R3292 C3292 C3294 C3298 C3299 C3271 DDC pull-up
I2C_SDA6 10uF 10uF 0.1uF 0.1uF 0.1uF
RSVDNC_7 CSCL 33 R3236 10V 10V 16V 16V 16V
23 53 I2C_SCL6
RSVDNC_8 RSVDL_2 33 R3237
24 52 +5V_NORMAL +5V_NORMAL 5V_HDMI_2 +5V_NORMAL +5V_NORMAL
+3.5V_ST
RSVDNC_9 SBVCC5V 5V_HDMI_1
25 51 5V_HDMI_3
HDMI2 With ARC L3213
XTAL_VCC33_R9531
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
C3273 C3274
A1
A2
A1
A2
A1
A2
A1
A2
VA3201 BLM18PG121SN1D
5V_HDMI_2 5V_DET_HDMI_2 10uF 0.1uF
ESD_HDMI 10V 16V MMBD6100 MMBD6100 MMBD6100 MMBD6100
D3218 D3208 D3209 D3210
C3290 C3293
RSVDNC_10
RSVDNC_11
RSVDNC_12
RSVDNC_13
RSVDNC_14
RSVDNC_15
CVDD10_2
AVDD10_2
AVDD33_2
RSVDNC_16
RSVDNC_17
RSVDNC_18
RSVDNC_19
RSVDNC_20
RSVDNC_21
RSVDNC_22
RSVDNC_23
RESET_N
CI2CA_TPWR
INT
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
VCC33_OUT
C
C
C
C
10uF 0.1uF
R3223 10V 16V
33
HDMI_HPD_2 PWRMUX_OUT
AR3201
AR3200
AR3203
1/16W
1/16W
1/16W
BODY_SHIELD VA3209
47K
47K
47K
10K
4.7K
ESD_HDMI AR3202
20 33 R9531_RESET
1/16W C3276 C3277 DDC_SDA_1_R9531 DDC_SDA_2 DDC_SCL_MHL
+3.3V_NORMAL 10uF 0.1uF
DDC_SDA_2 3.3V Power Separation
DDC_SDA_1_R9531
DDC_SCL_1_R9531
R3283
R3282
HDMI_HPD_1
19
HOT_PLUG_DETECT S 10V 16V DDC_SCL_1_R9531 DDC_SDA_MHL
DDC_SCL_2
DDC_SCL_2 Q3202
18 PWRMUX_OUT CVDD10_R9531 DVDD10_R9531 AVDD33_R9531
VDD[+5V] R3207 SI1012CR-T1-GE3
1.8K R3221 5V_HDMI_2 G +3.3V_NORMAL +5V_NORMAL HDMI_3.3V
17 3.3K
AVDD33_R9531
DDC/CEC_GND VA3212 VA3214 D R3252
OPT 10K
R3230
OPT R3254
16
R3208
SDA 10
OPT
5V_HDMI_1
1K
10K
15 C3201 HDMI_ARC
SCL 1uF C3275 R3253
14 1uF 5.1K
R3231
10V OPT
G
RESERVED
3.9K
VA3216
OPT
HDMI_CEC ESD_HDMI C3202
13
CEC D3200 0.1uF
16V
12 IP4294CZ10-TBR
S
D
TMDS_CLK-
ARC AO3438
11 Q3204
TMDS_CLK_SHIELD 1 10 C3268 C3269
C3235
10 CK-_HDMI2_JACK 100uF 22uF
10uF
TMDS_CLK+ 2 9 6.3V 10V
10V
9 CK+_HDMI2_JACK
TMDS_DATA0- 3 8
8 OPT
TMDS_DATA0_SHIELD 4 7
7 D0-_HDMI2_JACK
TMDS_DATA0+ 5 6
D0+_HDMI2_JACK
6
TMDS_DATA1-
5 D3201
D0+_HDMI3_JACK
D0-_HDMI3_JACK
TMDS_DATA1_SHIELD
4
IP4294CZ10-TBR
TMDS_DATA1+
3 1 10 HDMI_3.3V 3.3V_Sil9617 Current Limit
TMDS_DATA2- D1-_HDMI2_JACK 5V_HDMI_3
+5V_NORMAL 5V_MHL
2 2 9
TMDS_DATA2_SHIELD D1+_HDMI2_JACK R3914
3 8 IC3207 BLM31PG500SN1
1
TMDS_DATA2+ 5V_MHL TPS2553DBV 50-ohm
OPT L3202 L3208
4 7 BLM18PG121SN1D BLM18PG121SN1D
D2-_HDMI2_JACK
5 6 IN OUT D3211
05008WR-H19C. 1 6
D2+_HDMI2_JACK
D2+_HDMI3_JACK
D2-_HDMI3_JACK
D1+_HDMI3_JACK
D1-_HDMI3_JACK
CK+_HDMI3_JACK
CK-_HDMI3_JACK
JK3201 C3218 C3249 ZD3200 30V From HDMI2&3_SIL9617
C3219 C3236
0.1uF 0.1uF 5V 1% OPT C3242
ESD_HDMI 22uF 0.1uF GND ILIM R3289
16V 16V OPT 2 5
VA3206 16V 10uF
10V 100K
20K 10V
D2+_HDMI_TX_MHL
R3295
EN FAULT D2-_HDMI_TX_MHL
MHL_DET 3 4
R3202 5.1
5.1
D1+_HDMI_TX_MHL
/MHL_OCP
R3294 D1-_HDMI_TX_MHL
R3203
+1.0V_R9531 3.3V_Sil9617
10K D0+_HDMI_TX_MHL
D0-_HDMI_TX_MHL
CK+_HDMI_TX_MHL
/MHL_OCP TP3203 CK-_HDMI_TX_MHL
AVDD10_2
[EP]GND
VDD33_2
RSVD_16
RSVD_15
RSVD_14
RSVD_13
RSVD_12
RSVD_11
RSVD_10
VDD33_1
RSVD_9
R1X2P
R1X2N
R1X1P
R1X1N
R1X0P
R1X0N
R1XCP
R1XCN
C3203 C3209 C3210 C3211
0.1uF 0.1uF 0.1uF
10uF 16V
16V 16V
10V
HDMI3 With MHL
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
AVDD10_1 1 57 R0X2P
D2+_HDMI2_JACK
VA3202 RSVD_1 2 56 R0X2N
5V_HDMI_3 5V_DET_HDMI_3 THERMAL D2-_HDMI2_JACK
ESD_HDMI RSVD_2 3 55 R0X1P
77 D1+_HDMI2_JACK
RSVD_3 4 54 R0X1N
D1-_HDMI2_JACK
RSVD_4 5 53 R0X0P DDC_SDA_MHL +3.3V_MUX
R3225 D0+_HDMI2_JACK
33 RSVD_5 R0X0N R3255 5.1 DDC_SCL_MHL
6 52 D0-_HDMI2_JACK
HDMI_HPD_3_MHL
RSVD_6 R0XCP R3256 5.1
SCL_B OPT 0 R3504
SDA_A OPT 0 R3505
DDC_SCL_1
BODY_SHIELD VA3211
RSVD_7
RSVD_8
7
8
51
50 R0XCN
VDD10_2
CK+_HDMI2_JACK
CK-_HDMI2_JACK
TI 2:1 Mux DDC_SDA_1
9 49 PWRMUX_OUT_SIL9617 C3301 C3300
+3.3V_MUX
ESD_HDMI AR3204 VDD10_1 10 IC3206 48 ARC R3227 C3213 0.1uF 10uF +3.3V_MUX
20 +3.3V_NORMAL
[EP]GND
33 TAVDD10 SPDIF_IN 10K 10uF 16V 10V
1/16W 11 SIL9617 47
R3318
SDA_B
SCL_A
TX2P CSCL
3.3K
19 DDC_SDA_MHL D2+_HDMI_TX_MHL
TX2N
12 46
CSDA R3238 33
I2C_SCL8 IC3302 L13413
HOT_PLUG_DETECT D2-_HDMI_TX_MHL 13 45 BLM18PG121SN1D
I2C_SDA8 5V_HDMI_2
18
R3216
DDC_SCL_MHL
D1+_HDMI_TX_MHL
TX1P 14 44 PWRMUX_OUT R3239 33 +5V_NORMAL TS3DV642A0RUAR +3.3V_NORMAL
VDD[+5V] R3222
1.8K TX1N 15 43 SBVCC5 R3249 10 R3251
D1-_HDMI_TX_MHL MUX_EN
39
40
41
42
17 3.3K 10 From HDMI2&3_SIL9617 C3314
DDC/CEC_GND VA3213 VA3215 TX0P 16 42 R0PWR5V R3300 0 OPT OPT
OPT D0+_HDMI_TX_MHL D0+A 22uF
OPT TX0N CBUS_HPD0 38 1 VCC R3502 R3503
16 D0-_HDMI_TX_MHL 17 41 10V
SDA HDMI_HPD_2 C3220 R3250 10K 10K
TXCP 18 40 DSCL0 D2+_HDMI_TX_MHL D0-A 37 2 EN OPT
CK+_HDMI_TX_MHL DDC_SCL_2 1uF 5.1K
THERMAL
15 R3500 33
SCL TXCN 19 39 DSDA0 10V D2-_HDMI_TX_MHL D1+A SCL
CK-_HDMI_TX_MHL DDC_SDA_2 36 3 OPT RXBSCL_URSA9
43
14 D1+_HDMI_TX_MHL D1-A SDA R3501 33
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RESERVED 35 4 RXBSDA_URSA9
HDMI_CEC D1-_HDMI_TX_MHL
13 D2+A 34 5 D0+
CEC D3204 D0+_HDMI_TX_MHL
TPWR_CI2CA
RSVDL_1
INT
RESET_N
CD_SENSE
DSDA4[VGA]
DSCL4[VGA]
RSVDH_1
RSVDH_2
RSVDL_2
RSVDL_3
RSVDH_3
RSVDH_4
RSVDL_4
RSVDL_5
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
HDMI_RX2+_URSA9_0_RP
D2-A 33 6 D0- HDMI OUTPUT_0 DDC to URSA9
12 IP4294CZ10-TBR D0-_HDMI_TX_MHL HDMI_RX2-_URSA9_0_RP
TMDS_CLK- D3+A D1+
CK+_HDMI_TX_MHL 32 7 HDMI_RX1+_URSA9_0_RP
11
TMDS_CLK_SHIELD 1 10 5V_HDMI_3 CK-_HDMI_TX_MHL D3-A 31 8 D1- HDMI_RX1-_URSA9_0_RP
SIL9617_RESET
10 CK-_HDMI3_JACK
NC_2 30 9 NC_1 HDMI_RX0+_URSA9_0_RP
TMDS_CLK+ 2 9 R3320
CK+_HDMI3_JACK 10 D0+B D2+ HDMI_RX0-_URSA9_0_RP
9 D2+_HDMI_TX_R9531 29 10
TMDS_DATA0- 3 8 HDMI_CLK+_URSA9_0_RP
4.7K
D0-B D2-
R3210
D2-_HDMI_TX_R9531
8 OPT C3315 R3321
28 11 HDMI_CLK-_URSA9_0_RP
TMDS_DATA0_SHIELD 4 7 1uF 5.1K
D1+_HDMI_TX_R9531 B1+B 27 12 D3+ +3.3V_NORMAL
7 D0-_HDMI3_JACK
10V D1-_HDMI_TX_R9531
TMDS_DATA0+ 5 6 B1-B 26 13 D3-
D0+_HDMI3_JACK D0+_HDMI_TX_R9531
6
R3319
D2+B 25 14 HPD
10K
TMDS_DATA1- D0-_HDMI_TX_R9531
5 D3205 CK+_HDMI_TX_R9531 D2-B 24 15 CEC
TMDS_DATA1_SHIELD
HDMI_HPD_3_MHL
IP4294CZ10-TBR CK-_HDMI_TX_R9531 D3+B SEL1
DDC_SCL_MHL
23 16
DDC_SDA_MHL
4 SIL9617_INT
TMDS_DATA1+ +3.5V_ST +5V_NORMAL D3-B SEL2
+3.3V_NORMAL PWRMUX_OUT_SIL9617 22 17
3 1 10
TMDS_DATA2- D1-_HDMI3_JACK S From HDMI1_R9531AN
21
20
19
18
Q3203 HDMI_MUX_SEL
2 2 9
R3234
R3201
D1+_HDMI3_JACK SI1012CR-T1-GE3
10K
TMDS_DATA2_SHIELD
G R3224 R3226 R3229 R3246
10K
3 8
HPD_B
CEC_B
HPD_A
CEC_A
1 47K 47K 47K
MHL_DET
47K
TMDS_DATA2+ D
OPT E MMBT3906(NXP)
4 7 R3235
10K Q3205 +3.3V_NORMAL
D2-_HDMI3_JACK
05008WR-H19C. 5 6 B
D2+_HDMI3_JACK
JK3202 C C
R3200
R3209
R3228
SEL2(LM14_GPIO116) Function
R3212 5.1K
R3215 5.1K
1K B
R3211 47K
47K
47K
R3213 47K
MHL_DET
1/16W Q3201
Low CH A (HDMI2&3_SIL9617) enable
R3232
C3200 5% MMBT3904(NXP) E
(CD_SENCE)
180K
ESD_HDMI 0.1uF High CH B (HDMI1_R9531AN) enable
VA3208 16V
OPT
R3233
120K
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI JACK 07
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
SPDIF OUT +3.3V_NORMAL
JK801
JSTIB15
VIN A
Fiber Optic
VCC B
R800
33 GND C
SPDIF_OUT
VA800 C801 4
C800 5.5V 0.1uF
47pF 16V
SHIELD
50V OPT
COMPONENT 1 PHONE JACK
+3.3V_NORMAL
OPT
CVBS 1 PHONE JACK
C802
18pF +3.3V_NORMAL
R801
10K
R805
1K R812
COMP1_DET
47K
R816 E
10K
VA801 MMBT3906(NXP)
5.6V B Q800
C805
VA804 C
JK800 5.6V 0.1uF
AV1_CVBS_DET
PEJ038-3B6111 16V
5 M5_GND JK802 for audio Hum noise (L) R821
PEJ038-3B611 10K
5 M5_GND
4 M4 COMP1_Y
R817
ZD800 4 M4 10K
3 M3_DETECT COMP1/AV1/DVI_L_IN
COMP_ESD
R802
75 3 M3_DETECT VA802
1 M1 5.6V
ZD801 R810 C806 R819
COMP_LR_ZENER 1000pF
COMP_ESD 470K 50V 12K
1 M1 OPT
6 M6
6 M6
EAG61030017
R818
COMP1_Pb 10K
EAG61030016 COMP1/AV1/DVI_R_IN
ZD802
COMP_ESD VA803
R803
75 5.6V C807 R820
COMP_LR_ZENER R811 1000pF
470K 50V 12K
ZD803
OPT
COMP_ESD
COMP1_Pr
ZD804
COMP_ESD
R804
75 AV1_CVBS_IN
ZD805 ZD806 C808
COMP_ESD AV2_CVBS_ZENER_ROHM R814 47pF
75 50V
ZD807 1%
AV2_CVBS_ZENER_ROHM 3216
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AV&COMP JACK 08
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
P900
SMAW200-H18S5 L900
+3.3V_NORMAL
BLM18PG121SN1D
C909
C907 22uF
GND 1 2 +3.5V_WOL 0.1uF 10V
R908
M_RFModule_RESET
100 BT_RESET 3 4 USB_DM WIFI_DM
RCLAMP0502BA
C902
0.1uF NC 5 6 USB_DP
Place Near Wafer WIFI_DP
R909 +3.5V_ST
100 WOL 7 8 GND C906 C908
D900
WOL/WIFI_POWER_ON
5pF 5pF
R904
100
C903
0.1uF
SDA 9 10 GND OPT
50V 50V
R910 R911
EYE_SDA 10K 10K
R905 R912
EYE_SCL
100 SCL 11 12 KEY1 5% 5%
100
KEY1
+3.5V_ST R913
R907 GND 13 14 KEY2 100
10K KEY2
5%
IR 15 16 +3.5V_ST +3.5V_ST
IR
C904 C910 C911
100pF LED_R 17 18 GND C905
1000pF
0.1uF 0.1uF
OPT
50V 50V OPT
OPT
R906
1.8K
LED_R
OPT 19
GND
C901
0.1uF
16V
SMD bottom for ESD_UB8 10.5T
SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83_US
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M900 M901 M902 M903 M904 M905 M906 M907
MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225
SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_EMS_UB83 SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83
SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M908 M909 M910 M911 M912 M913 M914 GASKET_8.0X6.0X10.5H
M915 M916
MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225
MDS62110225
OPT
OPT OPT SMD_GASKET_for_ESD_UB83
GASKET_8.0X6.0X10.5H
M917 GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M923 M924 M925
MDS62110225
MDS62110225 MDS62110225 MDS62110225
only for proto board
SMD T0P for EMI_UB8 13.5T
IR
+3.5V_ST SMD_GASKET_for_ESD_UB83_US
SMD_GASKET_for_ESD_UB83_US GASKET_8.0X6.0X13.5H SMD_GASKET_for_ESD_UB83_US SMD_GASKET_for_ESD_UB83_US OPT
GASKET_8.0X6.0X13.5H M919 GASKET_8.0X6.0X13.5H GASKET_8.0X6.0X13.5H GASKET_8.0X6.0X13.5H
M918 M920 M921
MDS62110221 M922
MDS62110221 MDS62110221 MDS62110221 MDS62110221
IR_PROTO
IC900
IR_PROTO
AO-R123C7G-LG
1/16W
1/10W
R900
R901
IR_PROTO
OPT
330
SMD_GASKET_for_ESD_UB83_US
5%
47
5%
GASKET_8.0X6.0X13.5H SMD_GASKET_for_ESD_UB83 SMD_GASKET_for_ESD_UB83 OPT
GASKET_8.0X6.0X13.5H
GND M927 GASKET_8.0X6.0X13.5H GASKET_8.0X6.0X13.5H GASKET_8.0X6.0X13.5H
G M926
M928 M929 M930
MDS62110221 MDS62110221
MDS62110221 MDS62110221 MDS62110221
VS
V
OUT
O
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR/KEY/WIFI/BT 09
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+5V_USB_1 USB1 (2.0) +5V_USB_2 USB2 (2.0) +5V_USB_3
USB3 (2.0)
MAX 1.0A MAX 1.0A MAX 1.0A
3AU04S-385-ZC-(LG). 3AU04S-385-ZC-(LG).
3AU04S-385-ZC-(LG). JK1001 JK1002
JK1000
1
1
USB DOWN STREAM
USB DOWN STREAM
1
USB DOWN STREAM
2
2
USB_DM2 USB_DM3
2
USB_DM1
RCLAMP0502BA
RCLAMP0502BA
3
3
RCLAMP0502BA
USB_DP2 USB_DP3
3
USB_DP1
C1002 ZD1001
D1003
D1004
5V C1003
4
4
C1001 ZD1000 10uF ZD1002
D1000
5V
4
10uF 5V
10uF 10V
5
5
OPT 10V
10V OPT
5
OPT
OCP USB1
+5V_USB_1
+3.3V_NORMAL
+5V_NORMAL
IC1000
BD2242G
R1001 VIN VOUT
4.7K 1 6
C1000 GND ILIM
0.1uF 2 5
16V
14K
R1002
1%
EN OC
/USB_OCD1 3 4
USB_CTL1
R1000
10K
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
USB JACK 10
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
C1100 C1101 C1102 C1103
0.1uF 0.01uF 0.1uF 0.01uF
16V 50V 16V 50V
JK1100
BS-R570098
LAN_UDE
P1[CT]
1
P2[TD+]
2
EPHY_TDP
P3[TD-]
3
EPHY_TDN
P4[RD+]
4
EPHY_RDP
P5[RD-]
5
EPHY_RDN
VA1100 VA1101 VA1102 VA1103
P6[CT]
6
5.5V 5.5V 5.5V 5.5V
P7
7
P8
8
9
9 EMI
R1100
P10[GND] 0
10
P11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
12
SHIELD
JK1100-*1
TLA-6T764
LAN_TDK
R1
1
R2
2
R3
3
R4
4
R5
5
R6
6
R7
7
R8
8
R9
9
R10[GND]
10
R11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
12
SHIELD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LAN JACK 11
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Main AMP
+3.3V_NORMAL
R1213
AMP_RESET_N 100
L1201 C1227 L1202
1/16W 1000pF 10uH
BLM18PG121SN1D SPK_L+
50V
SP-7850_10
AUD_MASTER_CLK
50V
+24V_AMP
22000pF
R1205
C1206
5.6
+24V +24V_AMP 1/10W R1209
C1222
C1226 0.1uF
C1205 C1216 50V 4.7K
[EP]GND
10uF 390pF
L1200 0.1uF C1208 C1210 50V
VDD_IO
GND_IO
PGND1A
PVDD1A
PVDD1B
UBW2012-121F 10V 0.1uF
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
35V
C1220
0.47uF
50V
AD
C1217
390pF
50V
C1223 R1210
R1206
5.6
0.1uF
50V 4.7K
SPEAKER_L
40
39
38
37
36
35
34
33
32
31
1/10W
L1205
NC_1 1 30 OUT1B 10uH
SPK_L-
SP-7850_10
VDD_PLL 2 29 PGND1B C1212
THERMAL 22000pF
NC_2 3 41 28 BST1B 50V
C1203
1uF
10V GND 4 27 VDR1
NC_3 5 IC1200 26 NC_4
C1204
1uF
10V
DVDD 6 NTP7514 25 AGND
SDATA EAN62886101 VDR2
From DACLRCH AUD_LRCH 7 24
WCK
0x54 BST2A
C1214
1uF
C1215
1uF
AUD_LRCK 8 23 10V 10V
AUD_SCK
BCK 9 22 PGND2A C1213
22000pF
R1202
I2C_SDA7
100 SDA 10 21 OUT2A 50V
R1203
100
11
12
13
14
15
16
17
18
19
20
I2C_SCL7
C1201 C1202
33pF 33pF
L1203
50V 50V 10uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+
SP-7850_10
+3.3V_NORMAL +24V_AMP
R1207
5.6
1/10W C1224 R1211
R1201 0.1uF 4.7K
10K C1218 C1221 50V
C1211 390pF 0.47uF
R1204 C1209 0.1uF
50V
50V 50V
SPEAKER_R
10uF C1219
C 100 390pF
35V 50V
R1200 C1200 C1225 R1212
B Q1200 C1207
AMP_MUTE 1000pF R1208 0.1uF 4.7K
10K MMBT3904(NXP) 50V 22000pF 5.6 50V
E 1/10W L1204
50V
I2S_AMP
10uH
SPK_R-
SP-7850_10
I2S_AMP
WAFER-ANGLE
SPK_L+
4
SPK_L-
3
SPK_R+
2
SPK_R-
1
P1200
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN AMP 12
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
EARPHONE AMP
IC1400
TPA6138A2
+INR +INL
C1401 1 14 C1407
C1400 HP_OUT 180pF HP_OUT HP_OUT 180pF HP_OUT C1409
1uF R1400 R1402 R1404 R1406 1uF
10V 10K 43K -INR -INL 43K 10K 10V
2 HP_OUT 13
HP_ROUT_MAIN HP_OUT HP_OUT 1% HP_OUT HP_LOUT_MAIN
HP_BYPASS
HP_OUT
R1407
1% C1403
R1408
C1405 R1405
R1401
HP_BYPASS
10pF OUTR OUTL 10pF
33K 33K
50V 3 12 50V
0
0
HP_LOUT_AMP
HP_ROUT_AMP
+3.3V_NORMAL GND_1 UVP
4 11 +3.3V_NORMAL
MUTE GND_2 HP_OUT
4.7K 5 10 L1400
R1403
HP_OUT 120-ohm
SIDE_HP_MUTE VSS VDD BLM18PG121SN1D
6 9
HP_OUT HP_OUT
HP_OUT C1406 C1408
C1402 CN CP 1uF 0.1uF
1uF 7 8
10V 16V
10V
C1404
1uF
10V
HP_OUT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR HEADPHONE AMP
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 14
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
Signal to Signal Width = 12mils
+3.3V_TU Ground Width >= 24mils
L1500
BLM18PG121SN1D
close to TUNER
+3.3V_LNA_TU
1
C1500
0.1uF R1514 1K
2 RF_SWITCH_CTL_TU RF_SWITCH_CTL
C1503 R1508
0.1uF 10K
close to Tuner +3.3V_NORMAL +3.3V_TU
R1513 100
3 IF_AGC_TU IF_AGC
C1501
0.1uF
16V +3.3V_TU L1505
BLM18PG121SN1D
R1511 33
I2C_SCL5_TU I2C_SCL5
4 C1504
15pF L1504
50V R1510 33 C1511 BLM18PG121SN1D
I2C_SDA5_TU I2C_SDA5 0.1uF
5 C1502 OPT
16V 1608 perallel
15pF because of derating C1519
C1520
50V 0.1uF
ATV_OUT
22uF 16V
OPT OPT 10V
R1517 R1518
200 200
R1504 10
6 IF_P_TU IF_P
R1523
should be guarded by ground,Match GND VIA L1501
OPT TU_CVBS
100
R1505 10
EU
7 IF_N_TU IF_N
E
8 TU_CVBS_TU
B Q1500
TU_SIF MMBT3906(NXP)
R1509 150 C
9 TU_SIF_TU
+3.3V_TU
L1502
BLM18PG121SN1D T2 : Max 1.7A
else : Max 0.7A
11 +3.3V_TUNER
C1509
R1507 0 0.1uF
FE_DEMOD1_TS_ERROR_TU FE_DEMOD1_TS_ERROR TU_Q/N/M/W
12 D_Demod_Core_1
+3.3V_NORMAL IC1500
0 FE_DEMOD1_1 AP2132MP-2.5TRG1 [EP]
TU_1.2V
R1501
R1522-*1 R1521-*1
14 FE_DEMOD1_1_TS_CLK FE_DEMOD1_TS_CLK
R1521
1/16W
FE_DEMOD1_TS_ERROR
TU_1.1V TU_1.1V
10K
1/16W
1%
TU_Q/N/M/W 1 8 R2
18K
15 FE_DEMOD1_TS_SYNC FE_DEMOD1_TS_SYNC
1%
TU_Q/N/M/W C1515
THERMAL
0.1uF PG GND
C1513
TU_1.2V
R1522
1/16W
0.1uF
9
2 7 R1
1/16W
16 FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL
10K
16V TU_Q/N/M/W
1%
ADJ
15K
R1520 EN
1%
10K
R1502 0 FE_DEMOD1_1 3 6
17 FE_DEMOD1_1_TS_DATA[0]
VIN VOUT
18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[0-7]
+5V_NORMAL 4 2A 5
VCTRL NC
FE_DEMOD1_TS_DATA[0] EAN61387601
19 FE_DEMOD1_TS_DATA[2] FE_DEMOD1_TS_DATA[1] TU_Q/N/M/W
C1516
FE_DEMOD1_TS_DATA[2] 10uF
FE_DEMOD1_TS_DATA[3] TU_Q/N/M/W 10V
20 FE_DEMOD1_TS_DATA[3]
C1514
1uF
FE_DEMOD1_TS_DATA[4]
21 FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
Global F/E Option Name
1. TU
22 FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[7]
Vout=0.6*(1+R1/R2)
2. Tuner Name = TDS’S’,TDS’Q’...
23 FE_DEMOD1_TS_DATA[6]
3. Country Name = T,T2,S2,KR,US,BR ...
Example of Option name 24 FE_DEMOD1_TS_DATA[7]
TU_Q_T2 = apply TDSQ type tuner and T2 country R1519
100 /TU_RESET1
TU_M/W = apply TDSM&TDSW Type Tuner 25 /TU_RESET1_TU
L1503 +3.3V_TU
C1512
BLM18PG121SN1D 16V
13’ Tuner Type for Global 26 +3.3V_DEMOD_TU 0.1uF
TDS’S’-G501D : T/C Half NIM Horizontal Type R1516 C1510
TDS’Q’-G501D : T/C/S2 Combo Horizontal type 33 0.1uF
27 I2C_SCL2_TU
TDS’Q’-G601D : T2/C/S2 Combo Horizontal Type L1506 D_Demod_Core_1
C1507
TDS’Q’-G651D : T2/C/S2 Combo Vertical Type BLM18PG121SN1D
15pF
I2C_SCL2
TDS’M’-C601D : China NIM with Isolater Type 28 D_Demod_Core 50V
OPT
TDS’W’-J551F : Japan Dual NIM C1505
0.1uF
TDS’W’-B651F : Brazil 2Tuner 29 LNB_TX LNB_TX
TDS’W’-A651F : Taiwan 2Tuner R1515
TDS’W’-K651F : Colombia DVB-T2 2Tuner 33
30 I2C_SDA2_TU
C1508
15pF I2C_SDA2
LNB_OUT 50V
31 LNB_OUT OPT
C1517 C1518
0.1uF 18pF
LNB LNB
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU CIRCUIT 15
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
DEV_TDJM_G251D DEV_TDJM_H151F DEV_TDJM-K151F DEV_TDJH_H251F DEV_TDJK-T151F
TU1602 TU1603 TU1607 TU1604 TU1606
TDJM-G251D TDJM-H151F TDJM-K151F TDJH-H251F TDJK-T151F
EBL61400503 EBL61400602 EBL61400802 EBL61380102 EBL61400002
B1[+3.3V] B1[+3.3V] B1[+3.3V] B1[+3.3V] B[+3.3V]
1 1 1 1 1 +3.3V_LNA_TU
NC_1 NC_1 RF_SW_CTL NC RF_SW_CTL
2 2 2 2 2 RF_SWITCH_CTL_TU
NC_2 M_DIF_AGC AIF_AGC DIF_AGC IF_AGC
3 3 3 3 3 IF_AGC_TU
SCL_RF SCL_RF SCL_RF SCL SCL
4 4 4 4 4 I2C_SCL5_TU
SDA_RF SDA_RF SDA_RF SDA SDA
5 5 5 5 5 I2C_SDA5_TU
NC_3 M_DIF[P] AIF[P] DIF[P] IF[P]
6 6 6 6 6 IF_P_TU
NC_4 M_DIF[N] AIF[N] DIF[N] IF[N]
7 7 7 7 7 IF_N_TU
SIF S_SIF NC_1 SIF NC_1
8 8 8 8 8 TU_SIF_TU
CVBS S_CVBS NC_2 CVBS NC_2
9 9 9 9 9 TU_CVBS_TU
NC_5 NC_2 NC_3
10 10 10
B2[+3.3V] B2[+3.3V] NC_4 A1 B1 A1 B1
11 11 11 +3.3V_TUNER A1 B1 A1 B1
ERROR S_ERROR ERROR 47 47
12 12 12 FE_DEMOD1_TS_ERROR_TU
GND_1 GND_1 GND
TU_GND_A
13 13 13 SHIELD SHIELD
TU_GND_B
TU_GND_A
TU_GND_B
MCLK S_MCLK MCLK
14 14 14 FE_DEMOD1_1_TS_CLK
SYNC S_SYNC SYNC
15 15 15 FE_DEMOD1_TS_SYNC
VAILD S_VAILD VAILD
16 16 16 FE_DEMOD1_TS_VAL
D0 S_DATA D0
17 17 17 FE_DEMOD1_1_TS_DATA[0]
D1 NC_3 D1
18 18 18 FE_DEMOD1_TS_DATA[1]
D2 NC_4 D2
19 19 19 FE_DEMOD1_TS_DATA[2]
D3 NC_5 D3
20 20 20 FE_DEMOD1_TS_DATA[3]
D4 NC_6 D4
21 21 21 FE_DEMOD1_TS_DATA[4]
D5 NC_7 D5
22 22 22 FE_DEMOD1_TS_DATA[5]
D6 NC_8 D6
23 23 23 FE_DEMOD1_TS_DATA[6]
D7 NC_9 D7
24 24 24 FE_DEMOD1_TS_DATA[7]
RESET_DEMOD S_RESET_DEMOD RESET_DEMOD
25 25 25 /TU_RESET1_TU
B3[+3.3V] B3[+3.3V] B2[+3.3V]
26 26 26 +3.3V_DEMOD_TU
SCL_DEMOD SCL_DEMOD SCL_DEMOD
27 27 27 I2C_SCL2_TU
B4[+1.1V] B4[+1.1V] B3[+1.2V]
28 28 28 D_Demod_Core
F22_OUTPUT NC_10 NC_5
29 29 29 LNB_TX
SDA_DEMOD SDA_DEMOD SDA_DEMOD
30 30 30 I2C_SDA2_TU
LNB
31 LNB_OUT
GND_2 A1 B1 A1 B1
32 A1 B1 A1 B1
47 47
TU_GND_B
TU_GND_A
A1 B1
TU_GND_A
A1 B1 SHIELD SHIELD
TU_GND_B
47
TU_GND_A
SHIELD
TU_GND_B
TU_GND_A
TU_GND_B
TU_GND_B
TU1603-*2 TU1602-*1 TU1603-*1
TDJM-C351D TDJM-G255D TDJM-H101F
DEV_TDJM_C351D DEV_TDJM_G255D
B1[+3.3V] B1[+3.3V] DEV_TDJM_H101F B1[+3.3V]
1 1 1
RF_SW_CTL NC_1 NC_1
0 R1601
2 2 2
NC_1 NC_2 M_DIF_AGC
0
0
3 3 3
C1606-*1 C1602 C1606 C1601 C1600 4
SCL_RF
4
SCL_RF SCL_RF
4
1000pF 1000pF 1000pF 1000pF SDA_RF SDA_RF
R1600
SDA_RF
R1602
5 5
3300pF 630V 630V 630V C1601-*1 5
630V NC_2 NC_3
TU_M/W_EU_3300pF
M_DIF[P]
TU_M/W_EU_3300pF
TU_M/W_EU_3300pF
6 6 6
TU_M/W_CN/HK/TW/BR/EU_1000pF
630V
TU_M/W_CN/HK/TW/BR/EU_1000pF
3300pF NC_3 NC_4
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ_1000pF
M_DIF[N]
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ
7 7 7
TU_M/W_CN/HK/TW/BR/EU_3300pF
SIF SIF S_SIF
630V 8 8 8
CVBS CVBS S_CVBS
TU_H/M_KR/US/JP/EU
TU_H/M/W_KR/US/CN/JP/TW/BR/EU/AJ_3300pF
9 9 9
TU_H/M_KR/US/JP/EU
NC_4 NC_5 NC_2
10 10 10
NC_5 B2[+3.3V] B2[+3.3V]
11 11 11
ERROR ERROR S_ERROR
12 12 12
GND_1 GND_1 GND_1
13 13 13
MCLK MCLK S_MCLK
14 14 14
SYNC SYNC S_SYNC
15 15 15
TU_GND_B 16
VAILD
16
VAILD S_VALID
16
D0 D0 S_DATA
17 17 17
C1605 C1603 C1604 D1 D1 NC_3
18 18 18
3300pF 3300pF 3300pF GND_3 D2 D2 NC_4
19 19 19
630V 630V 630V D3 D3 NC_5
20 20 20
TU_GND_A for tuner EMS (S4) testing 21
D4
D5
21
D4
D5
21
NC_6
22 22 NC_7
22
D6 D6 NC_8
23 23 23
D7 D7 NC_9
24 24 24
RESET_DEMOD RESET_DEMOD S_RESET_DEMOD
25 25 25
B2[+3.3V] B3[+3.3V] B3[+3.3V]
26 26 26
SCL_DEMOD SCL_DEMOD SCL_DEMOD
27 27 27
B3[+1.1V] B4[+1.2V] B4[+1.1V]
28 28 28
NC_6 F22_OUTPUT NC_10
29 29 29
SDA_DEMOD SDA_DEMOD SDA_DEMOD
30 30 30
A1 B1 A1 B1 A1 B1
A1 B1 A1 B1 A1 B1
47 47 47
SHIELD SHIELD SHIELD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_SYMBOL 16
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
RS-232C Control INTERFACE
JK1700
PEJ038-3B61
RS232C_PHONE GND 5
R1700
100 L 4
+3.5V_ST DETECT 3
RS232C_PHONE
R1701
100 R 1
C1700 OPT
0.33uF ZD1700 OPT
ADUC 20S 02 010L ZD1701
20V ADUC 20S 02 010L
RS232C_PHONE RS232C_PHONE 20V
RS232C_PHONE C1705
IC1700 0.1uF
MAX3232CDR
C1+ VCC
RS232C_PHONE 1 16
C1701
0.1uF V+ GND
RS232C_PHONE 2 15
C1702
0.1uF C1- DOUT1
3 14
C2+ RIN1
RS232C_PHONE 4 13
C1703
0.1uF C2- ROUT1
5 12
SOC_RX
V- DIN1
RS232C_PHONE 6 11
SOC_TX
C1704
0.1uF DOUT2 DIN2
7 10
RIN2 ROUT2
8 9
EAN41348201 HP OUT R1703-*1
1uF
10V
HP_BYPASS
HP_OUT
HP_OUT
L1701 R1703
BLM18PG121SN1D 150
HP_LOUT_AMP HP_OUT 1/10W
C1707 5% +3.3V_NORMAL
0.22uF
10V
R1706
10K
HP_OUT
R1705 HP_OUT
100
HP_DET
1/16W
HP_OUT HP_OUT 5%
L1700 R1704
BLM18PG121SN1D 150
HP_ROUT_AMP HP_OUT 1/10W
C1706 5% R1704-*1
0.22uF 1uF ZD1702
10V 10V 5.6V
HP_BYPASS HP_OUT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C 17
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
DVB-S2 LNB Part Allegro
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A
3A
+12V
2A D1802-*1
SS23L
D1804-*1
30V Max 1.3A
DIODE_SS23L 40V
LNB_SX34
D1802 3.5A
DIODE_ONSEMI D1804
30V 40V
LNB
15uH
SP-7850_15
L1800
LNB_SMAB34
C1809
10uF
C1803 C1805 C1806 C1807 25V
0.01uF 10uF 10uF 10uF LNB
50V 25V 25V 25V
LNB LNB LNB LNB
C1808 0.1uF
close to Boost pin(#1) A_GND
A_GND
LNB
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND
30V
BOOST
GNDLX
NC_3
NC_2
C1810 R1804
SS23L A_GND
LX
0
D1801-*1 0.1uF
50V
20
19
18
17
16
DIODE_SS23L LNB
D1801 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT 21
30V EAN62653701 LNB
D1803 NC_1 3 13 VREG
DIODE_ONSEMI C1804
0.1uF LNB_SMAB34 IC1800 R1803
C1800 C1801 R1800 TDI ISET 39K
LNB 50V 40V 4A8303SESTR-T12
18pF 33pF 2.2K
D1800 1W LNB 1/16W
LNB LNB C1802 TDO 5 11 TCAP C1812
LNB LNB 0.22uF 1%
LNB 25V D1803-*1
10
LNB
LNB_SX34
6
7
8
9 0.1uF
40V
IRQ
SCL
SDA
ADD
TONECTRL
0.22uF
Close to Tuner A_GND
A_GND
Surge protectioin
LNB
C1811
R1801 33
R1802 33
LNB
LNB
I2C_SCL2
LNB_TX
I2C_SDA2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
LNB 18
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
eMMC I/F
DVDD18_EMMC
R1900
R1901
1/16W
10K
10K
1/16W
10K 10K
AR1903 AR1904
IC1900
THGBMAG5A1JBAIR
EMMC_DATA[0-7] AR1900 IC1900-*1 IC1900-*2
THGBMAG6A2JBAIR THGBMAG7A2JBAIR
22
1/16W EAN62886901 A3
DAT0
EAN62740501
NC_23
C8 A3
DAT0 NC_23
C8
A4 C9 A4 C9
DAT1 NC_24 DAT1 NC_24
EMMC_DATA[0] A3 C8 A5 C10 A5 C10
TOSHIBA_EMMC_16GB_V4.5
DAT2 NC_25 DAT2 NC_25
B2 C11 B2 C11
DAT0 NC_23 B3
DAT3 NC_26
C12 B3
DAT3 NC_26
C12
EMMC_DATA[1] A4 C9 B4
DAT4
DAT5
NC_27
NC_28
C13 B4
DAT4
DAT5
NC_27
NC_28
C13
TOSHIBA_EMMC_8GB_V4.5
B5 C14 B5 C14
DAT1 NC_24 B6
DAT6 NC_29
D1 B6
DAT6 NC_29
D1
EMMC_DATA[2] A5 C10 DAT7 NC_30
NC_31
D2
DAT7 NC_30
NC_31
D2
DAT2 NC_25 M6
NC_32
D3
D4 M6
NC_32
D3
D4
EMMC_DATA[3] B2 C11 M5
CLK
CMD
NC_33
NC_34
D12 M5
CLK
CMD
NC_33
NC_34
D12
EMMC_DATA[4] DAT3 NC_26 NC_35
D13
D14
NC_35
D13
D14
B3 C12 A6
RFU_1
NC_36
NC_37
E1 A6
RFU_1
NC_36
NC_37
E1
EMMC_DATA[5] DAT4 NC_27 A7
RFU_2 NC_38
E2 A7
RFU_2 NC_38
E2
B4 C13 C5
E5
NC_21 NC_39
E3
E12
C5
E5
NC_21 NC_39
E3
E12
EMMC_DATA[6] DAT5 NC_28 E8
RFU_3
RFU_4
NC_40
NC_41
E13 E8
RFU_3
RFU_4
NC_40
NC_41
E13
B5 C14 E9
E10
RFU_5 NC_42
E14
F1
E9
E10
RFU_5 NC_42
E14
F1
EMMC_DATA[7] AR1901 DAT6 NC_29 F10
RFU_6
RFU_7
NC_43
NC_44
F2 F10
RFU_6
RFU_7
NC_43
NC_44
F2
22 B6 D1 G3
G10
RFU_8 NC_45
F3
F12
G3
G10
RFU_8 NC_45
F3
F12
1/16W DAT7 NC_30 DAT5 H5
RFU_9 NC_46
F13 H5
RFU_9 NC_46
F13
D2 J5
K6
RFU_10
RFU_11
NC_47
NC_48
F14
G1
J5
K6
RFU_10
RFU_11
NC_47
NC_48
F14
G1
NC_31 K7
RFU_12 NC_49
G2 K7
RFU_12 NC_49
G2
D3 K10
P7
RFU_13
RFU_14
NC_50
NC_51
G12 K10
RFU_13
RFU_14
NC_50
NC_51
G12
NC_32 P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
M6 D4 RFU_16 NC_53
NC_54
H1
RFU_16 NC_53
NC_54
H1
CLK NC_33 K5
NC_55
H2
H3 K5
NC_55
H2
H3
M5 D12 RST_N NC_56
NC_57
H12
RST_N NC_56
NC_57
H12
CMD NC_34 NC_58
H13
NC_58
H13
D13 C6
M4
VCCQ_1 NC_59
H14
J1
C6
M4
VCCQ_1 NC_59
H14
J1
NC_35 N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J2 N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J2
D14 P3
P5
VCCQ_4 NC_62
J3
J12
P3
P5
VCCQ_4 NC_62
J3
J12
NC_36 VCCQ_5 NC_63
NC_64
J13
VCCQ_5 NC_63
NC_64
J13
A6 E1 E6
NC_65
J14
K1 E6
NC_65
J14
K1
RFU_1 NC_37 F5
VCC_1 NC_66
K2 F5
VCC_1 NC_66
K2
A7 E2 J10
K9
VCC_2
VCC_3
NC_67
NC_68
K3
K12
J10
K9
VCC_2
VCC_3
NC_67
NC_68
K3
K12
RFU_2 NC_38 VCC_4 NC_69
K13
VCC_4 NC_69
K13
C5 E3 NC_70
NC_71
K14
NC_70
NC_71
K14
NC_21 NC_39 C2
VDDI NC_72
L1
L2
C2
VDDI NC_72
L1
L2
E5 E12 NC_73
NC_74
L3
NC_73
NC_74
L3
AR1902 RFU_3 NC_40 E7
G5
VSS_1 NC_75
L12
L13
E7
G5
VSS_1 NC_75
L12
L13
22 E8 E13 H10
VSS_2
VSS_3
NC_76
NC_77
L14 H10
VSS_2
VSS_3
NC_76
NC_77
L14
RFU_4 NC_41 K8
VSS_4 NC_78
M1 K8
VSS_4 NC_78
M1
E9 E14 C4
N2
VSSQ_1 NC_79
M2
M3
C4
N2
VSSQ_1 NC_79
M2
M3
EMMC_CLK RFU_5 NC_42 N5
VSSQ_2
VSSQ_3
NC_80
NC_81
M7 N5
VSSQ_2
VSSQ_3
NC_80
NC_81
M7
E10 F1 P4
VSSQ_4 NC_82
M8 P4
VSSQ_4 NC_82
M8
DAT7
P6 M9 P6 M9
EMMC_CMD RFU_6 NC_43 DAT6 VSSQ_5 NC_83
NC_84
M10
VSSQ_5 NC_83
NC_84
M10
F10 F2 NC_85
M11
M12
NC_85
M11
M12
EMMC_RST RFU_7 NC_44 A1
NC_86
M13 A1
NC_86
M13
G3 F3 A2
A8
NC_1
NC_2
NC_87
NC_88
M14
N1
A2
A8
NC_1
NC_2
NC_87
NC_88
M14
N1
RFU_8 NC_45 A9
NC_3 NC_89
N3 A9
NC_3 NC_89
N3
G10 F12 A10
NC_4
NC_5
NC_90
NC_91
N6 A10
NC_4
NC_5
NC_90
NC_91
N6
RFU_9 NC_46 A11
A12
NC_6 NC_92
N7
N8
A11
A12
NC_6 NC_92
N7
N8
H5 F13 A13
NC_7
NC_8
NC_93
NC_94
N9 A13
NC_7
NC_8
NC_93
NC_94
N9
OPT RFU_10 NC_47 A14
B1
NC_9 NC_95
N10
N11
A14
B1
NC_9 NC_95
N10
N11
J5 F14 B7
NC_10 NC_96
N12 B7
NC_10 NC_96
N12
C1901 RFU_11 NC_48 B8
NC_11
NC_12
NC_97
NC_98
N13 B8
NC_11
NC_12
NC_97
NC_98
N13
10pF K6 G1 B9
B10
NC_13 NC_99
N14
P1
B9
B10
NC_13 NC_99
N14
P1
RFU_12 NC_49 B11
NC_14
NC_15
NC_100
NC_101
P2 B11
NC_14
NC_15
NC_100
NC_101
P2
50V K7 G2 B12
B13
NC_16 NC_102
P8
P9
B12
B13
NC_16 NC_102
P8
P9
RFU_13 NC_50 B14
NC_17
NC_18
NC_103
NC_104
P11 B14
NC_17
NC_18
NC_103
NC_104
P11
K10 G12 C1
C3
NC_19 NC_105
P12
P13
C1
C3
NC_19 NC_105
P12
P13
RFU_14 NC_51 C7
NC_20 NC_106
P14 C7
NC_20 NC_106
P14
P7 G13 NC_22 NC_107 NC_22 NC_107
RFU_15 NC_52
P10 G14
RFU_16 NC_53
H1
NC_54
H2
TOSHIBA_EMMC_4GB_V4.5
NC_55
K5 H3
RST_N NC_56
OPT H12
NC_57
C1900 H13
0.1uF NC_58
C6 H14
16V VCCQ_1 NC_59
DVDD18_EMMC 3.3V_EMMC M4 J1
VCCQ_2 NC_60
N4 J2
VCCQ_3 NC_61
P3 J3
VCCQ_4 NC_62
P5 J12
VCCQ_5 NC_63
DAT3
DAT4
DAT5
DAT6
EMMC_CLK_BALL
EMMC_CMD_BALL
EMMC_RESET_BALL
J13
C1902 C1903 NC_64
0.1uF 2.2uF J14 EMMC_RESET_BALL
NC_65
16V 10V E6 K1
VCC_1 NC_66
F5 K2
VCC_2 NC_67
J10 K3
VCC_3 NC_68
K9 K12
VCC_4 NC_69
K13
NC_70
EMMC_VDDI K14
pattern 0.2mm NC_71
C2 L1
VDDI NC_72
L2
C1906 NC_73
1uF L3
NC_74
10V E7 L12
VSS_1 NC_75
G5 L13
VSS_2 NC_76
H10 L14
VSS_3 NC_77
K8 M1
VSS_4 NC_78
C1904 C1905 C4 M2
0.1uF 2.2uF VSSQ_1 NC_79
N2 M3 EMMC_CLK_BALL
16V 10V VSSQ_2 NC_80
N5 M7
VSSQ_3 NC_81
P4 M8
VSSQ_4 NC_82
P6 M9
VSSQ_5 NC_83
M10
NC_84
M11
NC_85
M12
NC_86
A1 M13
DAT3 NC_1 NC_87
A2 M14
DAT4 NC_2 NC_88
A8 N1
DAT7 NC_3 NC_89
A9 N3 EMMC_CMD_BALL
NC_4 NC_90
A10 N6
NC_5 NC_91
A11 N7
NC_6 NC_92
A12 N8
NC_7 NC_93
A13 N9
NC_8 NC_94
A14 N10
NC_9 NC_95
B1 N11
NC_10 NC_96
B7 N12
NC_11 NC_97
B8 N13
NC_12 NC_98
B9 N14
NC_13 NC_99
B10 P1
NC_14 NC_100
B11 P2
NC_15 NC_101
B12 P8
NC_16 NC_102
Don’t Connect Power At VDDI EMMC_VDDI B13
B14
NC_17
NC_18
NC_103
NC_104
P9
P11
C1 P12
NC_19 NC_105
(Just Interal LDO Capacitor) DAT5
C3
C7
NC_20 NC_106
P13
P14
NC_22 NC_107
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EMMC 19
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
EU_CVBSOUT
EU_CVBSOUT
RTR030P02
RTR030P02
Q2103
+3.3V_CVBS_out
Q2101
+3.3V_NORMAL +3.3V_CVBS_out
Full Scart(18 Pin Gender) L2100
BLM18PG121SN1D
D
S
D
S
EU_CVBSOUT
EU_CVBSOUT
OPT
R2120
OPT
EU_CVBSOUT
R2121
OPT
G
R2125
+3.3V_NORMAL C2108 EU_CVBSOUT C2112
OPT
G
R2126
EU_CVBSOUT
200
1K
1uF R2127 1uF
1K
R2119
200
0 10V
1.8K
CVBS_OUT_SEL
EU 1/16W
R2114 CLOSE TO JUNCTION 5%
10K EU EU_CVBSOUT
C
R2116 R2118
1K 10K B Q2100
SC_DET CVBS_OUT_SEL 2SC3052
1/16W
EU
C2106 5% E EU_CVBSOUT E
VA2101 EU_CVBSOUT
5.6V 0.1uF
DTV/MNT_V_OUT MMBT3906(NXP)
OPT B Q2102
EU_CVBSOUT
EU_CVBSOUT
R2123
R2122
C
E
EU_CVBSOUT
75
75
ATV_OUT MMBT3906(NXP)
SC_CVBS_IN B Q2104
C
75 OPT
VA2107 +3.3V_CVBS_out
R2105 C2102
SHIELD 5.5V 47pF
EU 3216 50V EU_CVBSOUT
EU EU
19 C2110
R2113 C2114
AV_DET 0 1uF EU_CVBSOUT
0.1uF
18 IC2100 C2109
COM_GND MM1756DURE(4M) EU_CVBSOUT 0.1uF
VA2108 DTV/MNT_V_OUT1
C2113
0.1uF
EU_CVBSOUT
17 5.5V
SYNC_IN OPT SCART_OUT_BYPASS OPT OPT
75 C2103 C2107 VCC IN
16
SYNC_OUT R2102 68pF 68pF 6 1
15 50V 50V
SYNC_GND EU PS EU_CVBSOUT GND
R2112 5 2
14 22
RGB_IO EU_CVBSOUT
13 SC_FB R2124
R_OUT VA2102 75 OUT BIAS
4 3 EU_CVBSOUT
12 5.6V
R_GND EU C2111
EU DTV/MNT_V_OUT1 4.7uF
11 R2108
G_OUT 75
10 SCART_OUT_BYPASS
G_GND
9 SC_R R2128
ID 0
EU DTV/MNT_V_OUT1 DTV/MNT_V_OUT
8 VA2103 1/16W
B_OUT R2106
5.5V 75 5%
7
AUDIO_L_IN EU
6
B_GND
5
AUDIO_GND
SC_G CVBS_OUT_SEL 0 1
4 EU
VA2104 R2109
AUDIO_L_OUT
5.5V 75
3
AUDIO_R_IN EU DTV_MNT_V_OUT1 DTV OUT ATV OUT
2
AUDIO_R_OUT
1
SC_B
EU
VA2105 R2107
5.5V 75
DA1R018H91E EU
JK2100
EU EU
R2115
15K
EU
SC_ID
R2103 EU
10K
SC_L_IN R2117
3.9K
VA2100 VA2109 R2110
EU 12K
5.6V
20V EU R2100
EU
470K
EU
EU
R2104
10K
SC_R_IN
EU R2111
12K
VA2106 R2101
470K EU
5.6V
EU
DTV/MNT_L_OUT
EU
C2100
1000pF
50V
DTV/MNT_R_OUT
EU
C2101
1000pF
50V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART JACK 21
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+12V
EU
L2200
AUD_OUT >> EU/CHINA_HOTEL_OPT
IC2200
AZ4580MTR-E1
EU EU
EU
2.2K R2202 OUT1 8 VCC
1 C2207
DTV/MNT_L_OUT EU
C2202 OPT
0.1uF
50V R2211
EU
C2210
[SCART AUDIO MUTE]
10uF OPT R2203 EU IN1- OUT2 SIGN74002423 2.2K
33K R2204 2 7
C2203 470K DTV/MNT_R_OUT
6800pF
33pF C2204
IN1+
3
EU 6 IN2- R2209
EU
33K
OPT
R2210
OPT
C2209
10uF DTV/MNT_L_OUT
EU 470K
6800pF
EU
VEE 5 IN2+ C
4 C2208 EU R2212
33pF Q2200 B 1K
SCART_AMP_L_FB MMBT3904(NXP)
EU_SCART_MUTE_ISAHAYA
SCART_AMP_R_FB E EU Q2202
R2218
1/16W
100K
RT1P141C-T112
EU
C2215
2.2uF
R2220
1/16W
SCART_MUTE
EU
C
E
5%
100K
EU
10V
EU
R2214
5%
C2216
2.2uF
5.6K EU
10V
SCART_Lout
R2216
B
R2219
1/16W
EU
5.6K
100K
330pF 220K
EU
R2215 SCART_Rout DTV/MNT_R_OUT
5%
R2221
1/16W
C2211
100K
EU EU EU PDTA114ET
EU Q2202-*1
EU
5%
R2217 C2212 EU
C
E
220K 330pF C
R2213
Q2201 B 1K
MMBT3904(NXP)
B
CLOSE TO MSTAR E EU EU_SCART_MUTE_NXP
CLOSE TO MSTAR
Near Place Scart AMP
EU EU
SCART_AMP_R_FB
10K
4.7uF
C2213 R2201
EU EU
SCART_AMP_L_FB
10K
4.7uF
C2214 R2200
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UB83 2013-10-28
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART JACK 21
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
CI Region * Option name of this page : CI_SLOT
(because of Hong Kong)
CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_DATA[0-7]
+5V_NORMAL AR2303 33
FE_DEMOD1_TS_DATA[0-7]
C2303 FE_DEMOD1_TS_DATA[7]
CI_MDI[7]
10uF FE_DEMOD1_TS_DATA[6]
10V CI_MDI[6]
R2308 FE_DEMOD1_TS_DATA[5]
CI_MDI[5]
10K CI_SLOT_JACK FE_DEMOD1_TS_DATA[4]
CI_MDI[4]
/CI_CD1 P2300
10125901-015LF
AR2304 33 FE_DEMOD1_TS_DATA[3]
R2314 35 1 CI_MDI[3]
100 CI_DATA[3] FE_DEMOD1_TS_DATA[2]
36 2 CI_MDI[2] FE_DEMOD1_TS_DATA[1]
AR2300 CI_DATA[4]
CI_DATA[0-7]
33 37 3 CI_MDI[1] FE_DEMOD1_TS_DATA[0]
CI_DATA[5] R2320
TPI_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
TPI_DATA[5] 39 5
CI_DATA[7] FE_DEMOD1_TS_DATA[0-7]
TPI_DATA[6] 40 6
R2318 R2322 33
TPI_DATA[7] 41 7 47 CI_MISTRT FE_DEMOD1_TS_SYNC
CI_ADDR[10] /PCM_CE1 R2323 33
42 8 CI_MIVAL_ERR FE_DEMOD1_TS_VAL
R2310 10K R2324 100
43 9 CI_OE CI_MCLKI FE_DEMOD1_TS_CLK
CI_ADDR[11]
CI_IORD 44 10 +5V_NORMAL
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R2321
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14
CI_MDI[2] 49 15 CI_WE
50 16 R2319 100
CI_MDI[3] CAM_IREQ_N
51 17
GND
C2301
0.1uF
52
53
18
19
C2304
0.1uF
C2305
0.1uF
CI HOST I/F
CI_MDI[4]
GND
CI_MDI[5] 54 20
+5V_NORMAL CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R2300 56 22 GND
CI_MDI[7] CI_ADDR[6]
10K R2311 10K 57 23
R2303 CI_ADDR[5] AR2310
47 58 24
PCM_RESET CI_ADDR[4] 33
R2304 47 59 25
CAM_WAIT_N CI_ADDR[3] CI_ADDR[0] EB_ADDR[0]
CLOSE TO MSTAR 60 26
REG CI_ADDR[2] CI_ADDR[1] EB_ADDR[1]
R2305 33 61 27
TPI_CLK CI_ADDR[1] CI_ADDR[2] EB_ADDR[2]
R2306 33
TPI_VAL 62 28 EB_ADDR[3]
CI_ADDR[0] CI_ADDR[3]
R2307 33 63 29
TPI_SOP
CI_DATA[0]
64 30
AR2301 33 CI_DATA[1]
65 31 CI_ADDR[0-14]
TPI_DATA[0] CI_DATA[2]
66 32
TPI_DATA[1] 67 33 AR2302
TPI_DATA[2] 68 34 33
TPI_DATA[3]
CI_ADDR[4] EB_ADDR[4]
G2 69 G1
R2312 CI_ADDR[5] EB_ADDR[5]
100 CI_ADDR[6] EB_ADDR[6]
/CI_CD2
CI_ADDR[7] EB_ADDR[7]
+5V_NORMAL GND
GND AR2308 33
C2300
2pF CI_ADDR[8] EB_ADDR[8]
R2309
50V CI_ADDR[9] EB_ADDR[9]
10K GND
CI_ADDR[10] EB_ADDR[10]
CLOSE TO MSTAR
CI_ADDR[11] EB_ADDR[11]
CI_MISTRT AR2309 33
CI_MIVAL_ERR CI_ADDR[12] EB_ADDR[12]
CI_ADDR[13] EB_ADDR[13]
CI_MCLKI CI_ADDR[14] EB_ADDR[14]
REG CAM_REG_N
AR2307 33
CI_OE EB_OE_N
CI_WE EB_WE_N
CI_IORD EB_BE_N1
CI DETECT +3.3V_NORMAL
CI_IOWR EB_BE_N0
OR_GATE_CI_PHILIPS
IC2300
74LVC1G32GW +3.3V_NORMAL
B 1 5 VCC
/CI_CD2
A 2
/CI_CD1 AR2305 33
GND 3 4 Y R2313 CI_DATA[0] EB_DATA[0]
10K CI_DATA[1] EB_DATA[1]
CI_DATA[0-7]
CI_DATA[2] EB_DATA[2]
OR_GATE_CI_TI OR_GATE_CI_TOSHIBA CI_DATA[3] EB_DATA[3]
IC2300-*1 IC2300-*2
SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION
EB_DATA[0-7]
A VCC IN_B VCC
1 5 1 5
CAM_CD1_N AR2306 33
B IN_A R2316 CI_DATA[4] EB_DATA[4]
2 2
47 CI_DATA[5] EB_DATA[5]
GND Y GND OUT_Y
3 4 3 4
CI_DATA[6] EB_DATA[6]
CI_DATA[7] EB_DATA[7]
EB_DATA[0-7]
CI_DATA[0-7]
CI POWER ENABLE CONTROL
+5V_NORMAL IC2301
AP2151WG-7 +5V_CI_ON
L2300
BLM18PG121SN1D
IN OUT
5 1
GND
2
R2317
C2302
100K
R2302 1uF
100 EN FLG 10V
PCM_5V_CTL 4 3
R2301
10K
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013.04.29
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 19
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
VDDP
4st Layer
L2190
BLM18PG121SN1D
C2190 C2195 C2120 C2128 C2134 C2139 C2143 C2145 C13314 C13315
10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF
IC2500
LGE7411(URSA9) 10V 10V 10V 10V 16V 16V 16V 16V 16V 10V
AG2
RB0N
AG1
RB0P
AH3
AH1
RB1N
RB1P AVDD_PLL 4st Layer
Close to Chip side
AH2
RB2N L2101
AJ3
RB2P BLM18PG121SN1D
AJ2
RBCKN
AK2
RBCKP
AK1 AM17
RB3N VX1_0-
AL1 AK17 C2105 C2192 C2151
RB3P VX1_0+ C13302
AM2 AL18
RB4N VX1_1- 10uF 0.1uF 0.1uF 10uF
AL2 AK18
RB4P VX1_1+ 10V 16V 16V 10V
AM19
VX1_2-
AL19
VX1_2+
AK3 AL20
RC0N VX1_3-
AL3 AM20
RC0P VX1_3+
AK4 AK22 0.1uF C13008 TXDBN7_L
AL4
AM4
RC1N
RC1P
VX1_4-
VX1_4+
AL21
AK23
0.1uF
0.1uF
C13009
C13010
TXDBP7_L
TXDBN6_L
IC2500 Close to Chip side
AK5
RC2N VX1_5-
AM22 0.1uF C13011 TXDBP6_L
LGE7411(URSA9) AVDD_MOD
AM5
RC2P VX1_5+
AK24 0.1uF C13012 TXDBN5_L
4th Layer
RCCKN VX1_6- L2102
AL5 AL23 0.1uF C13013 TXDBP5_L BLM18PG121SN1D
RCCKP VX1_6+
AK6 AL25 0.1uF C13014 TXDBN4_L
RC3N VX1_7-
AL6 AK25 0.1uF C13015 TXDBP4_L
RC3P VX1_7+
AK7 AM26 0.1uF C13016 TXDBN3_L
RC4N VX1_8- C2104 C2193 C2119 C2127 C2133 C2138 C2142 C13306
AL7 AK26 0.1uF C13017 TXDBP3_L
RC4P VX1_8+
AL27
10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF C13018 TXDBN2_L
VX1_9-
AK27 10V 10V 10V 16V 16V 16V 16V 16V
0.1uF C13019 TXDBP2_L
VX1_9+
AM7 AM28 0.1uF C13020 TXDBN1_L
RD0N VX1_10-
AK8 AL28 0.1uF C13021 TXDBP1_L
AM8
RD0P VX1_10+
AL29 D1
0.1uF C13022 TXDBN0_L
AL8
RD1N VX1_11-
AM29
HDMI_CLK+_URSA9_0_RP HDMI_RXCP_0
RD1P VX1_11+
0.1uF C13023 TXDBP0_L D3
AK9 AM31 HDMI_CLK-_URSA9_0_RP HDMI_RXCN_0
AL9
RD2N
RD2P
VX1_12-
VX1_12+
AL30
0.1uF
0.1uF
C13024
C13025
TXDAN7_L
TXDAP7_L HDMI_RX0+_URSA9_0_RP
E3
HDMI_RX0P_0
Close to Chip side
AK10 AL32 0.1uF C13026 TXDAN6_L D2
RDCKN VX1_13-
AL10 AL31 0.1uF C13027 TXDAP6_L HDMI_RX0-_URSA9_0_RP HDMI_RX0N_0
AM10
RDCKP VX1_13+
AK31 F3
0.1uF C13028 TXDAN5_L
AK11
RD3N VX1_14-
AK32
HDMI_RX1+_URSA9_0_RP HDMI_RX1P_0 VDDC VDDC 4th Layer
RD3P VX1_14+
0.1uF C13029 TXDAP5_L E2
AM11 AJ30 0.1uF C13030 TXDAN4_L HDMI_RX1-_URSA9_0_RP HDMI_RX1N_0
AL11
RD4N VX1_15-
AJ31 F1
0.1uF C13031 TXDAP4_L
RD4P VX1_15+
AH30
HDMI_RX2+_URSA9_0_RP HDMI_RX2P_0
VX1_16-
0.1uF C13064 TXDAN3_L F2
VX1_16+
AH32 0.1uF C13065 TXDAP3_L HDMI_RX2-_URSA9_0_RP HDMI_RX2N_0
AK12 AG30 0.1uF C13066 TXDAN2_L
AL12
RE0N VX1_17-
AG31 C2191 C2198 C2194 C2122 C2132 C2137 C2144 C2146 C2147 C2148 C2149 C13307 C2150 C2196
0.1uF C13067 TXDAP2_L
AK13
RE0P VX1_17+
AE31 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
0.1uF C13068 TXDAN1_L
RE1N VX1_18- 10V
AL13 AF30 0.1uF C13069 TXDAP1_L 10V 10V 10V 10V 10V 10V 16V 16V 16V 16V 16V 16V 10V
RE1P VX1_18+
AM13 AD32 0.1uF C13070 TXDAN0_L
RE2N VX1_19-
AK14 AE30 0.1uF C13071 TXDAP0_L
RE2P VX1_19+
AM14
RECKN
AL14 AVDDL_MOD
RECKP
AK15 AH29
AL15
AK16
RE3N
RE3P
VX1_HTDPN
VX1_LOCKN
AG29
HTPDAn
L2104
4th Layer
Close to Chip side
RE4N R1938 BLM18PG121SN1D
AL16 10K
RE4P
URSA_TX_HTPD_pulldown G1
HDMI_RXCP_1
G3 C2115 C2123 C13311 C13305 C2154
HDMI_RXCN_1 0.1uF 0.1uF 10uF 10uF
H3 0.1uF
HDMI_RX0P_1 16V 16V 10V 16V 10V
0.1uF C13036 AE2 G2
TXVBY1_2N VBY1_RXM[0]
TXVBY1_2P 0.1uF C13037 AE1 HDMI_RX0N_1
VBY1_RXP[0] J3
OSD
AD2
AE3
VBY1_RXM[1] LOCKAn HDMI_RX1P_1
VBY1_RXP[1]
H2
TXVBY1_3N 0.1uF
0.1uF
C13040
C13041
AC2
AD3
VBY1_RXM[2] J1
HDMI_RX1N_1
AVDDL_DRV
Close to Chip side
TXVBY1_3P
AC3
VBY1_RXP[2] HDMI_RX2P_1
VBY1_RXM[3] +3.3V_NORMAL
J2 4th Layer
AC1
VBY1_RXP[3]
HDMI_RX2N_1
L2105
BLM18PG121SN1D
0.1uF C13044 AB2
TXVBY1_4N VBY1_RXM[4]
0.1uF C13045 AB1
TXVBY1_4P VBY1_RXP[4]
AA2 C2116 C2124 C13310 C13304 C2153
VBY1_RXM[5]
AB3 0.1uF 0.1uF 10uF 0.1uF 10uF
R1952
VBY1_RXP[5]
Y2 16V
0.1uF C13048 16V 10V 16V 10V
22
TXVBY1_5N
VIDEO
VBY1_RXM[6]
0.1uF C13049 AA3
TXVBY1_5P VBY1_RXP[6]
Y3
VBY1_RXM[7]
Y1
SML-512UW
VBY1_RXP[7]
LD1900
TXVBY1_6N
TXVBY1_6P
0.1uF
0.1uF
C13052
C13053
W2
W1
VBY1_RXM[8]
VBY1_RXP[8]
R1939
HDMI_TX_DDC_CLK
DVDD_DDR Close to Chip side
V2 10K HDMI_TX_DDC_SDA 4th Layer
VBY1_RXM[9]
W3
R1943
VBY1_RXP[9] L2106
U2 BLM18PG121SN1D
220
TXVBY1_7N 0.1uF C13056 R1996
V3
VBY1_RXM[10] 22 N4
0.1uF C13057 HDMI_TX_DDC_CLK
TXVBY1_7P
U3
VBY1_RXP[10] HDMITX_SCL
R1997 22 M4 C2152
U1
VBY1_RXM[11] HDMI_TX_DDC_SDA HDMITX_SDA C2117 C2125 C13312 C13303 C13313
VBY1_RXP[11] N1 10uF
HDMI OUTPUT to LM14
E Q1901 0.1uF 0.1uF 4.7uF 0.1uF 4.7uF
MMBT3906(NXP)
HDMI_CLK+ HDMI_TXCP 16V 10V 10V 16V 10V
P1 16V
B HDMI_CLK- HDMI_TXCN
N3
C HDMI_RX0+ HDMI_TX0P
N2
HDMI_RX0- HDMI_TX0N
M3
HDMI_RX1+
M2
HDMI_TX1P
AVDDL_HDMI_TX_RX
Close to Chip side
HDMI_RX1- HDMI_TX1N
L1
HDMI_RX2+ HDMI_TX2P
L2 L2107
HDMI_RX2- HDMI_TX2N BLM18PG121SN1D
C2118 C2126 C2131 C13309
0.1uF 0.1uF 0.1uF 10uF
16V 16V 16V 10V
GND Connection at Vx1 41pin wafer
AVDDL_LVDSRX
R12900 0
GND_Vx1_2
Non_LGD_Module L13300
(pin 8) BLM18PG121SN1D
C13300 C13301 C13308
0.1uF 0.1uF 10uF
R12901 0 16V 16V 10V
GND_Vx1
(pin 5,11,14) Non_UB95
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-128-02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_LVDS INPUT
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+1.8V Vx1 LOCKAn/HTPDn
[51P Vx1
output wafer]
R13064
R13063
1.5K
47K
51pin_Wafer
P13000 Q1404 [41P Vx1
G
FI-RE51S-HF-J-R1500 AO3438
LOCKAn output wafer]
S
D
LOCKn_IN
1
41pin_Wafer
2 TXDAP7_L +1.8V P13001
3 FI-RE41S-HF-J-R1500
TXDAN7_L
4
URSA_TX_HTPD_Pullup
URSA_TX_HTPD_Pullup
+3.3V_NORMAL
5 TXDAP6_L 1
6 TXDAN6_L 2 D9_I2C_SCL
R209 R211 R222
7 4.7K 1.5K 10K
3 D9_I2C_SDA
URSA_TX_HTPD_Pullup
8 TXDAP5_L 4 Not Used Net (UB85/95/UC89)
9
G
TXDAN5_L 5 GND_Vx1 TXDBP11_L
10
HTPDAn 6 TXDBP11_L TXDBN11_L
S
D
11 HTPDn_IN R221
TXDAP4_L 0 Q203 7
URSA_TX_HTPD_Pullup AO3438 TXDBN11_L
12 URSA_TX_HTPD_Pullup TXDBP10_L
TXDAN4_L 8 GND_Vx1_2
13 TXDBN10_L
9 TXDBP10_L
14 TXDAP3_L R220 TXDBP9_L
0 10 TXDBN10_L
15 OPT
TXDAN3_L 11 TXDBN9_L
16
12 TXDBP9_L TXDBP8_L
17 TXDAP2_L 13 TXDBN9_L TXDBN8_L
18 TXDAN2_L +3.3V_NORMAL 14
L/D_EN(Pin30) GND_Vx1
19 - T-Con L/D Function
R13034 15 TXDBP8_L
10K HIGH : Enable GND_Vx1_2
20 TXDAP1_L LOW or NC : Disable
OPT 16 TXDBN8_L
+3.3V_NORMAL *LGD_120Hz: T240 module (UB98/95,D9)
21 R13037 0
TXDAN1_L L_DIM_EN 17
Non_AUO_Module
22 R13003 18 TXDBP7_L
10K R13007
23 D9_I2C_SCL
TXDAP0_L OPT 10K 19 TXDBN7_L
Non_AUO_Module
D9_I2C
+3.3V_NORMAL
24
R13014 0
TXDAN0_L 20
TCON_I2C_EN
25
R13004 R13018 21 TXDBP6_L
G
10K 4.7K
26 LOCKn_IN LGD_Module
OPT 22 TXDBN6_L
R13013 0 R13061 0
27 HTPDn_IN I2C_SCL7
S
23
D
R13011 10K NON_D9_I2C Non_AUO_Module
28 EL_VDD_DETECT_22V Q13004
2N7002A 24 TXDBP5_L
Non_INX_Module
29 R13055
25 TXDBN5_L
30 L13001 33 OPT
BLM18PG121SN1D 26
OPT *Pin31(BIT_SEL) +3.3V_NORMAL
31 HIGH or NC : 10Bit OLED D9_I2C_SDA
0
27 TXDBP4_L
D9_I2C
R13033 10K LOW : 8Bit
32 TCON_I2C_EN
R13017
R13019 28 TXDBN4_L
G
33 4.7K
OPT 29
R13012 0 R13062 0
34 I2C_SDA7
S
30
D
R13006 0 *Pin35(PCID) NON_D9_I2C Non_AUO_Module TXDBP3_L
35 3D_EN High:PCID enable Q13005
2N7002A 31 TXDBN3_L
3D_EN_LGD_120Hz Low or NC : PCID diable
36
R13059 32
37
33 OPT 33 TXDBP2_L
R13005 0 +3.3V_NORMAL
38
34 TXDBN2_L
Non_LGD_60Hz
39
35
R13000 0 *Pin38 R13044
40 PWM_TIN Non_LGD_60Hz: T120 module(UB85) 10K
G+ OPT 36 TXDBP1_L
R13001 0
41 INV_CTL R13016 0 37 TXDBN1_L
OLED R13002 0 Data_Format_1
42 Compensation_Done 38
Non_OLED & Non_AUO_Module
LGD_Module
Non_OLED & Non_AUO_Module
OLED
43
R13009 R13010 39
0 0 TXDBP0_L
44 R13045
Compensation_Done 40 TXDBN0_L
10K Data Input Format[1:0]
45 LGD_Module 41
*Mode 3 (4 Division)
46 - Data Format 0(Pin37) = Low
Data Format 1(Pin36) = High 42
47 +3.3V_NORMAL
*Mode 2 (2 Division)
48 - Data Format 0(Pin37) = High
R13008 0
PWM_TOUT Data Format 1(Pin36) = Low
49 R13040 G+
10K
50 OPT
PANEL_VCC
51 R13015 0
Data_Format_0
L13000 LGD_Module
52 MLB-201209-0120P-N2
51pin_12V
C13032 C13033 R13041
10K
10uF 10uF LGD_Module
25V 25V
51pin_12V 51pin_12V
EL_VDD_DETECT_22V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-130-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Output_wafer
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
LGE7411(URSA9)
F14 H27 B_DDR3_A[0]
B_DDR3_A[0-15] DDR PHY VREF
A_DDR3_A[0] A_DDR3_A0 B_DDR3_A0
B13 G31 B_DDR3_A[1] +1.5V_U_DDR +1.5V_U_DDR
A_DDR3_A[1] A_DDR3_A1 B_DDR3_A1 U_MVREFCA_A0 U_MVREFCA_A1
E13 G28 B_DDR3_A[2]
A_DDR3_A[2] A_DDR3_A2 B_DDR3_A2
D13 G29 B_DDR3_A[3]
A_DDR3_A[3] A_DDR3_A3 B_DDR3_A3 DDR_VTT_URSA_1
C14 H30 B_DDR3_A[4]
A_DDR3_A[4] A_DDR3_A4 B_DDR3_A4 R13110 R13120
F13 G27 B_DDR3_A[5] 1K
A_DDR3_A[5] A_DDR3_A5 B_DDR3_A5 1%
1K IC2600
A_DDR3_A[6]
C13 G30 B_DDR3_A[6] 1%
H5TQ1G63EFR-RDC AR13100 AR13102 AR13104 AR13106 AR13108 AR13110 AR13112
IC2700
A_DDR3_A6 B_DDR3_A6
B10 D31 B_DDR3_A[7] U_MVREFCA_A0 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
A_DDR3_A[7] A_DDR3_A7 B_DDR3_A7 U_MVREFCA_A1
A12 F32 B_DDR3_A[8]
A_DDR3_A[8] A_DDR3_A8 B_DDR3_A8 R13111 C13202 C13210 R13121 C13222 C13230
C10 D30 B_DDR3_A[9]
1K
A_DDR3_A[9] A_DDR3_A9 B_DDR3_A9 0.1uF 1000pF 1K 0.1uF 1000pF N3 M8
A14 H32 B_DDR3_A[10] 1% 1% A_DDR3_A[0] A0 VREFCA N3 M8
A_DDR3_A[10] A_DDR3_A10 B_DDR3_A10 P7 A_DDR3_A[0] A0 VREFCA
B12 F31 B_DDR3_A[11] A_DDR3_A[1] A1 P7
A_DDR3_A[11] A_DDR3_A11 B_DDR3_A11 P3 A_DDR3_A[1] A1
F15 J27 B_DDR3_A[12] A_DDR3_A[2] A2 P3
A_DDR3_A[12] A_DDR3_A12 B_DDR3_A12 N2 H1 A_DDR3_A[2] A2
C11 E30 B_DDR3_A[13] A_DDR3_A[3] A3 VREFDQ N2 H1
A_DDR3_A[13] A_DDR3_A13 B_DDR3_A13 P8 A_DDR3_A[3] A3 VREFDQ
C12 F30 B_DDR3_A[14] A_DDR3_A[4] A4 P8
A_DDR3_A[14] A_DDR3_A14 B_DDR3_A14 P2 A_DDR3_A[4] A4
D17 L29 B_DDR3_A[15] A_DDR3_A[5] A5 P2
A_DDR3_A[15] A_DDR3_A15 B_DDR3_A15 R8 L8 R13126 240
A_DDR3_A[5] A5
E14 H28 A_DDR3_A[6] A6 ZQ R8 L8 R13134 240
A_DDR3_BA[0] A_DDR3_BA0 B_DDR3_BA0 B_DDR3_BA[0] R2 1%
A_DDR3_A[6] A6 ZQ
B14 H31 A_DDR3_A[7] A7 R2 1% +1.5V_U_DDR
A_DDR3_BA1 T8 +1.5V_U_DDR A_DDR3_A[7]
A_DDR3_BA[1] B_DDR3_BA1 B_DDR3_BA[1] A_DDR3_A[8] A7
E15 J28 A8 T8
A_DDR3_BA[2] A_DDR3_BA2 B_DDR3_BA2 B_DDR3_BA[2] R3 B2 A_DDR3_A[8] A8
A_DDR3_A[9] A9 VDD_1 R3 B2
L7 D9 A_DDR3_A[9] A9 VDD_1
E17 L28 A_DDR3_A[10] A10/AP VDD_2 L7 D9
A_DDR3_RASZ A_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ R7 G7 A_DDR3_A[10] A10/AP VDD_2
C17 L30 A_DDR3_A[11] A11 VDD_3 R7 G7
A_DDR3_CASZ A_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ N7 K2 A_DDR3_A[11] A11 VDD_3
C16 K30 A_DDR3_A[12] A12/BC VDD_4 N7 K2
A_DDR3_WEZ A_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ T3 K8 A_DDR3_A[12] A12/BC VDD_4
F17 L27 A_DDR3_A[13] NC_7 VDD_5 T3 K8
A_DDR3_ODT A_DDR3_ODT B_DDR3_ODT B_DDR3_ODT N1 A_DDR3_A[13] NC_7 VDD_5
C15 J30 VDD_6 N1
A_DDR3_CKE A_DDR3_CKE B_DDR3_CKE B_DDR3_CKE M7 N9 A_DDR3_A[14] VDD_6
B11 E31 A_DDR3_A[15] NC_5 VDD_7 M7 N9
A_DDR3_RESET A_DDR3_RESETB B_DDR3_RESETB B_DDR3_RESET R1 A_DDR3_A[15] NC_5 VDD_7
B16 K31 VDD_8 R1
A_DDR3_MCLK A_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK +1.5V_U_DDR M2 R9 VDD_8
A16 K32 A_DDR3_BA[0] BA0 VDD_9 M2 R9
A_DDR3_MCLKZ B_DDR3_MCLKZ +1.5V_U_DDR N8
A_DDR3_MCLKZ B_DDR3_MCLKZ U_MVREFCA_B0 U_MVREFCA_B1 A_DDR3_BA[0] BA0 VDD_9
C9 C30 A_DDR3_BA[1] BA1 +1.5V_U_DDR N8
M3 +1.5V_U_DDR
R13123R13122
A_DDR3_CSB1 A_DDR3_CSB1 B_DDR3_CSB1 B_DDR3_CSB1 A_DDR3_MCLK A_DDR3_BA[1] BA1
A9 C32 A_DDR3_BA[2] BA2 M3
56
A_DDR3_CSB2 A_DDR3_CSB2 B_DDR3_CSB2 B_DDR3_CSB2 C13233 A1 A_DDR3_BA[2] BA2
VDDQ_1 A1
A_DDR3_DQ[0-15] B_DDR3_DQ[0-15] R13108 0.01uF J7 A8 VDDQ_1
R13118
56
A_DDR3_DQ[0] D23 U29 B_DDR3_DQ[0] CK VDDQ_2 J7 A8
1K 1K K7 C1
A_DDR3_DQ0 B_DDR3_DQ0 A_DDR3_MCLK CK VDDQ_2
A_DDR3_DQ[1] A19 N32 B_DDR3_DQ[1] 1% 1% A_DDR3_MCLKZ CK VDDQ_3 K7 C1
A_DDR3_DQ1 B_DDR3_DQ1 K9 C9 A_DDR3_MCLKZ CK VDDQ_3
A_DDR3_DQ[2] E22 T28 B_DDR3_DQ[2] A_DDR3_CKE CKE VDDQ_4 K9 C9
A_DDR3_DQ2 B_DDR3_DQ2 D2 A_DDR3_CKE CKE VDDQ_4
A_DDR3_DQ[3] B18 M31 B_DDR3_DQ[3] VDDQ_5 D2
A_DDR3_DQ3 B_DDR3_DQ3 L2 E9 VDDQ_5
A_DDR3_DQ[4] C23 U30 B_DDR3_DQ[4] R13109 C13201 C13209 R13119 C13221 C13229 A_DDR3_CSB1 CS VDDQ_6 L2 E9
A_DDR3_DQ4 B_DDR3_DQ4 1K 0.1uF 1000pF 1K K1 F1 A_DDR3_CSB2 CS VDDQ_6
A_DDR3_DQ[5] C18 M30 B_DDR3_DQ[5] 0.1uF 1000pF A_DDR3_ODT ODT VDDQ_7 K1 F1
1% 1% J3 H2
A_DDR3_DQ5 B_DDR3_DQ5 A_DDR3_ODT ODT VDDQ_7
A_DDR3_DQ[6] B22 T31 B_DDR3_DQ[6] A_DDR3_RASZ RAS VDDQ_8 J3 H2
A_DDR3_DQ6 B_DDR3_DQ6 K3 H9 A_DDR3_RASZ RAS VDDQ_8
A_DDR3_DQ[7] A18 M32 B_DDR3_DQ[7] A_DDR3_CASZ CAS VDDQ_9 K3 H9
A_DDR3_DQ7 B_DDR3_DQ7 L3 A_DDR3_CASZ CAS VDDQ_9
A_DDR3_DQ[8] E19 N28 B_DDR3_DQ[8] A_DDR3_WEZ WE L3
A_DDR3_DQ8 B_DDR3_DQ8 J1 A_DDR3_WEZ WE
A_DDR3_DQ[9] B21 R31 B_DDR3_DQ[9] NC_1 J1
A_DDR3_DQ9 B_DDR3_DQ9 T2 J9 NC_1
A_DDR3_DQ[10] F18 M27 B_DDR3_DQ[10] A_DDR3_RESET RESET NC_2 T2 J9
A_DDR3_DQ10 B_DDR3_DQ10 L1 A_DDR3_RESET RESET NC_2
A_DDR3_DQ[11] C22 T30 B_DDR3_DQ[11] NC_3 L1
A_DDR3_DQ11 B_DDR3_DQ11 L9 NC_3
A_DDR3_DQ[12] D20 P29 B_DDR3_DQ[12] NC_4 L9
A_DDR3_DQ12 B_DDR3_DQ12 F3 T7 NC_4
A_DDR3_DQ[13] F22 T27 B_DDR3_DQ[13] A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14] F3 T7
A_DDR3_DQ13 B_DDR3_DQ13 G3 A_DDR3_DQS2 DQSL NC_6 A_DDR3_A[14]
A_DDR3_DQ[14] E18 M28 B_DDR3_DQ[14] A_DDR3_DQS0B DQSL G3
A_DDR3_DQ14 B_DDR3_DQ14 A_DDR3_DQS2B DQSL
A_DDR3_DQ[15] D22 T29 B_DDR3_DQ[15]
A_DDR3_DQ15 B_DDR3_DQ15 C7 A9
B19 N31 A_DDR3_DQS1 DQSU VSS_1 C7 A9
A_DDR3_DM0 A_DDR3_DM0 B_DDR3_DM0 B_DDR3_DM0 B7 B3 A_DDR3_DQS3 DQSU VSS_1
E21 R28 A_DDR3_DQS1B DQSU VSS_2 B7 B3
A_DDR3_DM1 A_DDR3_DM1 B_DDR3_DM1 B_DDR3_DM1 E1 A_DDR3_DQS3B DQSU VSS_2
VSS_3 E1
E7 G8 VSS_3
A21 R32 A_DDR3_DM0 DML VSS_4 E7 G8
A_DDR3_DQS0 A_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_DQS0 D3 J2 A_DDR3_DM2 DML VSS_4
B20 P31 A_DDR3_DM1 DMU VSS_5 D3 J2
A_DDR3_DQS0B A_DDR3_DQS0B B_DDR3_DQS0B B_DDR3_DQS0B J8 A_DDR3_DM3 DMU VSS_5
C20 P30 A_DDR3_DQ[0-15] VSS_6 J8
A_DDR3_DQS1 A_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_DQS1
A_DDR3_DQ[0] E3 M1 A_DDR3_DQ[16-31] VSS_6
C19 N30 DQL0 VSS_7 A_DDR3_DQ[16] E3 M1
A_DDR3_DQS1B A_DDR3_DQS1B B_DDR3_DQS1B B_DDR3_DQS1B
A_DDR3_DQ[1] F7 M9 DQL0 VSS_7
DQL1 VSS_8 A_DDR3_DQ[17] F7 M9
A_DDR3_DQ[16-31] B_DDR3_DQ[16-31]
A_DDR3_DQ[2] F2 P1 DQL1 VSS_8
A_DDR3_DQ[16] B27 AA31 B_DDR3_DQ[16] DQL2 VSS_9 A_DDR3_DQ[18] F2 P1
A_DDR3_DQ16 B_DDR3_DQ16
A_DDR3_DQ[3] F8 P9 DQL2 VSS_9
A_DDR3_DQ[17] A24 V32 B_DDR3_DQ[17] DQL3 VSS_10 A_DDR3_DQ[19] F8 P9
A_DDR3_DQ17 B_DDR3_DQ17
A_DDR3_DQ[4] H3 T1 DQL3 VSS_10
A_DDR3_DQ[18] C27 AA30 B_DDR3_DQ[18] DQL4 VSS_11 A_DDR3_DQ[20] H3 T1
A_DDR3_DQ18 B_DDR3_DQ18
A_DDR3_DQ[5] H8 T9 DQL4 VSS_11
A_DDR3_DQ[19] C24 V30 B_DDR3_DQ[19] DQL5 VSS_12 A_DDR3_DQ[21] H8 T9
A_DDR3_DQ19 B_DDR3_DQ19
A_DDR3_DQ[6] G2 DQL5 VSS_12
A_DDR3_DQ[20] A28 AB32 B_DDR3_DQ[20] DQL6 A_DDR3_DQ[22] G2
A_DDR3_DQ20 B_DDR3_DQ20
A_DDR3_DQ[7] H7 DQL6
A_DDR3_DQ[21] E24 V28 B_DDR3_DQ[21] DQL7 A_DDR3_DQ[23] H7
A_DDR3_DQ21 B_DDR3_DQ21 +1.5V_U_DDR A_DDR3_CKE B1 DQL7
A_DDR3_DQ[22] B28 AB31 B_DDR3_DQ[22] VSSQ_1 B1
A_DDR3_DQ22 B_DDR3_DQ22
A_DDR3_DQ[8] D7 B9 VSSQ_1
A_DDR3_DQ[23] B23 U31 B_DDR3_DQ[23] R13112 DQU0 VSSQ_2 A_DDR3_DQ[24] D7 B9
A_DDR3_DQ23 B_DDR3_DQ23
R13102
1K
A_DDR3_DQ[9] C3 D1 DQU0 VSSQ_2
1K DQU1 VSSQ_3
A_DDR3_DQ[24] D25 W29 B_DDR3_DQ[24] A_DDR3_DQ[25] C3 D1
A_DDR3_DQ24 B_DDR3_DQ24
A_DDR3_DQ[10] C8 D8 DQU1 VSSQ_3
A_DDR3_DQ[25] E27 AA28 B_DDR3_DQ[25] A_DDR3_RESET DQU2 VSSQ_4 A_DDR3_DQ[26] C8 D8
A_DDR3_DQ25 B_DDR3_DQ25
A_DDR3_DQ[11] C2 E2 DQU2 VSSQ_4
A_DDR3_DQ[26] C25 W30 B_DDR3_DQ[26] DQU3 VSSQ_5 A_DDR3_DQ[27] C2 E2
A_DDR3_DQ26 B_DDR3_DQ26
A_DDR3_DQ[12] A7 E8 DQU3 VSSQ_5
A_DDR3_DQ[27] D28 AB29 B_DDR3_DQ[27] DQU4 VSSQ_6 A_DDR3_DQ[28] A7 E8
A_DDR3_DQ27 B_DDR3_DQ27
A_DDR3_DQ[13] A2 F9 DQU4 VSSQ_6
A_DDR3_DQ[28] E26 Y28 B_DDR3_DQ[28] DQU5 VSSQ_7 A_DDR3_DQ[29] A2 F9
A_DDR3_DQ28 B_DDR3_DQ28
A_DDR3_DQ[14] B8 G1 DQU5 VSSQ_7
A_DDR3_DQ[29] E28 AB28 B_DDR3_DQ[29] DQU6 VSSQ_8 A_DDR3_DQ[30] B8 G1
A_DDR3_DQ29 B_DDR3_DQ29
A_DDR3_DQ[15] A3 G9 DQU6 VSSQ_8
A_DDR3_DQ[30] E25 W28 B_DDR3_DQ[30] DQU7 VSSQ_9 A_DDR3_DQ[31] A3 G9
A_DDR3_DQ30 B_DDR3_DQ30 DQU7 VSSQ_9
A_DDR3_DQ[31] C28 AB30 B_DDR3_DQ[31]
A_DDR3_DQ31 B_DDR3_DQ31 +1.5V_U_DDR B_DDR3_CKE
B24 V31
A_DDR3_DM2 A_DDR3_DM2 B_DDR3_DM2 B_DDR3_DM2
B26 Y31
A_DDR3_DM3 A_DDR3_DM3 B_DDR3_DM3 B_DDR3_DM3 R13113
R13103 1K
1K
B25 W31
A_DDR3_DQS2 A_DDR3_DQS2 B_DDR3_DQS2 B_DDR3_DQS2
A25 W32 B_DDR3_RESET
A_DDR3_DQS2B A_DDR3_DQS2B B_DDR3_DQS2B B_DDR3_DQS2B
D26 Y29
A_DDR3_DQS3 A_DDR3_DQS3 B_DDR3_DQS3 B_DDR3_DQS3
C26 Y30
A_DDR3_DQS3B A_DDR3_DQS3B B_DDR3_DQS3B B_DDR3_DQS3B
* DDR_VTT
DDR_VTT_URSA_0
+1.5V_U_DDR
+3.3V_NORMAL
R13100
10K 1%
IC13100
TPS51200DRCR [EP] L13101
C13199
AR13101 AR13103 AR13105 AR13107 AR13109 AR13111 AR13113
IC2900
10uF
R13101 C13122
CIS21J121 10V 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
10K 1000pF IC2800 U_MVREFCA_B1
REFIN VIN
1% 1 10
H5TQ1G63EFR-RDC
THERMAL
U_MVREFCA_B0
11
VLDOIN PGOOD C13150
2 9 4700pF N3 M8
B_DDR3_A[0] A0 VREFCA
DDR_VTT_URSA VO GND
P7
C13123 B_DDR3_A[1] A1
3 8
22uF N3 M8 P3
10V B_DDR3_A[0] A0 VREFCA B_DDR3_A[2] A2
L13100 PGND EN P7 N2 H1
CIS21J121
4 7 B_DDR3_A[1] A1 B_DDR3_A[3] A3 VREFDQ
P3 P8
VOSNS REFOUT
B_DDR3_A[2] A2 B_DDR3_A[4] A4
5 6 N2 H1 P2
B_DDR3_A[3] A3 VREFDQ B_DDR3_A[5] A5
C13110 C13111 C13113 C13147 P8 R8 L8 R13135 240
10uF 10uF 10uF 0.1uF B_DDR3_A[4] A4 B_DDR3_A[6] A6 ZQ
P2 R2 1%
B_DDR3_A[5] A5 B_DDR3_A[7] A7 +1.5V_U_DDR
Close to REFOUT pin
R8 L8 R13127 240
T8
B_DDR3_A[6] A6 ZQ B_DDR3_A[8] A8
R2 1%
R3 B2
B_DDR3_A[7] A7 +1.5V_U_DDR B_DDR3_A[9] A9 VDD_1
T8 L7 D9
B_DDR3_A[8] A8 B_DDR3_A[10] A10/AP VDD_2
R3 B2 R7 G7
B_DDR3_A[9] A9 VDD_1 B_DDR3_A[11] A11 VDD_3
L7 D9 N7 K2
B_DDR3_A[10] A10/AP VDD_2 B_DDR3_A[12] A12/BC VDD_4
R7 G7 T3 K8
B_DDR3_A[11] A11 VDD_3 B_DDR3_A[13] NC_7 VDD_5
N7 K2 N1
B_DDR3_A[12] A12/BC VDD_4 B_DDR3_A[14] VDD_6
T3 K8 M7 N9
B_DDR3_A[13] NC_7 VDD_5 B_DDR3_A[15] NC_5 VDD_7
DDR_VTT_URSA N1
DDR_VTT_URSA_0 R1
L13102 VDD_6 VDD_8
BLM18PG121SN1D M7 N9 M2 R9
B_DDR3_A[15] NC_5 VDD_7 B_DDR3_BA[0] BA0 VDD_9
R1 N8 +1.5V_U_DDR
C13181 C13179 C13189 C13151
VDD_8 B_DDR3_BA[1] BA1
C13105 M2 R9 M3
1uF 0.1uF 0.1uF 0.1uF
25V 16V 16V 16V
0.1uF B_DDR3_BA[0] BA0 VDD_9 B_DDR3_BA[2] BA2
16V N8 A1
B_DDR3_BA[1] BA1 VDDQ_1
M3 +1.5V_U_DDR
R13125R13124
B_DDR3_MCLK J7 A8
B_DDR3_BA[2] BA2 B_DDR3_MCLK CK VDDQ_2
56
C13234 A1 K7 C1
VDDQ_1 B_DDR3_MCLKZ CK VDDQ_3
0.01uF J7 A8 K9 C9
56
DDR_VTT_URSA DDR_VTT_URSA_1 CK VDDQ_2 B_DDR3_CKE CKE VDDQ_4
L13103 K7 C1 D2
BLM18PG121SN1D B_DDR3_MCLKZ CK VDDQ_3 VDDQ_5
K9 C9 L2 E9
B_DDR3_CKE CKE VDDQ_4 B_DDR3_CSB2 CS VDDQ_6
D2 K1 F1
C13112 C13132 C13158 C13174 C13106 VDDQ_5 B_DDR3_ODT ODT VDDQ_7
1uF 0.1uF 0.1uF 0.1uF 0.1uF L2 E9 J3 H2
25V 16V 16V 16V 16V B_DDR3_CSB1 CS VDDQ_6 B_DDR3_RASZ RAS VDDQ_8
K1 F1 K3 H9
B_DDR3_ODT ODT VDDQ_7 B_DDR3_CASZ CAS VDDQ_9
J3 H2 L3
B_DDR3_RASZ RAS VDDQ_8 B_DDR3_WEZ WE
K3 H9 J1
B_DDR3_CASZ CAS VDDQ_9 NC_1
L3 T2 J9
B_DDR3_WEZ WE B_DDR3_RESET RESET NC_2
J1 L1
NC_1 NC_3
T2 J9 L9
B_DDR3_RESET RESET NC_2 NC_4
L1 F3 T7
NC_3 B_DDR3_DQS2 DQSL NC_6 B_DDR3_A[14]
L9 G3
NC_4 B_DDR3_DQS2B DQSL
F3 T7
Decap removed B_DDR3_DQS0
G3
DQSL NC_6 B_DDR3_A[14]
C7 A9
B_DDR3_DQS0B DQSL B_DDR3_DQS3 DQSU VSS_1
B7 B3
C7 A9 B_DDR3_DQS3B DQSU VSS_2
E1
B_DDR3_DQS1 DQSU VSS_1 VSS_3
B7 B3 E7 G8
B_DDR3_DQS1B DQSU VSS_2 B_DDR3_DM2 DML VSS_4
E1 D3 J2
VSS_3 B_DDR3_DM3 DMU VSS_5
E7 G8 J8
B_DDR3_DM0 DML VSS_4 B_DDR3_DQ[16-31] VSS_6
D3 J2 B_DDR3_DQ[16] E3 M1
B_DDR3_DM1 DMU VSS_5 DQL0 VSS_7
J8 B_DDR3_DQ[17] F7 M9
B_DDR3_DQ[0-15] VSS_6 DQL1 VSS_8
B_DDR3_DQ[0] E3 M1 B_DDR3_DQ[18] F2 P1
DQL0 VSS_7 DQL2 VSS_9
B_DDR3_DQ[1] F7 M9 B_DDR3_DQ[19] F8 P9
DQL1 VSS_8 DQL3 VSS_10
B_DDR3_DQ[2] F2 P1 B_DDR3_DQ[20] H3 T1
DQL2 VSS_9 DQL4 VSS_11
+1.5V_U_DDR B_DDR3_DQ[3] F8 P9 B_DDR3_DQ[21] H8 T9
DQL3 VSS_10 DQL5 VSS_12
Close to DDR Power pin B_DDR3_DQ[4] H3 T1 B_DDR3_DQ[22] G2
DQL4 VSS_11 DQL6
B_DDR3_DQ[5] H8 T9 B_DDR3_DQ[23] H7
DQL5 VSS_12 DQL7
B_DDR3_DQ[6] G2 B1
DQL6 VSSQ_1
B_DDR3_DQ[7] H7 B_DDR3_DQ[24] D7 B9
C13104 C13109 C13117 C13128 C13137 C13146 C13156 C13164 C13172 C13178 C13186 C13194 C13198 C13206 C13214 C13218 C13226 DQL7
B1 DQU0 VSSQ_2
B_DDR3_DQ[25] C3 D1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF B_DDR3_DQ[8] D7
VSSQ_1
B9 DQU1 VSSQ_3
B_DDR3_DQ[26] C8 D8
16V 16V 16V 16V 16V 16V 16V 16V 25V 16V 16V 10V 16V 16V 16V 16V 25V B_DDR3_DQ[9] C3
DQU0 VSSQ_2
D1 DQU2 VSSQ_4
B_DDR3_DQ[27] C2 E2
DQU1 VSSQ_3 DQU3 VSSQ_5
B_DDR3_DQ[10] C8 D8 B_DDR3_DQ[28] A7 E8
DQU2 VSSQ_4 DQU4 VSSQ_6
B_DDR3_DQ[11] C2 E2 B_DDR3_DQ[29] A2 F9
DQU3 VSSQ_5 DQU5 VSSQ_7
B_DDR3_DQ[12] A7 E8 B_DDR3_DQ[30] B8 G1
DQU4 VSSQ_6 DQU6 VSSQ_8
B_DDR3_DQ[13] A2 F9 B_DDR3_DQ[31] A3 G9
DQU5 VSSQ_7 DQU7 VSSQ_9
B_DDR3_DQ[14] B8 G1
DQU6 VSSQ_8
B_DDR3_DQ[15] A3 G9
+1.5V_U_DDR DQU7 VSSQ_9
Close to DDR Power pin
C13102 C13107 C13115 C13126 C13135 C13144 C13154 C13162 C13170 C13176 C13184 C13192 C13196 C13204 C13212 C13216 C13224 C13232 C13100 C13101
0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
16V 16V 25V 16V 16V 16V 16V 10V 16V 16V 16V 16V 16V 16V 25V 16V 16V 16V 10V 10V
4th layer
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13103 C13108 C13116
0.1uF 0.1uF 0.1uF
16V 16V 16V
BSD-14Y-UD-131-HD
+1.5V_U_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
Close to DDR Power pin SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
Decap removed FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
C13195 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
0.1uF THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
16V
2013.12.17
4th layer
URSA7_DDR
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
URSA9 Option
URSA_RX_LVDS
Div_BIT0_1
Div_BIT1_1
URSA_BIT0_1
LGD_Module
URSA_BIT1_1
URSA_BIT2_1
Clock for URSA9 URSA Reset
R1911 10K
R1913 10K
R1915 10K
R1917 10K
R13217 10K
R13219 10K
R13202 10K
R13213 10K
R13215 10K
R1909 10K
+3.3V_NORMAL
OPT
OPT
OPT
C1992
LM14_URSA9_crystalcap SW1901 BIT [1/0] Module Division
URSA_OPT_5
JTP-1127WEM +3.3V_NORMAL
8pF
50V
0/0 Non Division
URSA_OPT_6
1 2 OPT 0/1 2 Division
X-TAL_1
XIN_URSA C1996 1/0 4 Division
Div_BIT0
Division Type
GND_1
22uF R1919 1/1 8 Division Div_BIT1
3 4 10V 10K
URSA9_RST_PULLUP URSA_OPT_4
Module Type
R1925
URSA_OPT_0
URSA_RESET
2
1
Rx Interface
24MHz
X1900
0 URSA_OPT_1
1N4148W
1M
R1924 BIT [2/1/0] Tx Lane Tx Lane
URSA_BIT0
D1900
C1993
R1923
100V
URSA_RESET_SoC 0/0/0 4K@120 (16lane)
3
4
URSA_BIT1
8pF
50V
10K
0 0/0/1 4k@60 (8lane)
X-TAL_2
GND_2
R1930 0/1/0 5k@120 (20lane)
URSA_BIT2
XO_URSA
URSA_BIT1_0
URSA_BIT2_0
Div_BIT0_0
Div_BIT1_0
0/1/1 OLED ULTRA HD
URSA_BIT0_0
URSA_RX_VX1
10K
10K
10K
URSA_RESET_MICOM
10K
10K
OS_Module
R13218 10K
R13220 10K
R13212 10K
R13214 10K
R13216 10K
Reserved
Reserved
Reserved
0 1/0/0 FHD@120 (4lane)
R13221 1/0/1 FHD@60 (2lane)
R1916
R1918
R1910
R1912
R1914
URSA_RESET_MICOM 1/1/0 Reserved
1/1/1 Reserved
IC2500
LGE7411(URSA9)
URSA9_PQ_DEBUG
+3.3V_NORMAL AF29 AG25
URSA_RESET RESET I2C_HSC_SDA/VSYNC_LIKE2
AH25
URSA9_PQ_DEBUG I2C_HSC_SCL/VSYNC_LIKE3
R3
R13226
IC1901-*1 P1906 XIN_URSA XTALO
W25Q32BVSSIG 12507WS-04L R4 AH28
SPI Flash
10K
XO_URSA XTALI SPI1_CK/PWM2/GPIO58 URSA_OPT_0
Module Division OPT
AJ27
SPI1_DI/PWM3/GPIO59 Div_BIT0
/CS VCC
1 8 1 AJ24 AJ29
I2CS_SDA SPI2_CK/PWM0/GPIO56 Div_BIT1 +3.3V_NORMAL
R13222 I2CS_SDA AR13201 AH24 AF27
DO[IO1] /HOLD[IO3] I2CS_SCL 33 I2CS_SCL SPI2_DI/PWM1/GPIO57 URSA_OPT_4
2 7 2 33 C1990 C1991
47pF 47pF
AG28 OPT
SPI3_CK/DIM10/GPIO54 URSA_OPT_5 R1936
URSA9_PQ_DEBUG 50V 50V 10K
/WP[IO2] CLK OPT OPT AH26 AH27
3 6 3 I2CM_SDA SPI3_DI/DIM11/GPIO55 URSA_OPT_6
AG24 AG27 R1935 33
+3.3V_NORMAL R13223 I2CM_SCL/VSYNC_LIKE1 SPI4_CK/DIM8/GPIO52 3D_EN
GND
4 5
DI[IO0]
33 AG26 R1934 33
4 R1937
IC1901 URSA9_PQ_DEBUG B4
SPI4_DI/DIM9/GPIO53 L_DIM_EN
10K
OPT
MX25L3206EM2I-12G 5 C1998
0.1uF A4
GPIO[0][UART2_TX]
AF28
OPT
R13203 33
SPI_4MB_Winbond 16V GPIO[1][UART2_RX] VSYNC_LIKE/PWM5/GPIO40
URSA9_PQ_DEBUG
URSA9_SYS_DEBUG
CS# VCC C1995 B5
1 8 0.1uF GPIO[2][UART1_TX]
SPI_CZ_URSA9 SPI_4MB_MACRONIX 16V URSA9_SYS_DEBUG
+3.3V_NORMAL R13225 A5 AG23 +3.3V_NORMAL
33 GPIO[3][UART1_RX] DIM0/GPIO[32] DIM0
R13227
P1907
Change pin from A5 to C4
AG20
R1904 SO/SIO1 HOLD# 12507WS-04L URSA9_SYS_DEBUG DIM1/GPIO[33] DIM1 OPT
33 2 7 AH23 R13204
SPI_DO_URSA9 10K DIM2 10K
DIM2/GPIO[34]
10K R1903 +3.3V_NORMAL AD28 AH20
1
SPI_CZ_URSA9 SPI_CZ DIM3/GPIO[35]
1K WP# SCLK AD30 AG21
R1905 3 6 SPI_CK_URSA9 SPI_CK DIM4/GPIO[36] URSA_OPT_1
FLASH_WP_URSA SPI_CK_URSA9 AR13200 AC31 AH22 R13205
U_SPI_WP_f_URSA 2 1K SPI_DI_URSA9 33 SPI_DI DIM5/GPIO[37] URSA_BIT0 10K
AD29 AG22
GND SI/SIO0 R1954 SPI_DO_URSA9 SPI_DO DIM6/GPIO[38] URSA_BIT1
R1932 1K 4 5 3 AH21
FRC_FLASH_WP SPI_DI_URSA9 OPT DIM7/GPIO[39] URSA_BIT2
33 R1981 AE28
U_SPI_WP_f_SoC INT_R21/GPIO[41]
4
TCON_I2C_EN Ready OPT 33 R1933 AE27
URSA9_SYS_DEBUG 10K INT_R20/GPIO[42]
5 A3
C1997 R1955 GPIO43/TCON0
0.1uF B3
16V GPIO44/TCON1
A2
R13224 GPIO45/TCON2
33 C4 C3
IRE GPIO46/TCON3
URSA9_SYS_DEBUG B2
GPIO47/TCON4
URSA9 UART1_RX B1
GPIO48/TCON5
C2
GPIO49/TCON6
AC27 C1
GND_1 GPIO50/TCON7
AD27
GND_2
AG4
GPIO[18]/TCON8
A7 AG5 HDMI OUTPUT_SIL9617 DDC to URSA9_1
NC_1 GPIO[19]/TCON9
B6 AH4
Chip Config NC_2 GPIO[20]/TCON10
Debugging for URSA9 B7
C5
NC_3 GPIO[21]/TCON11
AH5
AH6
Debug/ISP ADDR NC_4 GPIO[22]/TCON12
Slave (Debug Port:0XB4,ISP:0X98) C6 AJ4
NC_5 GPIO[23]/TCON13
CHIP_CONF:{DIM2,DIM1,DIM0} C7 AJ5
CHIP_CONF=3’d7:111:boot from SPI Flash I2C_S Port NC_6 GPIO24/TCON14
D4 AJ6
NC_7 GPIO25/TCON15
P1905 D5
12507WS-04L NC_8
D6 AH16 R13210 0
WAFER-STRAIGHT Data_Format_1
URSA_DEBUG
NC_9 GPIO[4]
D7 AG16 R13211 0
+3.3V_NORMAL DIM0 1 SW1902 NC_10 GPIO[5] Data_Format_0 HDMI OUTPUT_R9531AN DDC to URSA9_0
JS2235S E4 Y5
NC_11 GPIO[6] RXBSCL_URSA9
OPT 10K E5 Y4
2 RXBSDA_URSA9
NC_12 GPIO[7]
10K R1908 I2C_SCL4 1 6 I2C_SDA4 E6 AB4
DIM1 R1922 R1958 R1959 NC_13 GPIO[8]
R1902 3 33
SCL2_+3.3V_DB 0 0 E7 AB5 For DFT JIG
URSA_MP URSA_MP
OPT 10K URSA_DEBUG
I2CS_SCL 2 5 I2CS_SDA NC_14 GPIO[9] OPT
R1960 URSA_DEBUG_SW R1961
F4 AG17 R13207 33
R13206 R13209
R1921 33 0 0 NC_15 GPIO[10]/PWM_DIM_IN[0] OPT 100K 100K
4 SDA2_+3.3V_DB
10K R1907 URSA_DEBUG
OPT
3 4
OPT F5 AH17 R13208 33
SCL2_+3.3V_DB SDA2_+3.3V_DB NC_16 GPIO[11]/PWM_DIM_IN[1]
R1991 DIM2 5 M5 AG18 10K R13201
NC_17 GPIO[12] URSA_RX_Vx1_HTPDn
OPT 10K M6 AJ20 10K R13200
NC_18 GPIO[13] URSA_RX_Vx1_HTPDn
M7 AH18 URSA9_Vx1_RX_HTPD_GPIO
10K R1906 NC_19 GPIO[14] URSA9_CONNECT
R1990 N5 AG19
NC_20 GPIO[15] LOCKAn_OSD
R7 AH19
NC_21 GPIO[16] LOCKAn_Video
P7 AJ21
NC_22 GPIO[17] FLASH_WP_URSA
N7
NC_23
N6
NC_24
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-132-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
IC2500 LGE7411(URSA9)
LGE7411(URSA9)
D18 D24
A8 T13 VSS_285 VSS_389
VSS_81 VSS_186 G18 F24
B8 R13 VSS_286 VSS_390
VSS_82 VSS_187 H18 G24
C8 P13 VSS_287 VSS_391
VSS_83 VSS_188 J18 H24
D8 N13 VSS_288 VSS_392
VSS_84 VSS_189 L18 J24
E8 M13 VSS_289 VSS_393
VSS_85 VSS_190 N18 K24
F8 U13 VSS_290 VSS_394
VSS_86 VSS_191 P18 L24
G8 V13 VSS_291 VSS_395
VSS_87 VSS_192 R18 M24
H8 W13 VSS_292 VSS_396
VSS_88 VSS_193 T18 N24
J8 Y13 VSS_293 VSS_397
VSS_89 VSS_194 U18 P24
K8 AA13 VSS_294 VSS_398
IC2500 VSS_90 VSS_195 V18 R24
L8 AB13 VSS_295 VSS_399
LGE7411(URSA9) VSS_91 VSS_196 W18 T24
M8 AD13 VSS_296 VSS_400
VSS_92 VSS_197 Y18 U24
VDDC N8 AE13 VSS_297 VSS_401
VSS_93 VSS_198 AA18 V24
P8 AF13 VSS_298 VSS_402
VSS_94 VSS_199 AB18 W24
A6 K1 R8 AG13 VSS_299 VSS_403
VDDC_1 VSS_1 VSS_95 VSS_200 AE18 Y24
M9 T1 T8 AH13 VSS_300 VSS_404
VDDC_2 VSS_2 VSS_96 VSS_201 AF18 AA24
M10 K2 U8 AJ13 VSS_301 VSS_405
VDDC_3 VSS_3 VSS_97 VSS_202 AJ18 AB24
M11 P2 V8 G14 VSS_302 VSS_406
VDDC_4 VSS_4 VSS_98 VSS_203 F19 AC24
N9 T2 W8 H14 VSS_303 VSS_407
VDDC_5 VSS_5 VSS_99 VSS_204 G19 AD24
N10 AF2 Y8 J14 VSS_304 VSS_408
VDDC_6 VSS_6 VSS_100 VSS_205 H19 AE24
N11 K3 AA8 K14 VSS_305 VSS_409
VDDC_7 VSS_7 VSS_101 VSS_206 J19 AF24
P9 T3 L14 VSS_306 VSS_410
VDDC_8 VSS_8 VSS_207 K19
P10 AF3 AC8 P14 VSS_307
VDDC_9 VSS_9 VSS_102 VSS_208 L19 AL24
P11 AG3 AD8 R14 VSS_308 VSS_411
VDDC_10 VSS_10 VSS_103 VSS_209 N19 F25
R9 G4 AE8 T14 VSS_309 VSS_412
VDDC_11 VSS_11 VSS_104 VSS_210 P19 G25
R10 H4 AF8 U14 VSS_310 VSS_413
VDDC_12 VSS_12 VSS_105 VSS_211 R19 H25
R11 J4 AG8 V14 VSS_311 VSS_414
VDDC_13 VSS_13 VSS_106 VSS_212 T19 J25
T9 K4 AH8 W14 VSS_312 VSS_415
VDDC_14 VSS_14 VSS_107 VSS_213 U19 K25
T10 P4 AJ8 Y14 VSS_313 VSS_416
VDDC_15 VSS_15 VSS_108 VSS_214 V19 L25
T11 T4 B9 AA14 VSS_314 VSS_417
VDDC_16 VSS_16 VSS_109 VSS_215 W19 M25
U9 U4 D9 AB14 VSS_315 VSS_418
VDDC_17 VSS_17 VSS_110 VSS_216 Y19 N25
U10 V4 E9 AE14 VSS_316 VSS_419
VDDC_18 VSS_18 VSS_111 VSS_217 AB19 P25
U11 W4 F9 AF14 VSS_317 VSS_420
VDDC_19 VSS_19 VSS_112 VSS_218 AC19 R25
V9 AA4 G9 AG14 VSS_318 VSS_421
VDDC_20 VSS_20 VSS_113 VSS_219 AD19 T25
V10 AC4 H9 AH14 VSS_319 VSS_422
VDDC_21 VSS_21 VSS_114 VSS_220 AE19 U25
V11 AD4 J9 AJ14 VSS_320 VSS_423
VDDC_22 VSS_22 VSS_115 VSS_221 AF19 V25
W9 AE4 K9 A15 VSS_321 VSS_424
VDDC_23 VSS_23 VSS_116 VSS_222 AK19 W25
W10 AF4 L9 B15 VSS_322 VSS_425
VDDC_24 VSS_24 VSS_117 VSS_223 A20 Y25
W11 G5 D15 VSS_323 VSS_426
VDDC_25 VSS_25 VSS_224 E20 AA25
Y9 H5 VSS_324 VSS_427
VDDC_26 VSS_26 F20 AB25
J5 AD9 G15 VSS_325 VSS_428
VSS_27 VSS_118 VSS_225 G20 AC25
K5 AE9 H15 VSS_326 VSS_429
AVDDL_HDMI_TX_RX VSS_28 VSS_119 VSS_226 H20 AD25
L5 AF9 J15 VSS_327 VSS_430
VSS_29 VSS_120 VSS_227 J20 AE25
AG9 K15 VSS_328 VSS_431
VSS_121 VSS_228 L20 AF25
L3 P5 AH9 L15 VSS_329 VSS_432
AVDDL_HDMITX_1 VSS_30 VSS_122 VSS_229 N20 AM25
AVDDL_LVDSRX L4 R5 AJ9 M15 VSS_330 VSS_433
AVDDL_HDMITX_2 VSS_31 VSS_123 VSS_230 P20 A26
AA9 T5 N15 VSS_331 VSS_434
AVDDL_RX_1 VSS_32 VSS_231 R20 F26
AA10 U5 D10 P15 VSS_332 VSS_435
AVDDL_RX_2 VSS_33 VSS_124 VSS_232 T20 G26
AB9 V5 E10 R15 VSS_333 VSS_436
AVDDL_RX_3 VSS_34 VSS_125 VSS_233 U20 H26
F10 T15 VSS_334 VSS_437
VSS_126 VSS_234 V20 J26
Y10 W5 G10 U15 VSS_335 VSS_438
AVDDL_DVI_1 VSS_35 VSS_127 VSS_235 W20 K26
Y11 AA5 H10 V15 VSS_336 VSS_439
AVDDL_DVI_2 VSS_36 VSS_128 VSS_236 AE20 L26
DVDD_DDR AC5 J10 W15 VSS_337 VSS_440
VSS_37 VSS_129 VSS_237 AF20 M26
M14 AD5 K10 Y15 VSS_338 VSS_441
DVDD_DDR_1 VSS_38 VSS_130 VSS_238 AK20 N26
N14 AE5 L10 AA15 VSS_339 VSS_442
AVDDL_MOD DVDD_DDR_2 VSS_39 VSS_131 VSS_239 P26
AF5 AB10 AE15 VSS_443
VSS_40 VSS_132 VSS_240 D21 R26
Y20 F6 AC10 AF15 VSS_340 VSS_444
AVDDL_MOD_1 VSS_41 VSS_133 VSS_241 F21 T26
Y21 G6 AD10 AG15 VSS_341 VSS_445
AVDDL_MOD_2 VSS_42 VSS_134 VSS_242 G21 U26
Y22 H6 AE10 AH15 VSS_342 VSS_446
AVDDL_MOD_3 VSS_43 VSS_135 VSS_243 H21 V26
AA19 J6 AF10 AJ15 VSS_343 VSS_447
AVDDL_MOD_4 VSS_44 VSS_136 VSS_244 J21 W26
AA20 K6 AG10 E16 VSS_344 VSS_448
AVDDL_DRV AVDDL_MOD_5 VSS_45 VSS_137 VSS_245 K21 Y26
AA21 L6 AH10 F16 VSS_345 VSS_449
AVDDL_DRV_1 VSS_46 VSS_138 VSS_246 L21 AA26
AA22 AJ10 G16 VSS_346 VSS_450
AVDDL_DRV_2 VSS_139 VSS_247 T21 AB26
AB20 P6 A11 H16 VSS_347 VSS_451
AVDDL_DRV_3 VSS_47 VSS_140 VSS_248 U21 AC26
AB21 R6 D11 J16 VSS_348 VSS_452
AVDDL_DRV_4 VSS_48 VSS_141 VSS_249 V21 AD26
AB22 T6 E11 VSS_349 VSS_453
AVDDL_DRV_5 VSS_49 VSS_142 W21 AE26
U6 F11 L16 VSS_350 VSS_454
AVDD_MOD VSS_50 VSS_143 VSS_250 AE21 AF26
AC20 V6 G11 N16 VSS_351 VSS_455
AVDD_MOD_1 VSS_51 VSS_144 VSS_251 AF21 AJ26
AC21 W6 H11 P16 VSS_352 VSS_456
AVDD_MOD_2 VSS_52 VSS_145 VSS_252 AK21 AL26
AD21 Y6 J11 R16 VSS_353 VSS_457
AVDD_MOD_3 VSS_53 VSS_146 VSS_253 D27
AD20 AA6 K11 T16 VSS_458
AVDD_MOD_LDO VSS_54 VSS_147 VSS_254 F27
VDDP AB6 L11 U16 VSS_459
VSS_55 VSS_148 VSS_255 K27
AC18 AC6 AA11 V16 VSS_460
VDDP_1 VSS_56 VSS_149 VSS_256 G22 N27
AD17 AD6 AB11 W16 VSS_354 VSS_461
VDDP_2 VSS_57 VSS_150 VSS_257 H22 P27
AD18 AE6 AC11 Y16 VSS_355 VSS_462
VDDP_3 VSS_58 VSS_151 VSS_258 J22 R27
AF6 AE11 AA16 VSS_356 VSS_463
VSS_59 VSS_152 VSS_259 U27
AD11 AG6 AF11 AE16 VSS_464
AVDD_DVI_1 VSS_60 VSS_153 VSS_260 L22 V27
AD12 AG11 AF16 VSS_357 VSS_465
AVDD_DVI_2 VSS_154 VSS_261 M22 W27
AC12 F7 AH11 VSS_358 VSS_466
AVDD_HDMITX_1 VSS_61 VSS_155 T22 Y27
AC13 G7 AJ11 VSS_359 VSS_467
AVDD_HDMITX_2 VSS_62 VSS_156 U22 AA27
AD15 H7 AJ16 VSS_360 VSS_468
AVDD_RX_1 VSS_63 VSS_262 V22 AB27
AC16 J7 D12 AM16 VSS_361 VSS_469
AVDD_RX_2 VSS_64 VSS_157 VSS_263 W22
AC17 K7 E12 A17 VSS_362
AVDD_RX_3 VSS_65 VSS_158 VSS_264 AC22 F28
AD16 L7 F12 B17 VSS_363 VSS_470
AVDD_RX_4 VSS_66 VSS_159 VSS_265 AD22 K28
AVDD_PLL G12 G17 VSS_364 VSS_471
VSS_160 VSS_266 AE22 P28
AD14 H12 H17 VSS_365 VSS_472
AVDD_XTAL VSS_161 VSS_267 AF22 U28
AC14 J12 J17 VSS_366 VSS_473
AVDD_PLL_1 VSS_162 VSS_268 AL22 AC28
+1.5V_U_DDR
AC15 T7 K12 K17 VSS_367 VSS_474
AVDD_PLL_2 VSS_67 VSS_163 VSS_269 AK28
M18 U7 L12 L17 VSS_475
AVDD_DDR0_1 VSS_68 VSS_164 VSS_270 A29
M19 V7 M12 N17 VSS_476
AVDD_DDR0_2 VSS_69 VSS_165 VSS_271 A23 C29
M20 W7 N12 P17 VSS_368 VSS_477
AVDD_DDR0_3 VSS_70 VSS_166 VSS_272 E23 D29
M21 Y7 P12 R17 VSS_369 VSS_478
AVDD_DDR0_4 VSS_71 VSS_167 VSS_273 F23 E29
M16 AA7 R12 T17 VSS_370 VSS_479
AVDD_DDR0_5 VSS_72 VSS_168 VSS_274 G23 F29
M17 AB7 T12 U17 VSS_371 VSS_480
AVDD_DDR0_6 VSS_73 VSS_169 VSS_275 H23 J29
AC7 U12 V17 VSS_372 VSS_481
VSS_74 VSS_170 VSS_276 J23 M29
P21 AD7 V12 W17 VSS_373 VSS_482
AVDD_DDR1_1 VSS_75 VSS_171 VSS_277 K23 R29
R21 AE7 W12 Y17 VSS_374 VSS_483
AVDD_DDR1_2 VSS_76 VSS_172 VSS_278 V29
P22 AF7 Y12 AA17 VSS_484
AVDD_DDR1_3 VSS_77 VSS_173 VSS_279 M23 AA29
R22 AG7 AA12 AB17 VSS_375 VSS_485
AVDD_DDR1_4 VSS_78 VSS_174 VSS_280 AC29
N21 AH7 AB12 AE17 VSS_486
AVDD_DDR1_5 VSS_79 VSS_175 VSS_281 P23 AK29
N22 AJ7 AE12 AF17 VSS_376 VSS_487
AVDD_DDR1_6 VSS_80 VSS_176 VSS_282 A30
AF12 VSS_488
VSS_177 T23 B30
AG12 VSS_377 VSS_489
VSS_178 V23 AC30
AH12 AJ17 VSS_378 VSS_490
VSS_179 VSS_283 W23 AK30
AJ12 AL17 VSS_379 VSS_491
VSS_180 VSS_284 Y23 AM30
VSS_380 VSS_492
AA23 A31
VSS_381 VSS_493
AB23 B31
G13 VSS_382 VSS_494
VSS_181 AC23 C31
H13 VSS_383 VSS_495
VSS_182 AD23 J31
J13 VSS_384 VSS_496
VSS_183 AE23 L31
K13 VSS_385 VSS_497
VSS_184 AF23 AD31
L13 VSS_386 VSS_498
VSS_185 AJ23 AF31
VSS_387 VSS_499
AM23 AH31
VSS_388 VSS_500
B32
VSS_501
E32
VSS_502
J32
VSS_503
L32
VSS_504
P32
VSS_505
U32
VSS_506
Y32
VSS_507
AE32
VSS_508
AG32
VSS_509
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-14Y-UD-133-HD
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_Power
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
MAX 4.7A
TCON_PWR_5pin_Wafer
P13401
+12V
+1.5V URSA DDR +1.15V URSA9 Core
+1.5V_U_DDR
20037WR-05A00
T-con power L13411
BLM18PG121SN1D
POWER_ON/OFF2_1 DCDC_TI
IC13403-*1
TPS54327DDAR [EP]GND
1 EN
1 8
VIN
THERMAL
VFB VBST
R13404
10K
9
2 7
C13443 C13410
2 10uF 0.1uF
VREG5
3 6
SW
R13407
R13408
PANEL_VCC DCDC_ROHM
4.87K
1/16W
16V SS GND 39K
IC13403 4 5
R13424 R1
1%
3 TCON_PWR_5pin_Wafer BD9D320EFJ [EP]FIN 1/16W
L13409 10K 5%
1%
1/16W
91K
R13406
MLB-201209-0120P-N2
C13403
R13411R13409
[EP]
GND2
GND1
NC_3
TRIP
4 EN VIN
1/16W 1/16W
1 8 1000pF
100 5.1K
VO
16V 50V R2
1%
1/16W
27K
R13405
THERMAL
1%
TCON_PWR_5pin_Wafer
R13410
0.1uF
1%
1/16W
20K
5 R13421 R13422 FB BOOT C13447
28
27
26
25
24
9
2 7
RF 1 23 FB
L13410 R1
1%
18K 3.6K L13412
6 MLB-201209-0120P-N2 1% 1% THERMAL
C13434 C13435 C13440 C13442 VREG SW 2.2uH PGOOD GND
10uF 0.1uF 10uF 0.1uF 3 6 2 29 22 +12V
25V 25V 25V 25V C13444 R13401 1K
100pF NR5040T2R2N EN 3 21 MODE
OPT 50V POWER_ON/OFF2_3 16V
TCON_PWR_5pin_Wafer SS GND 0.1uF IC13402
TCON_PWR_5pin_Wafer 1.0V_DCDC_TI 4
3A 5 C13448
22uF
C13449
22uF
ZD13401 VBST 4
TPS53513RVER
20 VREG L13402
R13403
10V 10V 2.5V
TCON_PWR_5pin_Wafer C13446-*1 R13423 C13405 NC_1 VDD
OPT 5 19
4.7
3300pF C13445 C13446 C13402 R13400
22K 2K
50V 1uF 2200pF SW_1 NC_2
1% 6 18
10V 50V
0.1uF 1/16W C13407 C13409
1.0V_DCDC_ROHM SW_2 7 17 VIN_3 C13408
R2 16V 5% 1uF 10uF
VDDC 10uF
10V 16V
L13403 SW_3 8 16 VIN_2 16V
Vout=0.765*(1+R1/R2)=1.516V 1uH
SW_4 9
8A 15 VIN_1
R13402
10
11
12
13
14
1/10W
3.3
D13400
C13400 C13401 C13411
5%
C13406
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
22uF 22uF 22uF
OPT
30V
2200pF
ZD13400
50V
2.5V
OPT
C13404
470pF
50V
Vout=0.6*(1+R1/R2)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-134-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
3 A. Video error Picture broken/ Freezing 3
4 Color error 4
Vertical/Horizontal bar
bar, residual image
image,
5 5
light spot, external device color error
6 No power 6
B Power error
B. Off when
h on, off
ff while
hil viewing,
i i power
7 7
auto on/off
8 No audio/Normal video 8
C. Audio error
9 Wrecked audio/discontinuation/noise 9
10 Remote control & Local switch checking 10
11 MR13 operating
i checking
h ki 11
D. Function error
12 Wifi operating checking 12
13 External device recognition error 13
145 E. Noise Circuit noise, mechanical noise 14
15 F. Exterior error Exterior defect 15
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
No video/ Normal audio Revised date 1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable, Speaker Cable, IR B/D Cable,,,)
☞A1 ☞A18
No video Normal Y Check Back Light Y Check Power Normal Y Replace T-con/Main
Normal audio On Board or module
audio On with naked eye Board voltage
24V, 12V,3.5V etc. And Adjust VCOM
N N N
Move to No Check Power Board 24V output Repair Power
☞A18
video/No audio Board or parts
Replace Inverter
Normal Y
or module
voltage
End
N
Repair Power
Board or parts
※Precaution ☞A4 & A2
Always check & record S/W Version and White
Replace Main Board Re-enter White Balance value
Balance value before replacing the Main Board
1
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
No video/ No audio Revised date 2/16
☞A18
Check various Check and
Normal Y
No Video/ voltages of Power replace
No audio Board ( 3.5V,12V,20V voltage?
MAIN B/D
or 24V…)
N End
Replace Power
Board and repair
parts
2
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
Picture broken/ Freezing Revised date 3/16
. By using Digital signal level meter
☞ A3
. By using Diagnostics menu on OSD
Check RF Signal level ( Setting→ Quick Setting → Programmes → Programme Tuning → Manual Tuning → Check the Signal )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Y Check whether other equipments have problem or not.
Normal
(By connecting RF Cable at other equipment)
Signal?
→ DVD Player ,Set-Top-Box,
,Set Top Box, Different maker TV etc`
etc
N
☞ A4
Check RF Cable
Normal Y Check SVC N Check Y
Connection Close
1. Reconnection Picture? S/W Version Bulletin? Tuner soldering
T ld i
2. Install Booster N
Y
N
S/W Upgrade
Normal N Contact with signal distributor
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture? Replace
Main B/D
Y
Close
Close
3
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
Color error Revised date 4/16
☞A6 ☞ A7
※ Check Y
Check color by input
and replace
-External Input Y Y
Color Link Cable Color Color
-COMPONENT
COMPONENT Replace Main B/D Replace module
error? (V by one) error? error?
-AV
and contact
-HDMI N N N
condition
Check error End
color input
mode
☞A8 Check
External Input/ External device Y
external
Ch k T
Check Testt pattern
tt C
Component t /C bl
/Cable R l
Replace M
Main/T-con
i /T B/D
device and
error normal
cable
N
Request repair
for external
device/cable
N
Check external External device Y
HDMI device and /Cable Replace Main/T-con B/D
error cable normal
4
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Error
A. Video error Established
2013.01.31
date
LCD TV symptom Vertical / Horizontal bar, residual image,
light spot, external device color error Revised date 5/16
Vertical/Horizontal bar, residual image, light spot Replace
Module
☞A6
☞ A7 N
Check color condition by input Check external
Check and
-External Input Screen Y device Y Screen N Screen
-Component Normal? replace Link Replace Main/T-con B/D
normal? connection normal? (adjust VCOM) normal?
-HDMI
HDMI Cable
condition
N N For LGD panel Y
Y
Replace Main B/D
Replace Request repair End End
for external
A8
☞A8 module
device
Check Test pattern
For other panel
External device screen error-Color error
Check screen
condition by input
-External Input External
Check S/W Version Check N
-Component Input Connect other external N
version
-HDMI/DVI error device and cable Screen Replace
(Check normal operation of normal? Main/T-con
Y External Input, Component, B/D
Component RGB and HDMI/DVI by
error Y
S/W Upgrade connecting Jig, pattern
Generator ,Set-top Box etc.
Request repair for
external device
Y
Connect other external
Normal N HDMI/
device and cable N
screen? DVI Screen Replace
(Check normal operation of
E t
External
l Input,
I t Component,
C t normal? Main /T-con
Y RGB and HDMI/DVI by B/D
connecting Jig, pattern
Generator ,Set-top Box etc.
End
5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date 2013.01.31
LCD TV symptom
No power Revised date 6/16
☞A17 ☞A18
DC Power on R l
Replace
Check Power LED Y Normal N Check Power Y
by pressing Power Key OK? Power
Logo LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red or Turn On
N Y
. Operating: Turn Off
Check Power cord Replace Main B/D
was inserted properly
☞A18
N Measure voltage of each output of Power B/D
Normal?
Y
Y Y
Normal
※ voltage?
g
Replace Main B/D
Close Normal
Check ST-BY 3.5V
Y
voltage? N
☞A18 Replace Power B/D
N
Replace Power
B/D
6
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date 2013.01.31
LCD TV symptom
Off when on
on, off while viewing,
viewing power auto on/off Revised date 7/16
Check outlet
☞A19
N Y
Check A/C cord Error? Check Power Off CPU Normal? End
Replace Main B/D
Mode Abnormal
N
Check for all 3- phase
power out Y Abnormal Replace Power B/D
1
Fix A/C cord & Outlet ☞A18
and check each 3
(If Power Off mode
phase out
is not displayed) Normal Y
Replace Main B/D
Check Power B/D voltage?
voltage
N
※ Caution
Ch k and
Check d fix
fi exterior
i Replace Power B/D
of Power B/D Part
* Please refer to the all cases which Status Power off List Explanation
"POWEROFF REMOTEKEY"
"POWEROFF_REMOTEKEY" P
Power off
ff by
b REMOTE CONTROL
can be displayed on power off mode.
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
N
Normal
l "POWEROFF_ONTIMER"
"POWEROFF ONTIMER" P
Power off
ff by
b ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF UNKNOWN"
"POWEROFF_UNKNOWN" P
Power off
ff by
b unknown
k status
t t exceptt lilisted
t d case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
7
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date 2013.01.31
LCD TV symptom
No audio/ Normal video Revised date 8/16
☞A20 ☞A21+A18
Check user N Check audio B+ Y
No audio Normal
menu > Off 24V of Power
Screen normal voltage
Speaker off Board
Y N
Cancel OFF Replace Power Board and repair parts
Check N
Disconnection Replace MAIN Board End
Speaker
disconnection
Y
Replace Speaker
8
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date 2013.01.31
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Wrecked audio/
☞A21+A18
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (24V)
connector
Check input all audio
signal Y Y
Signal
-RF
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV
N
Wrecked audio/
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
Request repair to external Wrecked audio/ Replace Main B/D End
cable/ANT provider Discontinuation/
Noise only
for External Input
(In case of N
External Input Connect and check Normal
signal error) other external audio?
Check and fix device
external device Y
Check and fix external device
9
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Error
D. Function error Established
2013.01.31
date
LCD TV symptom
Remote control & Local switch checking Revised date 10/16
1. Remote control(R/C) operating error Replace
Main B/D
☞A22 ☞A22 A22
☞A22
Check & Repair N Check B+ Y Y
Check R/C itself Normal Y Normal Normal Check IR Normal
operating? Cable connection operating? 3.5V Voltage? Signal?
Operation Output signal
Connector solder On Main B/D
N
Y N N
☞A18
Check R/C Operating Check & Replace Close Check 3.5v on Power B/D Repair/Replace
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal Y
operating? Close
Explain the customer
cause is interference
from light in room. N
Replace R/C
10
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Error
D. Function error Established
2013.01.31
date
LCD TV symptom
MR13 operating checking Revised date 11/16
2. MR13(Magic Remocon) operating error
☞A4
Check the N Check MR13
RF Receiver ver Normal Y Press the Is show ok N Turn off/on the
INSTART menu is “00.00”? itself Operation operating? set and press
wheel message?
the wheel
N
Y
Y
☞A23
Check & Replace Close
Check & Repair Battery of MR13
RF assy
connection
Normal Y
☞A4 operating? Close
Is show ok N Press the back
RF Receiver ver N message? y about 5sec
key
Cl
Close N
is “00.00”?
Y
Replace
MR13
Y Close
Down load the Firmware
* If you conduct the loop at 3times, change the M4.
* INSTART MENUÆ14.RF
Remocon TestÆ3. Firmware
download
11
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Error
D. Function error Established
2013.01.31
date
LCD TV symptom
Wifi operating checking Revised date 12/16
3.Wifi operating error
☞A4 ☞A24
Check the Wi-Fi Mac value N Check the Wifi wafer Normal N Replace
INSTART menu is “NG”? Voltage?
1pin Main B/D
Y
☞A24 Y
Check & Repair Close
Wifi cable
connection
☞A4
Wi-Fi Mac value N
is “NG”? Close
Y
Change the Wifi
assy
12
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error D. Function error date 2013.01.31
LCD TV symptom
External device recognition error Revised date 14/16
Y Check technical
Check External Input and
Signal information Technical N
input Component Replace Main B/D
input? - Fix information information?
Recognition error
signal
- S/W Version
N Y
HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information
14
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error E. Noise date 2013.01.31
LCD TV symptom
Circuit noise
noise, mechanical noise Revised date 15/16
Identify Check
Circuit
nose location of Replace PSU
noise
type noise
Mechanical Check location of
noise noise
※ When the nose is severe, replace the module
(For models with fix information, upgrade the
S/W or p
provide the description)
p )
※ Mechanical
M h i l noise i iis a natural
t l OR
phenomenon, and apply the 1st level ※ If there is a “Tak Tak” noise from the
description. When the customer does not cabinet, refer to the KMS fix information and
agree, apply the process by stage. then proceed as shown in the solution manual
※ Describe the basis of the description OR
((For models without anyy fix information,,
i “P
in “Partt related
l t d tto nose”” in
i th
the O
Owner’s
’ provide the description)
Manual.
15
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error F. Exterior defect date 2013.01.31
LCD TV symptom
Exterior defect Revised date 16/16
Zoom part with
Z ih Module
Replace module
exterior damage damage
Cabinet
damage Replace cabinet
Remote
controller Replace remote controller
damage
Stand
Replace
ep ace sta
stand
d
dent
16
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process Detail Technical Manual
No. Error symptom Content Page Remarks
1 A. Video error
A error_ No video/Normal Check LCD back light with naked eye A1
2 audio Check White Balance value A2
TUNER input signal strength checking
4 A3
method
A. Video error
A error_ video error /Video
5 lag/stop LCD-TV Version checking method A4
6 Tuner Checking Part A5
A. Video error _Vertical/Horizontal
Vertical/Horizontal bar,
7 LCD TV connection
ti diagram
di A6
residual image, light spot
Check Link Cable (EPI) reconnection
8 A7
A. Video error_ Color error condition
9 Adj
Adjustment Test pattern - ADJ
A J Key
K A8
10 Exchange Main Board (1) A-1/5
11 Exchange Main Board (2) A-2/5
Appendix
12 Defected Type caused by T-Con/ Exchange Power Board (PSU) A-3/5
Inverter/ Module
13 Exchange Module (1) A-4/5
14 Exchange Module (2) A-5/5
A 5/5
Continue to the next page
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No. Error symptom Content Page Remarks
16 Check front display LED A17
B. Power error_ No power
17 Check power input Voltage & ST-BY 3.5V A18
B. Power error_Off when on, off
18 POWER
POW R OFF MODE
MO checking method A19
while
hil viewing
i i
Checking method in menu when there is
19 A20
C. Audio error_ No audio/Normal no audio
video Voltage and speaker checking method
20 A21
when there is no audio
Remote controller operation checking
21 A22
method
Motion Remote operation checking
22 D. Function error A23
method
23 Wifi operation checking method A24
24 Camera operation checking method A25 Not Used
25 E. Etc Tool option changing method A26
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2013.01.31
LCD TV Revised
Content Check LCD back light with naked eye A1
date
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from locations.
* Tuner is different from region
A1
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2014.02.14
LCD TV Revised
Content Check White Balance value A2
date
Entry
Entrymethod
method
1.1.Press
Pressthe
theADJ
ADJbutton
buttonononthe
theremote
remotecontroller
controllerforforadjustment.
adjustment.
2.2.Enter
Enterinto
intoWhite
WhiteBalance
Balanceofofitem
item6.10.
3.3.Aft
3 After
Afterrecording
di the
ththeR,
recording RR,G
G,G,B B(GAIN,
(GAIN
(GAIN,C
Cut)
t) value
Cut) l offofC
value Color
l TTemp
Color Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm), re-enter the value after replacingthe
re-enter the value after replacing theMAIN
MAINBOARD.
BOARD.
A2
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
A. Video error_Video error, video lag/stop 2014.02.14
symptom date
LCD TV Revised
Content TUNER input signal strength checking method A3
date
MENU Æ support Æ signal test
Æ select
l t channel
h l
When the signal is strong, use the
attenuator ((-10dB
10dB, -15dB
15dB, -20dB
20dB etc.)
etc )
A3
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Video error, video lag/stop date
2014.02.14
LCD TV Revised
Content LCD TV Version checking method
LCD-TV A4
date
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller
t ll forf adjustment
dj t t
A4
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Video error, video lag/stop 2014.02.14
LCD TV date
Revised
Content TUNER checking part A5
date
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
g each voltage
2. After measuring g from ppower supply,
pp y, finally
y replace
p the MAIN BOARD.
A5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error A. Video error _Vertical/Horizontal bar, Established 2014.02.14
symptom residual image, light spot date
LCD TV Revised
Content LCD TV connection
ti didiagram (1) date A6
As the part connecting to the external input, check
the screen condition by signal
A6
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Color error date
2014.02.14
LCD TV Revised
Content Ch k Li
Check Link
kCCable
bl (LVDS) reconnection
ti condition
diti date A7
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7 * Tuner is different from region
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Color error 2014.02.14
LCD TV date
Adjustment Test pattern - ADJ Key Revised
Content date A8
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
Solder defect, CNT Broken T-Con
T-Con Defect,
Defect,
Solder
T-Con CNT
CNT
defect,CNT
Defect, Broken
Broken
CNTBroken
Broken Abnormal Power Section
Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack
A - 1/5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (2)
Abnormal Power Section Abnormal Power Section Solder defect
defect, Short/Crack
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
GRADATION Noise GRADATION
A - 2/5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Power Board (PSU)
No Light Dim Light
Dim Light Dim Light
No picture/Sound Ok
A - 3/5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (1)
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Crosstalk Press damage Crosstalk
Un-repairable Cases
In this case p
please exchange
g the module.
Press damage
A - 4/5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (2)
Vertical Block Vertical Line Vertical Block
Source TAB IC Defect S
Source TAB IC D Defect
f t S
Source TAB IC DDefect
f t
Horizontal Block Horizontal Block Horizontal line
Gate TAB IC Defect Gate TAB IC Defect
Gate TAB IC Defect Gate TAB IC Defect Gate TAB IC Defect
Un-repairable Cases
In this case p
please exchange
g the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom B. Power error _No power date
2014.02.07
LCD TV Revised
Content Ch k ffrontt P
Check Power IIndicator
di t date A17
ST-BY
ST BY condition: On or Off
Power ON condition: Turn Off
A17
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
B. Power error _No power 2014.02.05
LCD TV date
Revised
Content Check power input voltage and ST-BY
ST BY 3
3.5V
5V A18
date
Check the DC 24V, 12V, 3.5V.
P_main
P main
Maker : Yeonho
28Pin SMAW200-H28S5K
’14년 적용 28Pin map (LPB)
1 PWR ON 2 DVR_ON
3 P_DIM #1 4 PDIM #2
5 3.5V 6 GND
7 3.5V 8 3.5V
9 GND 10 GND
11 12V 12 12V
13 12V 14 12V
15 12V 16 GND
17 GND 18 24V
19 24V 20 24V
21 24V 22 24V
23 GND 24 GND
25 SCLK 26 GND
27 SIN 28 VSYNC
A18
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error
symptom B. Power error _Off when on, off whiling viewing Established
date
2014.02.05
LCD TV Revised
Content POWER OFF MODE checking
h ki method
th d date A19
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
C. Audio error_No audio/Normal video 2014.02.05
LCD TV date
Revised
Content Ch ki method
Checking th d in
i menu when
h there
th is
i no audio
di date A20
Checking method
1. Press the Setting
g button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Out
p
4. Select TV Speaker
A20
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom C. Audio error_No audio/Normal video date
2014.02.05
LCD TV Revised
Content Voltage and speaker checking method A21
when there is no audio date
1 PWR ON 2 DVR_ON
3 P_DIM #1 4 PDIM #2
5 3.5V 6 GND
7 3 5V
3.5V 8 3 5V
3.5V
①
9 GND 10 GND
② 11 12V 12 12V
13 12V 14 12V
15 12V 16 GND
17 GND 18 24V
19 24V 20 24V
21 24V 22 24V 1 SPK_R-
③
23 GND 24 GND 2 SPK_R+
25 SCLK 26 GND 3 SPK_L-
27 SIN 28 VSYNC 4 SPK_L+
Checking order when there is no audio
1.Check the contact condition of or 24V connector of Main Board
2. Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
3.Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
D. Function error 2014.02.07
symptom date
LCD TV Revised
Content Remote controller operation checking method date A22
1 GND
Front
2 +3.5V WOL
3 BT_RESET
4 USB_DM
5 NC
6 USB_DP
7 WOL
Back 8 GND
9 SDA
10 GND
11 SCL
12 KEY1
13 GND
14 KEY2
③ 15 IR
16 +3.5V_ST
② 17 LED_R
① Wifi/ BT Combo 18 GND
Checking order to check remote controller
Checking
g order
1.Check IR cable condition between IR & Main board.( Check picture number① and ②)
2.Check the standby 3.5V on the terminal 16 pin (③)
3.AS checking the Pre-Amp(IR LED light) , the power is in ON condition, an Analog Tester
needle should move slowly,
slowly otherwise
otherwise, it’s
it s defective
defective.
A22
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
D. Function error 2014.02.07
symptom date
LCD TV Revised
Content M ti
Motion R t / Wifi operation
Remote ti checking
h ki method
th d date A23
1 GND
Front
2 +3.5V WOL
3 BT_RESET
4 USB_DM
5 NC
6 USB_DP
7 WOL
Back 8 GND
9 SDA
10 GND
11 SCL
12 KEY1
13 GND
14 KEY2
③ 15 IR
16 +3.5V_ST
②
17 LED_R
① Wifi/ BT Combo 18 GND
Checking order to check motion remote/wifi
Checking order
1.Check BT/Wifi cable condition between BT/Wifi assy & Main board.
2.Check the 3.5V on the terminal 16
A23
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
1. Circuit Block Diagram
X TAL
X_TAL DDR3 1866 X 16
24MHz (512MB X 2EA)
CI Slot
T2/C/S2 W/O AD
P_TS
DDR3 1866 X 16
Air/ P_TS
A B (512MB X 2EA)
Cable TUNER
R IF (+/-) T/C Demod
E (T2/C/A)
Analog Demod SYSTEM EEPROM
A P_TS I2C 1
DVB-S P_TS (256Kb)
R TUNER DEMOD
(H) (S2) (S2) CVBS
LNB USB1 OCP eMMC
(HDD) 2A (4GB)
USB
USB2 OCP
USB3
(2.0) 1.5A
Vx1 Video 4K@30p/2K@60p(Vx1 4 lane), LGE7411
OSD FHD@60p(Vx1 2 lane)
HDMI3 (MHL) Mstar LM14
Sil9617 I2S Out MAIN A
Audio
di AMP
HDMI2 (ARC) I2C 4 (NTP7514)
Mux
LGE7411
HDCP2.2 HDMI
HDMI1 (HDCP2.2) MUX
R9531AN
IR/KEY IR / KEY
X_TAL Serial SUB
27MHz Flash(4MB) H/P ASSY
AV/COMP CVBS/YPbPr
USB_WIFI WIFI/BT Combo
SCART
CVBS/RGB
(IN/OUT) LOGO LIGHT(Ready)
OPTIC SPDIF OUT
Sub Micom
I2C 0 (RENESAS
LAN ETHERNET
R5F100GEAFB)
X TAL
X_TAL
32.768KHz
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
2. HDMI
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
3. LM14 + URSA9 I2C Block Diagram
+3.3V_NORMAL
+3 3V NORMAL
+3.3V_NORMAL
Mstar 33Ω IC1800
LM14 1.8KΩ LNB
1.8KΩ
I2C_SDA4 I2C_SDA2
_ TU1602
IC1200 100Ω 33Ω
NTP7514(Main AMP) I2C_SCL4 I2C_SCL2 TUNER(Demod)
+3.3V_NORMAL
P2000
LCD Panel 0Ω
+3.3V_NORMAL
1.8KΩ
1.8KΩ I2C_SDA1
33Ω IC102
I2C_SCL1 NVRAM
I2C_SDA_micom
IC1600 33Ω
I2C_SCL_micom 33 OR A
+3.3V_NORMAL
Renesas MICOM
+3.3V_NORMAL
1.8KΩ
1.8KΩ
I2C_SDA5 SWAP 예정
33Ω TU1602
I2C_SCL5 TUNER
IC3202 33Ω I2C_SDA6
R9531AN I2C_SCL6 +3.3V_NORMAL
+3.3V_NORMAL
3.3KΩ
3.3KΩ
I2C_SDA8 I2C_SDA7 IC2500
IC3206 33Ω 33Ω
I2C_SCL8 URSA9
Sil9617 (MHL) I2C_SCL7
※ I2C CH 6,7,8 S/W I2C 임
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
4. LM14 Power Block Diagram
MHL ※ DCDC 효율 80% 적용 DCDC LDO
5 5mA
5.5mA
MICOM
??mA
IR Ass’y
URSA9
3.5V
??mA 3.3V NORMAL 265mA
6A LM14 H/P AMP
IC500 339mA NTP7514
LM14 1.5V
1.5V DDR
IC402 DDR_VTT WIFI Combo
?mA ?mA DDR_VTT
3A DDR3*4EA
IC507 ??mA 200mA NVRAM
1.8V eMMC
IC501 R9531
457mA 1.1V/1.15V Core 4381mA
3A LM14 ??mA
??mA D.Demod_ MHL
IC504 Core 2A
IC1500 500mA Tuner
1.1V/1.13V Core
6A LM14
IC502 1V R9531 500mA
2A R9531
1.5V IC3204
12V IC13402 URSA9 1.5V
URSA9 Core 8A
IC13100
DDR_VTT_
DDR_VTT_URSA
1.5V
URSA
IC13403 DDR_URSA
URSA9 DDR
700mA
LNB LNB option
500mA
CI SLOT
PANEL VCC
HDMI/MHL
912mA R9531
5V NORMAL
6A 1500mA
24V IC503 USB1
2000mA
830mA USB2/3
NTP7514
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
5. Tuner/CI Block Diagram
TDJM-G251D +3.3V_NORMAL
[+3.3V_LNA_TU] 1
[+3.3V_TUNER] 11
+1.1V_Demod_Core+3.3V_NORMAL
[+3.3V_DEMOD_TU] 26
[1,1V_D_Demod_Core] 28
1.8KΩ CI Slot
LNB_TX
[LNB TX] 29
[LNB_TX] 10 [TONECTRL]
LNB_OUT LNB PCM_5V_CTL CI 5V +5V_CI_ON
[LNB_OUT] 31 2 [LNB] VCC
IC1800 Power detect
[I2C_SCL2_TU] 27 I2C_SCL2 7 [SCL]
33Ω A8303SESTR-TB
[I2C_SDA2_TU] 30 I2C_SDA2 8 [SDA]
+5V_CI_ON
W5[SCK2]
LM14
33 Ω
W6 [SDA2] N6[GPIO_PM4] CAM_CD1_N 10K Ω
/CI CD1
/CI_CD1 CI_CD1
[I2C_SCL5_TU] 4 I2C_SCL5 U6[SCK5] OR
33 Ω AH12[PCMCD] /CI_CD2
[I2C_SDA5_TU] 5 I2C_SDA5 T4 [SDA5] GATE CI_CD2
CI_MISTRT
FE_DEMOD1_TS_CLK CI_MIVA_ERR
[FE_DEMOD1_TS_ERROR_TU] 12 AJ15[TS0CLK]
/PCM_CE1 CI_MCLKI
[FE_DEMOD1_1_TS_CLK] 14 FE_DEMOD1_TS_SYNC AH16(TS0SYNC] AK18[PCMCEN] PCM_CE1
[FE_DEMOD1_TS_SYNC] 15 FE_DEMOD1_TS_VAL AH17[TS0VALID]
[FE_DEMOD1_TS_VAL] 16
EB_BE_NO
AJ11[PCMIOWR] CI_IOWR
FE_DEMOD1_TS_DATA[0]
FE DEMOD1 TS DATA[0] 17 EB BE N1
EB_BE_N1
FE_DEMOD1_TS_DATA[1] 18 AJ14[PCMIORD] CI_IORD
FE_DEMOD1_TS_DATA[2] 19 FE_DEMOD1_TS_DATA [0-7]
FE_DEMOD1_TS_DATA[3] 20 AH13~AH15 EB_ADDR[0-14] CI_ADDR[0-14]
FE_DEMOD1_TS_DATA[4] 21 [TS0DATA[0-7] AM23-AM16 CI_ADDR[0-14]
FE_DEMOD1_TS_DATA[5] 22 EB_DATA[0-7] CI_DATA[0-7]
FE_DEMOD1_TS_DATA[6] 23 AL21-AJ12 EB_DATA[0-7]
FE_DEMOD1_TS_DATA[7] 24
AL18[PCM_RST]
PCM_RESET
PCM_RESET
AL19[PCMWAIT] CAM WAIT N
CAM_WAIT_N CAM_WAIT_N
CAM_REG_N
REG
AK20[PCMREG]
CAM_IREQ_N CAM_IREQ_N
AL17[PCMIRQA]
/EB_OE_N
AG10[PCMOEN] CI_OE
RF_SWITCH_CTL /EB_WE_N
E11 [GPIO152] AK16[[PCMWEN] CI_WE
[RF_SWITCH_CTL] 2 /TU_RESET1
B4 [GPIO66] TPI CLK
TPI_CLK CI TS CLK
CI_TS_CLK
[/TU_RESET1_TU] 25 AG19[TS1CLK] TS_OUT_CLK
TPI_VAL CI_TS_VAL
AH20[TS1VALID] TS_OUT_VAL
IF_P ADC_I_INP TPI_SOP CI_TS_SYNC
AL7 [VIFP] AG18[TS1SYNC] TS_OUT_SYNC
[IF_P] 6 IF_N FILTER
ADC_I_INN
AM7 [VIFM] TPI_DATA[0-7] TPI_DATA[0-7]
[IF_N] 7 AJ18~AJ21
TUNER_SIF 33Ω TS_OUT[0-7]
AL6[SIFP] [TPI_DATA[0-7]]
[TU_SIF_TU] 9
TU_CVBS AH13~AH15
FE_DEMOD1_TS_DATA[0-7]
CI_MDI[0-7]
[TU_CVBS_TU] 8 AF4[CVBS0] 33Ω TS_IN[0-7]
IF AGC
IF_AGC [TS0DATA[0 7]
[TS0DATA[0-7]
[IF_AGC_TU] 3 AM5[IF_AGC]
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
6. Video/Audio In Block Diagram
Jack Side SoC Side
JK800
COMP1_Y COMP1_Y
[GIN1P]
COMP1_Pb COMP1_Pb
[RIN1P]
COMP1_Pr COMP1_Pr
[BIN1P]
JK802
AV1 CVBS IN
AV1_CVBS_IN AV1 CVBS IN
AV1_CVBS_IN
[CVBS2]
COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_L_IN
[LINE_IN_0L]
COMP1/AV1/DVI_R_IN COMP1/AV1/DVI_R_IN
[LINE_IN_0R]
LM14
SCART
SC_CVBS_IN SC_CVBS_IN
[CVBS1]
SC_FB/ID SC_FB/ID
[VSYNC0,HSYNC0]
SC R/G/B
SC_R/G/B SC R/G/B
SC_R/G/B
[RIN0P,GIN0P,BIN0P]
SC_L/R_IN SC_L/R_IN
[LINE_IN_2L,LINE_IN_2R]
DTV/MNT_V_OUT DTV/MNT_V_OUT
[CVBSOUT1]
JK2100
Tuner TU_CVBS TU_CVBS
[CVBS0]
TUNER_SIF, IF_P/N TUNER_SIF, IF_P/N
[SIFP,VIFP/VIFM]
Parallel TS / ERROR,VAL,SYNC,CLK Parallel TS / ERROR,VAL,SYNC,CLK
, , ,
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
7. Audio Out Block Diagram
SCART
[LINE_OUT_0L] SCART_L/Rout IC6000 DTV/MNT_L/R_OUT
COMP1/AV1/DVI_L_IN AZ4580MTR LPF
[LINE_OUT_0R]
COMP1/AV1/DVI_R_IN [LINE_IN_0L] OP AMP
[ N _IN
[LINE N_0R]
R]
Mute CTRL
(TR)
JK802 JK2100
DVB only
SCART_MUTE
SCART
AUD_MASTER_CLK
[I2S_OUT_MCK]
SC_L_IN / SC_R_IN [LINE_IN_2L] AUD_LRCH
[I2S_OUT_WS]
[LINE_IN_2R]
AUD_LRCK
[I2S_OUT_SD]
AUD_SCK
4P WAFER
[I2S_OUT_BCK]
IC1200 LPF SPEAKER_L
DVB only Audio AMP
JK2100 [SDA4]
I2C_SDA4
NTP7514 LPF SPEAKER R
SPEAKER_R
I2C SCL4
I2C_SCL4
[SCL4]
[GPIO153] AMP_RESET_N
LM14 AMP_MUTE
Tunerr
TUNER_SIF
TR BUF [SIFP]
IC3000
MICOM
SIDE_HP_MUTE
SPDIF_OUT
HEAD PHONE
[SPDIF_OUT]
[EAR_OUT_L] HP_LOUT / HP_ROUT
[EAR_OUT_R] LPF
JK801
JK803
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
8. USB / WIFI / M-REMOTE / UART
USB_DM1 USB1
[USB_DM] +5V_USB_1
USB_DP1
[USB_DP]
USB2.0
[GPIO11] /USB_OCD1 OCP
[GPIO15]
USB CTL1
USB_CTL1 (HDD)
USB_DM2 USB2
+5V_USB_2
[USB2_DM]
[USB2_DP] USB_DP2
[GPIO169]
/USB_OCD2
[GPIO170] USB_CTL2
USB2.0
USB_DM3 USB3 OCP
[USB0_DM]
+5V_USB_3
[USB0_DP] USB_DP3
/USB_OCD3
[GPIO171]
[GPIO172] USB_CTL3
WIFI_DM USB_WIFI/BT
[USB1_DM]
[USB1_DP] WIFI_DP
SOC_TX
[TX1]
[RX1] SOC_RX
4Pin debugging
wafer
LM14
RENESAS MICOM
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
9. Back End
SPI_CZ Panel
SPI_DO
SPI_CK 3840x2160@60p
XIN_URSA X-tal 24MHz
Serial SPI DI
SPI_DI
XO_URSA
or
Flash(4MB) FLASH_WP_URSA URSA9 3840x2160@120p
LGE7411
LM14 DDR3
16x4
1Gb x 4 (1866)
[TXDBN0/P0~N7/P7_L] Vx1 8Lane 41P
VBY[4,5,6,7]_N,P 4K@30Hz/2K@60p Vx1 4 Lane Video VBY1_RXM/P[4,6,8,10]
VBY[2,3] N,P
VBY[2,3]_N,P FHD@60Hz Vx1 2 Lane OSD VBY1 RXM/P[0 2]
VBY1_RXM/P[0,2]
URSA9_CONNECT
GPIO[??] [GPIO[14]]
Vx1_LOCKn,HTPDn_O/V
[LOCKN_D/Q] [VX1R_LOCK_O]
[TXDAN0/P0~N7/P7_L] Vx1 8Lane 51P
I2C_SCL7/SDA7
ICS SDA/SCL
ICS_SDA/SCL
[I2CS_SDA/SCL] [INT_R21/GPIO[41]] TCON_I2C_EN
L_DIM_EN
[SPI4_CK/DIM8/GPIO52]
LOCKn_IN/ HTPDn_IN
[VX1T_HTPDN]
[VX1T_LOCKN]
URSA_RESET LM14 I2C_SCL4/SDA4
[RESET]
GPIO[4][5]
Data_Format_0,1
GPIO[52] 3D_EN
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
10. LM14 Internal Block
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Only for training and service purposes
