Internal Use Only
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LED TV
SERVICE MANUAL
CHASSIS : LD41V
MODEL : 49UB850V 49UB850V-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL68084505 (1403-REV00) Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 14
BLOCK DIAGRAM................................................................................... 23
EXPLODED VIEW .................................................................................. 25
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method
This specification is applied to the LED TV used LD41V 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Model General Specification
No. Item Specification Remarks
DTV & Analog (Total 37 countries)
DTV (MPEG2/4, DVB-T) : 30 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bul-
garia, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Be-
larus
DTV (MPEG2/4, DVB-T2) : 8 countries
UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kaza-
khstan, Russia
DTV (MPEG2/4, DVB-C) : 37 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bul-
garia, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Bela-
EU(PAL Market-36Countries)/CIS rus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan
1 Market
+ Morocco(Africa)
DTV (MPEG2/4, DVB-S/S2) : 30 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bul-
garia, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Bela-
rus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan
Supported satellite : 29 satellites
ABS1 75.0E/ AMOS 4.0W/ ASIASATS 105.5E/ ASTRA1LHMKR
19.2E/ ASTRA2ABD 28.2E/ ASTRA3AB 23.5E/ ASTRA4A 4.8E/
ATLANTICBIRD2 8.0W/ ATLANTICBIRD3 5.0W/ BADR 26.0E/ EU-
ROBIRD3 33.0E/ EUROBIRD9A 9.0E/ EUTELSATW2A 10.E/ EU-
TELSATW3A 7.0E/ EUTELSATW4W7 36.0E/ EUTELSESAT 16.0E/
EXPRESSAM1 40.0E/ EXPRESAM3 140.0E/ EXPRESSAM33
96.5E/ HELLASAT2 39.0E/ HISPASAT1CDE 30.0W/ HOTBIRD
13.0E/ INTELSAT10&7 68.5E/ INTELSAT15 85.2E/ INTELSAT904
60.0E/ NILESAT 7.0W/ THOR 0.8W/ TURKSAT 42.0E/ YAMAL201
90.0E
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
2 Broadcasting system 1) PAL-BG/DK/I/I’
2) SECAM L/L’, DK, BG, I
3) DVB-T/T2, C, S/S2
1 ) Digital TV
- VHF, UHF
- C-Band, Ku-Band
2) Analogue TV
3 Program coverage
-VHF : E2 to E12
-UHF : E21 to E69
-CATV : S1 to S20
-HYPER : S21 to S47
► DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
4 Receiving system Digital : COFDM, QAM
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
► DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2 Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate :
DVB-S2 (8PSK / QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2 ~ 45 Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
5 Input Voltage AC 100 ~ 240V 50/60Hz
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. External Input Support Format
5.1. Component (Y, CB/PB, CR/PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1. 720×480 15.73 60.00 SDTV, DVD 480i SDTV, DVD 480I(525I)
2. 720×480 15.63 59.94 SDTV, DVD 480i SDTV, DVD 480I(525I)
3. 720×480 31.47 59.94 480p SDTV, DVD 576I(625I) 50Hz
4. 720×480 31.50 60.00 480p SDTV 480P
5. 720×576 15.625 50.00 SDTV 576i SDTV 480P
6. 720×576 31.25 50.00 SDTV 576p SDTV 576P 50Hz
7. 1280×720 45.00 50.00 HDTV 720p HDTV 720P
8. 1280×720 44.96 59.94 HDTV 720p HDTV 720P
9. 1280×720 45.00 60.00 HDTV 720p HDTV 720P 50Hz
10. 1920×1080 31.25 50.00 HDTV 1080i HDTV 1080I 50Hz,
11. 1920×1080 33.75 60.00 HDTV 1080i HDTV 1080I
12. 1920×1080 33.72 59.94 HDTV 1080i HDTV 1080I
13. 1920×1080 56.250 50 HDTV 1080p HDTV 1080P
14. 1920×1080 67.5 60 HDTV 1080p HDTV 1080P
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
5.2. HDMI(PC/DTV)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Remarks
HDMI-PC DDC
1 640*350 31.468 70.09 25.17 EGA Х
2 720*400 31.469 70.08 28.32 DOS O
3 640*480 31.469 59.94 25.17 VESA(VGA) O
4 800*600 37.879 60.31 40.00 VESA(SVGA) O
5 1024*768 48.363 60.00 65.00 VESA(XGA) O
6 1152*864 54.348 60.053 80.00 VESA O
7 1280*1024 63.981 60.020 108.00 VESA (SXGA) O
8 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9 1920*1080 67.5 60 148.5 WUXGA(Reduced Blanking) O
10 3840*2160 67.5 30.00 297.00 UD
11 3840*2160 56.25 25.00 297.00 UD
12 3840*2160 54.0 24.00 297.00 UD
HDMI-DTV
1 720*480 31.47 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.500 60 148.50 HDTV 1080P
8 1920*1080 67.432 59.939 148.352 HDTV 1080P
9 1920*1080 27.000 24.000 74.25 HDTV 1080P
10 1920*1080 26.97 23.976 74.176 HDTV 1080P
11 1920*1080 33.75 30.000 74.25 HDTV 1080P
12 1920*1080 33.71 29.97 74.176 HDTV 1080P
13 3840*2160 67.5 30.00 297.00 UDTV 2160P
14 3840*2160 56.25 25.00 297.00 UDTV 2160P
15 3840*2160 54.0 24.00 297.00 UDTV 2160P
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
6. 3D Mode
6.1. RF Input (3D supported mode manually)
No. Resolution Proposed Remarks
1080I
1 HD - DTV
720P 2D to 3D
576P Side by Side(Half)
2 SD - DTV
576I Top & Bottom
3 SD – ATV(CVBS/SCART)
6.2. RF Input (3D supported mode automatically)
No. Resolution Remarks
2D to 3D
1 Frame Compatible Side by Side(Half)
Top & Bottom
6.2. HDMI Input
(1) HDMI 1.3 (3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode
1 720*480 31.5 60 27.03 SDTV 480P
2 720*576 31.25 50 27 SDTV 576P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential, Row Inter-
45.00 60.00 74.25 HDTV 720P leaving, Column Interleaving
3 1280*720
37.500 50 74.25 HDTV 720P
33.75 60.00 74.25 HDTV 1080I
2D to 3D, Side by Side(Half), Top & Bottom
28.125 50.00 74.25 HDTV 1080I
27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
4 1920*1080 28.12 25 74.25 HDTV 1080P Checker Board, Row Interleaving, Column
33.75 30.00 74.25 HDTV 1080P Interleaving
67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential, Row
56.250 50 148.5 HDTV 1080P Interleaving, Column Interleaving
53.95 23.976 297.00
54 24.00 296.703
2D to 3D,
5 3840*2160 56.25 25.00 297.00 HDTV 2160P
Top & Bottom(half), Side by Side(half),
61.43 29.970 297.00
67.5 30.00 296.703
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
(2) HDMI 1.4b (3D Supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed
Top-and-Bottom Secondary(SDTV 480P)
1 31.469 / 31.5 59.94/ 60 25.125/25.2 1
Side-by-side(half) Secondary(SDTV 480P)
640*480 Frame packing Secondary(SDTV 480P)
2 62.938/63 59.94/ 60 50.35/50.4 1
Line alternative (SDTV 480P)
3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)
Top-and-Bottom Secondary(SDTV 480P)
4 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3
Side-by-side(half) Secondary(SDTV 480P)
720*480 Frame packing Secondary(SDTV 480P)
5 62.938/63 59.94 / 60 54/54.06 2,3
Line alternative (SDTV 480P)
6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)
Top-and-Bottom Secondary(SDTV 576P)
7 31.25 50 27 17,18
Side-by-side(half) Secondary(SDTV 576P)
720*576 Frame packing Secondary(SDTV 576P)
8 62.5 50 54 17,18
Line alternative (SDTV 576P)
9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)
Top-and-Bottom Primary(HDTV 720P)
10 37.500 50 74.25 19
Side-by-side(half) Primary(HDTV 720P)
Frame packing Primary(HDTV 720P)
11 75 50 148.5 19
Line alternative (HDTV 720P)
12 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)
1280*720
Top-and-Bottom Primary(HDTV 720P)
13 44.96 / 45 59.94 / 60 74.18/74.25 4
Side-by-side(half) Primary(HDTV 720P)
14 89.91/90 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)
Frame packing Primary(HDTV 720P)
15 44.96 / 45 59.94 / 60 148.35/148.5 4
Line alternative (HDTV 720P)
Frame packing Primary(HDTV 720P)
16 33.72 / 33.75 59.94 / 60 74.18/74.25 5
Line alternative (HDTV 720P)
Top-and-Bottom Secondary(HDTV 1080I)
17 67.432/67.50 59.94 / 60 148.35/148.5 5
Side-by-side(half) Primary(HDTV 1080I)
18 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)
1920*1080
Top-and-Bottom Secondary(HDTV 1080I)
19 28.125 50.00 74.25 20
Side-by-side(half) Primary(HDTV 1080I)
Frame packing Primary(HDTV 1080I)
20 56.25 50.00 148.5 20
Field alternative (HDTV 1080I)
21 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)
Top-and-Bottom Primary(HDTV 1080P)
22 26.97 / 27 23.97 / 24 74.18/74.25 32
Side-by-side(half) Primary(HDTV 1080P)
Frame packing Primary(HDTV 1080P)
23 43.94/54 23.97 / 24 148.35/148.5 32
Line alternative (HDTV 1080P)
24 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Secondary(HDTV 1080P)
25 28.12 25 74.25 33
Side-by-side(half) Secondary(HDTV 1080P)
Frame packing Primary(HDTV 1080P)
26 56.24 25 148.5 33
Line alternative (HDTV 1080P)
27 1920*1080 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Secondary(HDTV 1080P)
28 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34
Side-by-side(half) Secondary(HDTV 1080P)
Frame packing Primary(HDTV 1080P)
29 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34
Line alternative (HDTV 1080P)
30 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
31 56.250 50 148.5 31
Side-by-side(half) Secondary(HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
32 67.43 / 67.5 59.94 / 60 148.35/148.50 16
Side-by-side(half) Secondary(HDTV 1080P)
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
(3) HDMI-PC Input (3D) (3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1024*768 48.36 60 65 2D to 3D, Side by Side(half), Top & Bottom HDTV 768P
2 1360*768 47.71 60 85.5 2D to 3D, Side by Side(half), Top & Bottom HDTV 768P
2D to 3D, Side by Side(half), Top & Bottom,
3 1920*1080 67.500 60 148.50 Checker Board, Single Frame Sequential, HDTV 1080P
Row Interleaving, Column Interleaving
54 24.00 296.703
2D to 3D, Top & Bottom(half), Side by
4 3840*2160 56.25 25.00 297 HDTV 2160P
Side(half),
67.5 30.00 296.703
640*350
720*400
5 Others - - - 2D to 3D, Side by Side(half), Top & Bottom 640*480
800*600
1152*864
(4) Component Input (3D) (3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1280*720 37.5 50 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 720P
2 1280*720 45.00 60.00 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 720P
3 1280*720 44.96 59.94 74.176 2D to 3D, Side by Side(half), Top & Bottom HDTV 720P
4 1920*1080 33.75 60.00 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080I
5 1920*1080 33.72 59.94 74.176 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080I
6 1920*1080 28.12 50 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080I
7 1920*1080 67.500 60 148.50 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
8 1920*1080 67.432 59.94 148.352 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
9 1920*1080 27.000 24.000 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
10 1920*1080 28.12 25 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
11 1920*1080 56.25 50 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
12 1920*1080 26.97 23.976 74.176 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
13 1920*1080 33.75 30.000 74.25 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
14 1920*1080 33.71 29.97 74.176 2D to 3D, Side by Side(half), Top & Bottom HDTV 1080P
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
(5) USB, DLNA - Movie (3D) (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 704x480 - - - 2D to 3D
Over 704x480
2 - - - 2D to 3D, Side by Side(Half), Top & Bottom
interlaced
2D to 3D, Side by Side(Half), Top & Bottom, Checker
- 50 / 60 - Board, Row Interleaving, Column Interleaving, Frame
Over 704x480 Sequential
3
progressive
2D to 3D, Side by Side(Half), Top & Bottom, Checker
- others -
Board, Row Interleaving, Column Interleaving
(6) USB, DLNA -Photo (3D) (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 320x240 - - - 2D to 3D
2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom
(7) USB, DLNA (3D) (3D supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
Side by Side(Half), Top & Bottom, Checker Board,
1 1080p 33.75 30 74.25
MPO(Photo), JPS(Photo)
(8) Miracast, Widi (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1024*768p - 30/60 -
2 1280*720p - 30/60 - 2D to 3D, Side by Side(Half), Top & Bottom
3 1920*1080p - 30/60 -
4 Others - - - 2D to 3D
■ Remark: 3D Input mode
Single Frame Frame Line Column
No. Side by Side Top & Bottom Checker board 2D to 3D
Sequential Packing Interleaving Interleaving
1
ii. iii. iv. v. vi.
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 3.1.2. Adjustment method
This specification sheet is applied to all of the LED TV with - Using RS-232, adjust items in the other shown in "3.1.3"
LD41V chassis.
3.1.3. Adj. protocol
Protocol Command Set ACK
2. Designation Enter adj. mode aa 00 00
xb 00 04
a 00 OK00x
b 00 OK04x (Adjust 480i, 1080p Comp1 )
(1) Because this is not a hot chassis, it is not necessary to Source change
xb 00 06 b 00 OK06x (Adjust 1920*1080 RGB)
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument. Begin adj. ad 00 10
(2) Adjustment must be done in the correct order. Return adj. OKx (Case of Success)
result NGx (Case of Fail)
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative (main) (main)
ad 00 20 000000000000000000000000007c007b006dx
humidity if there is no specific designation. Read adj. data
(4) The input voltage of the receiver must keep AC 100-240 (sub ) (Sub)
ad 00 21 000000070000000000000000007c00830077x
V~, 50/60 Hz.
NG 03 00x (Fail)
(5) The receiver must be operated for about 5 minutes prior to NG 03 01x (Fail)
the adjustment when module is in the circumstance of over Confirm adj. ad 00 99
NG 03 02x (Fail)
15. OK 03 03x (Success)
End adj. aa 00 90 a 00 OK90x
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2 Ref.) ADC Adj. RS232C Protocol_Ver1.0
hours.
3.1.4. Adj. order
In case of keeping module is in the circumstance of below
- aa 00 00 [Enter ADC adj. mode]
-20 °C, it should be placed in the circumstance of above 15
- xb 00 04 [Change input source to Component1(480i& 1080p)]
°C for 3 hours.
- ad 00 10 [Adjust 480i&1080p Comp1]
- xb 00 06 [Change input source to RGB(1024*768)]
[Caution]
- ad 00 10 [Adjust 1920*1080 RGB]
When still image is displayed for a period of 20 minutes or
- ad 00 90 End adj.
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area. 3.2. M
AC address, ESN, Widevine, HDCP
2.0 key D/L
(1) Equipment & Condition
3. Automatic Adjustment 1) Play file: keydownload.exe
3.1. ADC Adjustment (2) Communication Port connection
ADC adjustment is needed to find the optimum black level 1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)
and gain in Analog-to-Digital device and to compensate RGB 2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)
deviation.
(3) Download process
3.1.1. Equipment & Condition 1) Select the download items.
(1) USB to RS-232C Jig 2) Mode check: Online Only
(2) M SPG-925 Series Pattern Generator(MSPG-925FA, 3) Check the test process: DETECT → MAC → WIDEVINE
pattern - 65) 4) Play: START
- Resolution : 480i Comp1 5) Check of result: Ready, Test, OK or NG
1080P Comp1
- Pattern : Horizontal 100% Color Bar Pattern (4) Communication Port connection
- Pattern level : 0.7 ± 0.1 Vp-p 1) Connect
- Image : PCBA Jig → RS-232C Port == PC → RS-232C Port
Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
(5) Download 3.3.4. LAN PORT inspection (PING TEST)
1) AJ/JA Models (13Y LCD TV + MAC + Widevine + ESN + (1) Play the LAN Port Test Program.
HDCP2.0) (2) Connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.
3.3. LAN Inspection
3.3.1. Equipment & Condition
▪ Each other connection to LAN Port of IP Hub and Jig
3.4. Model name & Serial number Download
3.4.1. Model name & Serial number D/L
- Press "Power on" key of service remote control.
3.3.2. LAN inspection solution (Baud rate : 115200 bps)
- Connect RS232 Signal to USB Cable to USB.
▪ LAN Port connection with PCB
- Write Serial number by use USB port.
▪ Network setting at MENU Mode of TV - Must check the serial number at Instart menu.
▪ Setting automatic IP
▪ Setting state confirmation 3.4.2. Method & notice
- If automatic setting is finished, you confirm IP and MAC (1) Serial number D/L is using of scan equipment.
Address. (2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
3.3.3. LAN PORT INSPECTION(PING TEST)
Connect SET -> LAN port == PC -> LAN Port
SET PC
(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2
Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
4. Manual Adjustment
model name or serial number is initialized.(Not always) 4.1. ADC adjustment
It is impossible to download by bar code scan, so It need (1) Remove Component and SCART Input Signal.
Manual download. (2) P
ress Adj. key on the Adjustment remote control, then select
1) Press the "Instart" key of Adjustment remote control. “9.ADC Calibration”.
2) Go to the menu "5.Model Number D/L" like below photo. (3) change ADC Type to Internal
3) Input the Factory model name or Serial number like photo. (4) Move curser on the Start.
(5) Press OK.
4.2. EDID(The
Extended Display Identification
Data)/DDC(Display Data Channel) download
4.2.1. Overview
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity
of user input. It is a realization of "Plug and Play".
4) Check the model name Instart menu. → Factory name 4.2.2. Equipment
displayed. - Since embedded EDID data is used, EDID download JIG,
5) C heck the Diagnostics.(DTV country only) → Buyer HDMI cable and D-sub cable are not need.
model displayed. - Adjustment remote control
3.5. WIFI MAC ADDRESS CHECK 4.2.3. Download method
(1) Using RS232 Command (1) Press "ADJ" key on the Adjustment remote control, then
select "12.EDID D/L", By pressing "Enter" key, enter EDID
Command Set ACK D/L menu.
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG] For HDMI EDID
DVI-D to HDMI or HDMI to HDMI
(2) Check the menu on in-start.
(2) S elect "Start" button by pressing "Enter" key, HDMI1/
HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG.
Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
4.2.4. EDID DATA EDID Block 1, Bytes 128-255 [80H-FFH]
▪ Reference 0 1 2 3 4 5 6 7 8 9 A B C D E F
- HDMI1 ~ HDMI4 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21
- In the data of EDID, bellows may be different by Input mode. 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
20 09 57 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02
0 1 2 3 4 5 6 7 8 9 A B C D E F
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F4
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 01 ⓔ1 # HDMI3 (C/S: 0xA1, 0x3A)
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ
EDID Block 0, Bytes 0-127 [00H-7FH]
0x02 ⓕ 0 1 2 3 4 5 6 7 8 9 A B C D E F
0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
ⓐ Product ID 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
ⓑ Serial No: Controlled on production line. 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A1
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2013’ → ‘17’ EDID Block 1, Bytes 128-255
ⓓ Model Name(Hex): LGTV 0 1 2 3 4 5 6 7 8 9 A B C D E F
ⓔ Checksum(LG TV): Changeable by total EDID data. 0 02 03 55 F1 58 10 1F 04 13 05 14 03 02 12 20 21
ⓕ Vendor Specific(HDMI) 10 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
20 C0 15 07 50 09 57 07 7C 03 0C 00 30 00 B8 3C 20
30 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10
(1) EDID
40 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 03 01
# HDMI 1(C/S: 0xE7, 0x04) 50 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36
EDID Block 0, Bytes 0-127 [00H-7FH] 60 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E
Block Type : EDID 1.3 70 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 3A
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 # HDMI4 (C/S: 0xE7, 0xD4)
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 EDID Block 0, Bytes 0-127
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0 1 2 3 4 5 6 7 8 9 A B C D E F
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
60 3E 1E 53 1E 00 0A 20 20 20 20 20 20 00 00 00 FC 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
EDID Block 1, Bytes 128-255 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
Block Type : CEA EDID Timing Extension Version 3 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
0 1 2 3 4 5 6 7 8 9 A B C D E F 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7
0 02 03 55 F1 54 10 9F 04 13 05 14 03 02 12 20 21
10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 EDID Block 1, Bytes 128-255
20 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02 0 1 2 3 4 5 6 7 8 9 A B C D E F
30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21
40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 20 09 57 07 7C 03 0C 00 40 00 B8 3C 20 C0 8E 01 02
60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C
50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72
60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00
# HDMI2 (C/S: 0xE7, 0xF4) 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type : EDID 1.3
0 1 2 3 4 5 6 7 8 9 A B C D E F * Checksum(HDMI 1/2/3/4)
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 Input FFh (Checksum)
10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 HDMI1 E7 04
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C HDMI2 E7 F4
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A HDMI3 A1 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC HDMI4 E7 D4
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7
Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
4.3. Camera Function Inspection 4.4.4. Adj. Command (Protocol)
(1) Objective : To check how it connects between Camera and
START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP
PCBA normally, and their Function
(2) Test Method : This Inspection is available only Power-Only - LEN: Number of Data Byte to be sent
Status. - CMD: Command
1) Push Camera Up. - VAL: FOS Data value
2) Camera’s Preview picture apeears on TV Set. - CS: Checksum of sent data
3) Push Camera Down. - A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
▪ RS-232C Command used during auto-adjustment.
RS-232C COMMAND
Explantion
[CMD ID DATA]
wb 00 00 Begin White Balance adjustment
wb 00 10 Gain adjustment(internal white pattern)
wb 00 1f Gain adjustment completed
wb 00 20 Offset adjustment(internal white pattern)
wb 00 2f Offset adjustment completed
(3) RS-232C Command End White Balance adjustment
wb 00 ff
RS-232C COMMAND (internal pattern disappears )
Explanation
CMD DATA ID
Ex) wb 00 00 -> Begin white balance auto-adj.
ai 00 23 Camera Function Start.
wb 00 10 -> Gain adj.
ai 00 24 Camera Function End.
ja 00 ff -> Adj. data
jb 00 c0
...
4.4. White Balance Adjustment ...
4.4.1. Overview wb 00 1f -> Gain adj. completed
▪ W/B adj. Objective & How-it-works *(wb 00 20(Start), wb 00 2f(end)) -> Off-set adj.
(1) Objective: To reduce each Panel's W/B deviation wb 00 ff -> End white balance auto-adj.
(2) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to ▪ Adj. Map
prevent saturation of Full Dynamic range and data, one Command Data Range
of R/G/B is fixed at 192, and the other two is lowered to Adj. item (lower case ASCII) (Hex.) Default
find the desired value. (Decimal)
CMD1 CMD2 MIN MAX
(3) Adjustment condition : normal temperature R Gain j g 00 C0
1) Surrounding Temperature : 25 °C ± 5 °C G Gain j h 00 C0
2) Warm-up time: About 5 Min B Gain j i 00 C0
3) Surrounding Humidity : 20 % ~ 80 % Cool
R Cut
G Cut
4.4.2. Equipment B Cut
(1) Color Analyzer: CA-210 (LED Module : CH 14)
R Gain j a 00 C0
(2) Adjustment Computer(During auto adj., RS-232C protocol
G Gain j b 00 C0
is needed)
B Gain j c 00 C0
(3) Adjustment Remote control Medium
R Cut
(4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 217, Pattern: 78) G Cut
→ Only when internal pattern is not available B Cut
• Color Analyzer Matrix should be calibrated using CS-100. R Gain j d 00 C0
G Gain j e 00 C0
4.4.3. Equipment connection MAP Warm B Gain j f 00 C0
R Cut
Co lo r Analyzer G Cut
Probe RS -232C
Co m p ut er
RS -232C
RS -232C
Pat t ern Generat o r
Signal Source
* If TV internal pattern is used, not needed
Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
4.4.5. Adj. method ▪ Standard color coordinate and temperature using CA-210(CH 14)
(1) Auto adj. method Coordinate
1) Set TV in adj. mode using POWER ON key. Mode Temp ∆uv
x y
2) Zero calibrate probe then place it on the center of the
Display. Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000
3) Connect Cable.(RS-232C to USB) Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000
4) Select mode in adj. Program and begin adj. Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj. 4.4.7. EDGE & IOL LED White balance table
▪ EDGE LED module change color coordinate because of
▪ W/B Adj. must begin as start command “wb 00 00” , and aging time.
finish as end command “wb 00 ff”, and Adj. offset if need. ▪ Apply under the color coordinate table, for compensated
aging time.
(2) Manual adjustment. method ▪ (Normal line) Edge & ALEF LED White balance table
1) Set TV in Adj. mode using POWER ON. - gumi(Mar. ~ Dec.) & Global
2) Zero Calibrate the probe of Color Analyzer, then place it Model : (normal line) LGD, CMI
on the center of LCD module within 10 cm of the surface. Aging Cool Medium Warm
3) Press ADJ key → EZ adjust using adj. R/C → 7. White- time x y x y x y
Balance then press the cursor to the right(key ►). (Min) 271 270 286 289 313 329
(When right key(►) is pressed 216 Gray internal pattern
1 0-2 282 289 297 308 324 348
will be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192, 2 3-5 281 287 296 306 323 346
and the rest will be lowered to meet the desired value. 3 6-9 279 284 294 303 321 343
5) Adjustment is performed in COOL, MEDIUM, WARM 3 4 10-19 277 280 292 299 319 339
modes of color temperature. 5 20-35 275 277 290 296 317 336
6 36-49 274 274 289 293 316 333
** G-fix adjustment 7 50-79 273 272 288 291 315 331
Adjust modes (Cool), Fix the G gain to 172 (default data)
8 80-119 272 271 287 290 314 330
and change the others (G/B Gain).
9 Over 120 271 270 286 289 313 329
Adjust two modes(Medium / Warm), Fix the one of R/G/B
gain to 192 (default data) and decrease the others. - gumi Winter table(Jan., Fab.)- Gumi producing model use only
▪ If internal pattern is not available, use RF input. In EZ Adj. Model : (normal line) LGD, CMI
menu 7.White Balance, you can select one of 2 Test- Aging Cool Medium Warm
pattern: ON, OFF. Default is inner(ON). By selecting OFF, time x y x y x y
you can adjust using RF signal in 216 Gray pattern. (Min) 271 270 286 289 313 329
1 0-5 286 295 301 314 328 354
▪ Adjustment condition and cautionary items
2 6-10 284 290 299 309 326 349
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to 3 11-20 282 287 297 306 324 346
isolate adj. area into dark surrounding. 4 21-30 279 283 294 302 321 342
2) Probe location 5 31-40 276 278 291 297 318 337
: Color Analyzer(CA-210) probe should be within 10 cm 6 41-50 274 275 289 294 316 334
and perpendicular of the module surface (80° ~ 100°) 7 51-80 273 272 288 291 315 331
3) Aging time 8 81-119 272 271 287 290 314 330
- After Aging Start, Keep the Power ON status during 5
9 Over 120 271 270 286 289 313 329
Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern. ▪ (Aging Chamber) Edge & ALEF
Model : (aging chamber)LGD, CMI
4.4.6. Reference(White balance adjusmtment coordinate Aging Cool Medium Warm
and color temperature) time x y x y x y
▪ Luminance : 206 Gray (Min) 271 270 285 293 313 329
▪ Standard color coordinate and temperature using CS-1000 1 0-5 280 285 294 308 319 340
(over 26 inch)
2 6-10 276 280 290 303 315 335
Coordinate
Mode Temp ∆uv 3 11-20 272 275 286 298 311 330
x y 4 21-30 269 272 283 295 308 327
Cool 0.271 0.270 13000 K 0.0000 5 31-40 267 268 281 291 306 323
Medium 0.286 0.289 9300 K 0.0000 6 41-50 266 265 280 288 305 320
Warm 0.313 0.329 6500 K 0.0000 7 51-80 265 263 279 286 304 318
8 81-119 264 261 278 284 303 316
9 Over 120 264 260 278 283 303 315
Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
4.4. Local Dimming Function Check (3) Don't wear a 3D Glasses, Check the picture like below.
Step 1) Turn on TV.
Step 2) At the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
Step 3) Confirm the Local Dimming mode.
Step 4) Press "exit" key.
4.7. Option selection per country
4.8.1. Overview
- Option selection is only done for models in AJ/JA/IL
4.8.2.Method
(1) Press "ADJ" key on the Adjustment remote control, then
select Country Group Menu.
(2) Depending on destination, select Country Group Code or
Country Group then on the lower Country option, select
US, CA, MX. Selection is done using +, - or ►◄ KEY.
4.5. Magic Motion Remote control test 4.8. HDMI ARC Function Inspection
- E quipment : RF Remote control for test, IR-KEY-Code
(1) Test equipment
Remote control for test
- Optic Receiver Speaker
- You must confirm the battery power of RF-Remote control
- MSHG-600 (SW: 1220 ↑)
before test(recommend that change the battery per every lot)
- HDMI Cable (for 1.4 version)
- Sequence (test)
1) If you select the ‘start key(OK)’ on the Adjustment remote
(2) Test method
control, you can pairing with the TV SET.
1) Insert the HDMI Cable to the HDMI ARC port from the
2) You can check the cursor on the TV Screen, when select
master equipment (HDMI1)
the "OK" key on the Adjustment remote control.
3) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the Adjustment remote control.
4.6. 3D function test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.
2) Check the sound from the TV Set
(2) When 3D OSD appear automatically, then select green key.
3) Check the Sound from the Speaker or using AV & Optic
TEST program (It’s connected to MSHG-600)
Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only
Only for training and service purposes
4.9. MHL Test 5. GND and Internal Pressure check
(1) Turn on TV
(2) Select HDMI4 mode using input Menu.
5.1. Method
(1) GND & Internal Pressure auto-check preparation
(3) Set MHL Zig(M1S0D3617) using MHL input, output and
- Check that Power Cord is fully inserted to the SET. (If
power cord.
loose, re-insert)
(4) Connect HDMI cable between MHL Zig and HDMI4 port.
(2) Perform GND & Internal Pressure auto-check
(5) Check LED light of Zig and Module of Set
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX.)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
Result) I f, the LED light is green and the Module shows 5.2. Checkpoint
normal stream → OK, Else → NG ▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
4.10. UHD 4K Test ▪ TEST time: 1 second
(1) Video Inspection(UDG-4004NS)
▪ TEST POINT
1) Insert the HDMI Cable to TV Set.
- GND TEST = POWER CORD GND & SIGNAL CABLE
2) Convert to HDMI Mode using TV/AV key on ADJ remote
METAL GND
control
- Internal Pressure TEST = POWER CORD GND & LIVE &
3) Inspect the sound and picture operation well.
NEUTRAL
(Color condition, Picture noise, Sound distortion etc.)
▪ LEAKAGE CURRENT: At 0.5 mArms
4)Inspection 2D → 3D conversion
(2) Pattern Inspection (MSPG-7100) 6. Audio
1) Insert the HDMI Jack to HDMI 1 Port.
No. Item Min Typ Max Unit
2) Convert to UHD Inspection Pattern. (Use remote control)
Audio practical max 10 12 W EQ Off
3) Check Video and Sound.
1 Output, L/R (Distor- AVL Off
4) Convert to 64 Gray Inspection Pattern. tion=10% max Output) 8.10 10.8 Vrms Clear Voice Off
5) Check Video and Sound.
EQ On
6)Inspect HDMI-CEC function. (Push Play & Pause button) Speaker
2 10 12 W AVL On
(3) I f there are HDMI Port 2,3 and 4, Do each pattern (8 Ω Impedance)
Clear Voice On
Inspection.
(4) 4K Inspection.(HEVC Inspection model only) Measurement condition:
1) Insert USB that 4K video file is saved. (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
2) Check that the video plays normally. (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
(3) RGB PC: 1KHz sine wave signal 0.7 Vrms
4.11. Tool Option selection
- Method : Press "ADJ" key on the Adjustment remote control,
then select Tool option.
4.12. Ship-out mode check (In-stop)
- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only
Only for training and service purposes
7. USB S/W download(Service only)
(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
it didn't work. But your downloaded version is High, USB
data is automatically detecting.(Download Version High &
Power only mode, Set is automatically Download)
(3) Show the message "Copying files from memory".
(4) Updating is starting.
(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn't
have a DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and push "OK" key.
3) Punch in the number. (Each model has their number.)
Copyright © LG Electronics. Inc. All rights reserved. - 22 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
TS
1. External
AUDA/D
CVBS SPDIF
Tuner OPTIC
SIF
BB_TP_DATA
H/P Audio L/R
H/P AMP H/P
LNB CVBS
H13 H13 I2S Audio AMP
Only for training and service purposes
SC_CVBS, RGB, Audio L/R SPK
(4.2ch~7.2ch)
LG1154AN DAC_DATA LG1154D
SCART DTV/MNT_LR/V_OUT
AV1_CVBS AAD_DATA CI
CI
AV1 COMP1/AV1/DVI_ L/R
HSR_P/M RS-232C
Comp1 Y,Pb,Pr
COMP1 DDR3
16x2
LG Electronics. Inc. All rights reserved.
Logo Light HDMI_CEC
Logo Light 792MHz
IR/Joy key
Logo Light 8x4 4Gbϧ 6 (1600)
WOL / WOW
RMII
LAN PHY
USB 2.0 (WIFI11ac & BT)
Motion-R & USB_WI-Fi 8
- 23 -
eMMC
USB 3.0
USB1(USB3.0)
USB2(USB2.0) USB USB 2.0
HUB
USB3(USB2.0)
USB_CAM USB 2.0
HDMI output
BLOCK DIAGRAM
HDMI1~4 HDMI 2.0
Switch
2:1 Mux
OSD HS-LVDS
FHD HS-LVDS
TS output
From H13D
Vx1
D14
URSA9
2:1 Mux
16x4 792MHz
DDR3
16x4 800MHz
DDR3
1Gb x 4 (1866)
1Gb x 4 (1866)
LGE Internal Use Only
Copyright ©
Digital Chip Total Pin : 491w/o Power
2. Internal
Analog Chip Total Pin : 183w/o Power DVB-CI/CI+
AtoDPin : 79
TS(P) TS(P) TS(S) TS(S)
H13A SDRAM H13D
(MCP)
DIF GBB AFE System Video Decoder USB2.0x3
TS (P) GPU Rogue Han
1ch@30MHz Global Baseband Demux Multi-STD
UARTx3
w/ PLL V/Q, DVB-T/C ISDB-T HD Decoder 2D GFX
Tuner GPIOx136
SIF AAD
(Boda950)
BTSC AFE JPG/PNG Decoder
Only for training and service purposes
(THAT) EMAC
Audio DSP
PHY
10b@18.432MHz JPG Encoder
I2S(External) Audio Multi-STD
w/ PLL SCI
Audio Decoder
Mux
Video Encoder
LX4 HiFi EP
SPIx2
1080p@30fps
I2Cx10
Audio L/R(4-ch) 1ch L/R I2S USB3.0 x1
Audio-ADC TrustZone
SW
24b@48KHz Sound DSP eMMC
CPU
SCART out Secure Engine
Audio DAC I2S Clear Voice II DMAC(8ch)
CPU
SW
(48KHz ) ARMCA9 Core 48KB ROM
LG Electronics. Inc. All rights reserved.
Perceptual Timer
Line Out I2S Dual 1.2GHz 64KB SRAM
Audio DAC (48KHz) Volume Control WDT
I2S(HPD) OTP
Slim SPK 32KBI$ 32KBD$ SRAM 16KB
UART
Digital AMP Digital DivX
Audio 1MB L2 $ Timer
SPDIF Bluetooth
Output
5x1ch (1ch)
- 24 -
CVBS(3ch) CVBS
CVBS DAC
Encoder
SW
CVBS-Out CVBS AFE(2-ch) CVD DE BE
12b@54MHz Y/C MCU MCU
CVBS
3ch Video 10x3ch
Mux
Mux
AFE Capture
(120Hz)
Component(2ch) LVDS LVDS
SW
10b@148.5MHz Block Tx Rx
w/ LLPLL (3CH)
PE1
TNR
H3D
SRE
LED
FRC
VCR
OSD
TCON
Vx1/EPI/LVDS Combo
Source Mux
De-interlacer
HDMI
Main/Sub Scaler
Output formatter
Audio PLL DCO
I2Cx1 (1-Link) CPLL
w/ DCO x2
HDMI I2Cx1 GPIOIx16
HDMI-Rx 1.4 SPLL DPLL
(1-port PHY) DDR3 Controller DDR3 Controller
3D, ARC, 4kx2k DDR DDR
PLL PLL
DDR3 PHY DDR3 PHY
16 8
LGE Internal Use Only
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
400
910
570
900
410
503
522
521
500
501
540
504
121
502
530
LV1
120
AT1
820
AG1
Stand screw
A10
A22
200
A2
Copyright © LG Electronics. Inc. All rights reserved. - 25 - LGE Internal Use Only
Only for training and service purposes
System Configuration
EEPROM_ST
IC102-*1
Clock for LG1154D NVRAM +3.3V_NORMAL
M24256-BRMN6TP
E0 VCC
1 8
MAIN Clock(24Mhz) E1
2 7
WC
EEPROM_RENESAS
X-TAL_1
IC102 C103
8pF E2 SCL
GND_1
3 6
XIN_MAIN R1EX24256BSAS0A 0.1uF
Write Protection
C100 VSS
4 5
SDA
- Low : Normal Operation
A0 VCC
R108
2
1
1 8 - High : Write Protection
24MHz
X100
1M
EEPROM_ATMEL
IC102-*2
AT24C256C-SSHL-T
A1 WP
2 7
3
4
A0 VCC
1 8
X-TAL_2
GND_2
8pF
XO_MAIN
A2
3 A0’h 6 SCL
A1
2 7
WP
C101 I2C_SCL5
AR102 A2
3 6
SCL
VSS SDA I2C_SDA5
4 5 33
GND SDA
4 5
System Clock for Analog block(24Mhz)
EB_ADDR[0-14]
EMMC_DATA[0-7]
EB_DATA[0-7]
EPHY_REFCLK
EPHY_CRS_DV
OPT PLL SET[1:0] : internal pull up
EPHY_MDIO
EPHY_TXD1
EPHY_TXD0
EPHY_RXD1
EPHY_RXD0
EPHY_MDC
R100 33 "00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
/USB_OCD3
EPHY_EN
PLLSET1
/USB_OCD2
USB_CTL3
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz) OP MODE[1:0]
USB_CTL2
EMMC_CLK
EMMC_CMD
EMMC_RST
R101 33 "10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz) "00" : Normal Mode +3.3V_NORMAL +3.3V_NORMAL
EB_ADDR[14]
EB_ADDR[13]
EB_ADDR[12]
EB_ADDR[11]
EB_ADDR[10]
EB_ADDR[9]
EB_ADDR[8]
EB_ADDR[7]
EB_ADDR[6]
EB_ADDR[5]
EB_ADDR[4]
EB_ADDR[3]
EB_ADDR[2]
EB_ADDR[1]
EB_ADDR[0]
EB_DATA[7]
EB_DATA[6]
EB_DATA[5]
EB_DATA[4]
EB_DATA[3]
EB_DATA[2]
EB_DATA[1]
EB_DATA[0]
EMMC_DATA[7]
EMMC_DATA[6]
EMMC_DATA[5]
EMMC_DATA[4]
EMMC_DATA[3]
EMMC_DATA[2]
EMMC_DATA[1]
EMMC_DATA[0]
PLLSET0 "11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz) "01/10/11" : Internal Test mode
EB_BE_N1
EB_BE_N0
OPT
EB_WE_N
EB_OE_N
INSTANT boot MODE BOOT MODE
+3.3V_NORMAL "1 : Instant boot
3.3K
3.3K
"0 : EMMC
R117
R150
OPT "0 : normal "1 : TEST MODE
OPT
OPT
R133 33
OPM1 (internal pull down)
R134 33 INSTANT_BOOT BOOT_MODE
+3.3V_NORMAL OPM0
3.3K
OPT
R118
Jtag I/F
For Main
AU11
AR10
AT10
AU10
AT11
AR11
T32
K35
K36
K37
L35
H35
H36
J35
J36
H37
G37
G36
G35
F36
F35
E36
E37
E35
D37
D36
D35
C36
C35
B37
B36
B35
C32
B33
A33
C33
A34
B34
C34
A36
Y37
Y36
W35
T36
W36
V35
V37
V36
U35
U36
U37
AU8
AT8
AR8
0.1uF +3.3V_NORMAL
INSTANT_MODE0 BOOT_MODE0
EB_CS3/GPIO93
EB_CS2/GPIO92
EB_CS1/GPIO91
EB_CS0/GPIO90
EB_WE_N/GPIO95
EB_BE_N1/GPIO81
EB_WAIT/GPIO94
EB_OE_N/GPIO82
EB_BE_N0/GPIO80
EB_ADDR15/GPIO89
EB_ADDR14/GPIO88
EB_ADDR13/GPIO103
EB_ADDR12/GPIO102
EB_ADDR11/GPIO101
EB_ADDR10/GPIO100
EB_ADDR9/GPIO99
EB_ADDR8/GPIO98
EB_ADDR7/GPIO97
EB_ADDR6/GPIO96
EB_ADDR5/GPIO111
EB_ADDR4/GPIO110
EB_ADDR3/GPIO109
EB_ADDR2/GPIO108
EB_ADDR1/GPIO107
EB_ADDR0/GPIO106
EB_DATA7/GPIO105
EB_DATA6/GPIO104
EB_DATA5/GPIO119
EB_DATA4/GPIO118
EB_DATA3/GPIO117
EB_DATA2/GPIO116
EB_DATA1/GPIO115
EB_DATA0/GPIO114
EMMC_CLK
EMMC_CMD
EMMC_RESETN
EMMC_DATA7
EMMC_DATA6
EMMC_DATA5
EMMC_DATA4
EMMC_DATA3
EMMC_DATA2
EMMC_DATA1
EMMC_DATA0
RMII_REF_CLK
RMII_CRS_DV
RMII_MDIO
RMII_MDC
RMII_TXEN
RMII_TXD1
RMII_TXD0
RMII_RXD1
RMII_RXD0
OPT
R175
3.3K
P100 R167
12505WS-10A00 33
T32
HDMI_MUX_SEL
1
TRST_N0
A26 AL34
2 XIN_MAIN XIN GPIO31 CAM_SLIDE_DET
TDI0 R152 560 B26 AM33
XO_MAIN XOUT GPIO30
3
TDO0 AM32
GPIO29 Compensation_Done
4 AF30
TMS0 GPIO28
B27 AN34
5
TCK0 XTAL_BYPASS GPIO27 /RST_PHY
AT37 AK34
6 H13DA_XTAL GPIO26 RF_SWITCH_CTL
SOC_RESET AL33
10K
10K
10K
+3.3V_NORMAL
10K
GPIO25 HDMI_HPD_3
7 AL32
GPIO24 HDMI_HPD_2
OPT
AR9 For ISP
OPT
OPT
OPT
8
GPIO23/UART2_TX For connecting
R163
R160
R166
R168
3.3K
AU16 AM5
R103
9 SOC_RESET PORES_N GPIO22/UART2_RX SIC debug tool
AM6
10 GPIO21 AUD_LRCH2 To surround amp
C108 AD34 AM7 R107 100
11 OPM1 OPM1 GPIO20
0.1uF AD33 AL6
OPM0 OPM0 GPIO19 INSTANT_BOOT
AK7
GPIO18
AT26 AK6
H13A_SCL H13DA_SCL GPIO17 SC_DET local dimming
AU26 AK5
H13A_SDA H13DA_SDA GPIO16 AV1_CVBS_DET I2C port
AJ5
GPIO15 AMP_RESET_N
AP9 AJ6
TRST_N0 TRST_N0 GPIO14 COMP1_DET
AN9 AJ7
WebOS UHD HW Option TMS0
TCK0
AP11
TMS0
TCK0
GPIO13
GPIO12
AH6
M_RFModule_RESET
HP_DET
AN11 AG7
TDI0 TDI0 GPIO11 SIL9617_RESET
+3.3V_NORMAL AN10 AG6
TDO0 TDO0 GPIO10 /TU_RESET1
AM10 AG5
TRST_N1 GPIO9 U14_RESET
AM9 AF5
TMS1 GPIO8 D14_HWRESET
AM11 AH30
TCK1 GPIO7 FRC_FLASH_WP
AM12 AG30
10K
TDI1 GPIO6 /RST_HUB
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
AL11 AN33
BIT6_1
BIT0_1
BIT1_1
BIT7_1
URSA9
TDO1 GPIO5
OLED
FHD
AL9 AK33
U14
D9
PLLSET1 /TU_RESET2
IC100
PLLSET1 GPIO4
R131
AL10 AE30
PLLSET0 MN864778_RESET
R124
R112
R114
R116
R120
R122
R126
R128
R129
PLLSET0 GPIO3
R110
AE34 AD30
BOOT_MODE BOOT_MODE GPIO2
AN32
BIT0 GPIO1
Y33 AK32
D13_INT EXT_INTR3/GPIO70 GPIO0 AMP_RESET_N_1
BIT1 W32 AR101
EPHY_INT 3.3K +3.3V_NORMAL
LG1154D_H13D
EXT_INTR2/GPIO69
W33 AC32
BIT2 R149 CAM_TRIGGER_DET EXT_INTR1/GPIO68 DDCD0_CK
1/16W
W34 AC33
R164
10K H13_CONNECT
EXT_INTR0/GPIO67 DDCD0_DA
BIT3 AB33
33
5%
HPD0
AU12
BIT4 R151 SOC_RX UART0_RXD
AT12 AE37
10K SOC_TX UART0_TXD PHY0_ARC_OUT_0 SPDIF_OUT_ARC
AU13 AC36
BIT5 M_REMOTE_RX UART1_RXD PHY0_RX0N_0 HDMI_RX0-
AT13 AC37
M_REMOTE_TX UART1_TXD PHY0_RX0P_0 HDMI_RX0+
BIT6 AP12 AB36
M_REMOTE_RTS UART1_RTS PHY0_RX1N_0 HDMI_RX1-
M_REMOTE_CTS AR12 AB37
BIT7 UART1_CTS PHY0_RX1P_0 HDMI_RX1+
AA36
PHY0_RX2N_0 HDMI_RX2-
AE35 AA37
U14 SPI
BIT8 SOC_SPI1_CS SPI_CS0/GPIO36 PHY0_RX2P_0 HDMI_RX2+
AE36 AD36
SOC_SPI1_MOSI SPI_DO0/GPIO38 PHY0_RXCN_0 HDMI_CLK-
AF36 AD37
BIT9 SOC_SPI1_MISO SPI_DI0/GPIO39 PHY0_RXCP_0 HDMI_CLK+
AF35
SOC_SPI1_SCLK SPI_SCLK0/GPIO37
BIT10 AG34 R32
D13 SPI
SOC_SPI0_CS0 SPI_CS1 HUB_PORT_OVER0 /USB_OCD1
AF33
SOC_SPI0_MOSI SPI_DO1
AG33 R33
SOC_SPI0_MISO SPI_DI1 HUB_VBUS_CTRL0 USB_CTL1
AG32
10K
SOC_SPI0_SCLK SPI_SCLK1
URSA7/URSA9P
10K
10K
10K
10K
10K
10K
10K
R127 LCD 10K
10K
10K
R125BIT7_0
R111BIT1_0
NON_U14
BIT0_0
AR15
NOT_D9
BIT6_0
OPT
OPT
I2C_SCL1
UHD
SCL0/GPIO66
AP15
I2C_SDA1 SDA0/GPIO65
R132
AR16
R115
R130
R109
R119
R121
R123
R113
I2C_SCL_MICOM_SOC SCL1/GPIO64 Not Used Net (UB85/95/UC89)
AP16
I2C_SDA_MICOM_SOC SDA1/GPIO79
AP17
I2C_SCL2_SOC SCL2/GPIO78 CAM_TRIGGER_DET
AR17
I2C_SDA2_SOC SDA2/GPIO77
AP6 H13_CONNECT
I2C_SCL4 SCL3
AR6 SOC_SPI1_CS
I2C_SDA4 SDA3
CAM_IOIS16_N/GPIO83
AH32
CAM_VCCEN_N/GPIO87
SC_VCC_SEL/GPIO128
SOC_SPI1_MOSI
I2C_SCL5
CAM_IREQ_N/GPIO73
CAM_INPACK/GPIO74
CAM_WAIT_N/GPIO84
SC_DETECT/GPIO133
SCL4
AJ33
CAM_CD1_N/GPIO76
CAM_CD2_N/GPIO75
CAM_VS1_N/GPIO86
CAM_VS2_N/GPIO85
CAM_REG_N/GPIO72
SC_VCCEN/GPIO129
SD_DATA3/GPIO121
SD_DATA2/GPIO120
SD_DATA1/GPIO135
SD_DATA0/GPIO134
SOC_SPI1_MISO
SC_DATA/GPIO132
SD_CD_N/GPIO123
SD_WP_N/GPIO122
USB3_REFPADCLKM
USB3_REFPADCLKP
I2C_SDA5 SDA4
SC_CLK/GPIO130
SC_RST/GPIO131
SD_CLK/GPIO125
SD_CMD/GPIO124
USB2_2_TXRTUNE
USB2_1_TXRTUNE
USB2_0_TXRTUNE
20131016 version AH34 SOC_SPI1_SCLK
I2C_SCL6 SCL5
AH33 CAM_SLIDE_DET
USB3_RESREF
I2C_SDA6 SDA5
USB2_2_DP0
USB2_2_DM0
USB2_1_DP0
USB2_1_DM0
CAM_CE1_N
CAM_CE2_N
CAM_RESET
USB2_0_DP
USB2_0_DM
USB3_RX0P
USB3_RX0M
USB3_TX0P
USB3_TX0M
AUD_LRCH2
BIT(0/1) DVB ATSC JP
USB3_DP0
USB3_DM0
GPIO136
GPIO137
GPIO138
GPIO139
AMP_RESET_N_1
00 TW/COL North.AM. U14_RESET
NC_1
NC_2
NC_3
NC_4
01 CN/HK /RST_HUB
KR JP
AMP_RESET_N_1
10 BR
F33
F34
D32
E32
G32
G33
F32
G34
D33
H32
E33
D34
H33
T33
U33
T32
V32
V33
V34
A25
C25
B25
E25
D25
E24
D24
C24
L37
L36
K34
M37
M36
K33
AU7
AT7
AP7
P37
P36
N36
N37
R36
R37
N34
P33
P32
L32
L33
M31
AJ31
J32
J33
K32
J34
EU M_REMOTE_RX
M_REMOTE_TX
11 AJJA I2C_SDA_MICOM I2C_SDA_MICOM_SOC
AR100 M_REMOTE_RTS
+3.3V_LNA_TU +3.3V_TUNER I2C_SCL_MICOM 33 I2C_SCL_MICOM_SOC
M_REMOTE_CTS
200 1%
High Low +3.3V_NORMAL +3.3V_NORMAL
0 R102
0.1uF
0.1uF
I2C_SDA2 I2C_SDA2_SOC
BIT2 Resolution FHD UHD I2C PULL UP 0 R104
200 1%
I2C_SCL2 I2C_SCL2_SOC
R159 200 1%
R157 200 1%
KR_PIP_NOT
BIT3 Support U14 U14 Non_U14
R162
KR_PIP_NOT
Not Used Net (Only OLED)
C104
C105
R135
1.8K
R136
1.8K
R137
1.8K
R138
1.8K
R141
1.8K
R142
1.8K
R143
1.8K
R144
1.8K
R146
1.8K
R147
1.8K
R148
1.8K
R145
1.8K
CAMERA_DP
CAMERA_DM
HUB_DP
HUB_DM
WIFI_DP
WIFI_DM
BIT4 D9 Model D9 Non_D9 DPC_CTL
/PCM_CE1
/PCM_CE2
CAM_CD1_N
CAM_CD2_N
CAM_IREQ_N
PCM_RESET
PCM_5V_CTL
CAM_WAIT_N
CAM_REG_N
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
BIT5 URSA7/URSA9 URSA9 URSA7/URSA9P
R161
DPC_CTL
SIL9617_INT
R9531_RESET
R9531_FLASH_WP
I2C_SDA1
SMARTCARD_CLK/SD_EMMC_DATA[0]
SMARTCARD_DET/SD_EMMC_DATA[3]
SMARTCARD_RST/SD_EMMC_DATA[2]
BIT(6/7) I2C_SCL1
EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP
SMARTCARD_DATA/SD_EMMC_CLK
SMARTCARD_VCC/SD_EMMC_CMD
I2C_SDA_MICOM_SOC
R135-*1 1.5K
Only SMART CARD
R136-*1 1.5K
00 T/C T/C T/C Default ATSC_PIP ATSC_PIP ISDB_PIP Default I2C_SCL_MICOM_SOC
+3.3V_NORMAL
interface
I2C_SDA2_SOC
KR_PIP
01 T2/C/S2/ATV_EXT T2/C_PIP T2/C_PIP ATV_SOC ATV_SOC ISDB
KR_PIP
R154
USB3_DP
USB3_DM
USB3_RX0P
USB3_RX0M
USB3_TX0P
USB3_TX0M
I2C_SCL2_SOC
R155
R153
10K
10K
CI
10K
CI
T2/C T2/C I2C_SDA4
CI
10 T2/C ATV_EXT ATV_EXT I2C for tuner AC-coupling CAP
I2C_SCL4
Place near by LG1154D
11 T2/C/S2/AT T2/C/S2 I2C_SDA5
I2C_SCL5
High Low I2C_SDA6
I2C_SCL6 I2C for tuner
BIT8 Display OLED LCD
BIT9 Reserved
BIT10 Reserved
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-001-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. H13 D CHIP
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LG1154A LG1154D
LG1154A
IC100
H13A_NON_BRAZIL LG1154D_H13D IC100
IC101
+3.3V_Bypass Cap +0.75V
VREF_M0_0
LG1154D_H13D
A27 Y5
AVDD33
LG1154AN_H13A VREF_M0_1
A24
B5
GND_1
GND_2
GND_185
GND_186
Y8
N21 C5 Y12
+3.3V_NORMAL
AVDD33 (2) +3.3V_NORMAL +3.3V_NORMAL +1.24V_Bypass Cap VREF_M1_0
A4
M0_DDR_VREF1
M0_DDR_VREF2
VDDC11_1
VDDC11_2
N22
+1.1V C26
C27
D5
GND_3
GND_4
GND_5
GND_187
GND_188
GND_189
Y13
Y14
Y15
GND_6 GND_190
AVDD33_XTAL(1) AVDD33_CVBS(2) VREF_M1_1 A2 N23 D26
GND_7 GND_191
Y16
Y17
E11 H14 M1_DDR_VREF1 VDDC11_3 E5
GND_8 GND_192
VDD33_1 +1.2V_VDD Y1 P15 E6 Y18
GND_30 L209 L216 M1_DDR_VREF2 VDDC11_4 E7
GND_9 GND_193
Y19
F5 J4 BLM18PG121SN1D L222 VDDC12_XTAL P16 E8
GND_10 GND_194
Y20
VDD33_2 GND_31 BLM18PG121SN1D BLM18PG121SN1D GND_11 GND_195
Y21
F6 J5 VDD25_XTAL VDDC11_5 E22
GND_12 GND_196
VDD33_3 P26 P17 E23 Y22
GND_32
0.1uF
0.1uF
GND_13 GND_197
Y23
XTAL_VDD VDDC11_6 E26
0.1uF
F11 J6 GND_14 GND_198
C2414.7uF
N26 P18
C2554.7uF
F7 Y24
C2794.7uF
VDD33_4 GND_33 XTAL_VDDP VDDC11_7 F8
GND_15 GND_199
Y25
G5 J8 R15 F22
GND_16 GND_200
Y26
+3.3V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDD33_5 GND_34 VDDC11_8 F23
GND_17 GND_201
Y31
H13 J9 +1.2V_VDD GND_18 GND_202
C2974.7uF
M21 T15
C3514.7uF
F24 Y35
VDD33_6 GND_35 VDD33_1 VDDC11_9 F25
GND_19 GND_203
AA8
J13 J10 VDD33
C218
C259
GND_20 GND_204
Y30 T22
C283
F26 AA12
VDD33_7 GND_36 VDD33_2 VDDC11_10 F27
GND_21 GND_205
AA13
P12 J11 AA30 T23 F31
GND_22 GND_206
AA14
VDD33_8 GND_37 VDD33_3 VDDC11_11 G7
GND_23 GND_207
AA16
C208
C209
C210
C213
C219
P13 J14 AE8 T24 G8
GND_24 GND_208
AA17
VDD33_9 GND_38 VDD33_4 VDDC11_12 G9
GND_25 GND_209
AA18
R5 K4 AF8 U15 G10
GND_26 GND_210
AA19
AVDD33_XTAL VDD33_10 GND_39 GND_27 GND_211
AA20
AVDD33_CVBS R6 K5 VDD33_5 VDDC11_13 G11
GND_28 GND_212
VDD33_11 AK13 U22 G12 AA21
GND_40 VDD33_6 VDDC11_14 G13
GND_29 GND_213
AA22
N16 K6 AK24 U23 G14
GND_30 GND_214
AA23
VDD33_XTAL GND_41 VDD33_7 VDDC11_15 G15
GND_31 GND_215
AA24
T13 K8 GND_32 GND_216
AVDD33_CVBS_1 GND_42 Place at the bottom side AK25 U24 G16
GND_33 GND_217
AA25
AA26
T14 K9 VDD33_8 VDDC11_16 G17
GND_34 GND_218
AVDD25 V15 G18 AA31
AVDD33_CVBS_2 GND_43 VDDC11_17 G19
GND_35 GND_219
AB6
K10 M22 V22 G20
GND_36 GND_220
AB8
GND_44 AVDD33_USB_1 VDDC11_18 G21
GND_37 GND_221
AB12
N10
N11
VDD25_CVBS_1 GND_45
K11
K13
+2.5V_Bypass Cap M23
AVDD33_USB_2 VDDC11_19
V23 G22
G23
GND_38
GND_39
GND_40
GND_222
GND_223
GND_224
AB13
AB16
VDD25_CVBS_2 +1.2V_VDD AK11 V24 G24 AB17
GND_46 AVDD33_BT_USB_1 VDDC11_20 G25
GND_41 GND_225
AB18
VDD25_REF N12 K14 AFE 3CH Power AK12 W22 G26
GND_42 GND_226
AB19
VDD25_VSB_1 GND_47 VDDC12_XTAL GND_43 GND_227
AB20
N13 L1 AVDD33_BT_USB_2 VDDC11_21 G27
GND_44 GND_228
VDD25_VSB_2 AF25 W23 G28 AB21
GND_48 L227 AVDD33_HDMI_1 VDDC11_22 G29
GND_45 GND_229
AB22
U5 L2 +2.5V_Normal AVDD25 VDD25_REF AF26 W24 G30
GND_46 GND_230
AB23
VDD25_REF GND_49 BLM18PG121SN1D GND_47 GND_231
AB25
AVDD33_HDMI_2 VDDC11_23 G31
0.1uF
N7 L3 AB15 H9
GND_48 GND_232
AB26
VDD25_COMP_1 GND_50 L225
0.1uF
GND_49 GND_233
C298 4.7uF
H26 AB30
N8 L4 L220 VDDC11_24 GND_50 GND_234
VDD25_LTX VDD25_COMP_2 GND_51 BLM18PG121SN1D
BLM15BD121SN1 +2.5V VDDC11_25
AB24 H27
H28
GND_51 GND_235
AB31
AC8
N9 L5 R31 AC15 H29
GND_52 GND_236
AC12
0.1uF
VDD25_AUD VDD25_COMP_3 GND_52 GND_53 GND_237
0.1uF
AC13
F14 L6 VDD25_LVDS SP_VQPS VDDC11_26 H30
GND_54 GND_238
AC24 H31 AC16
C2424.7uF
C2704.7uF
C300
C2114.7uF
VDD25_APLL GND_53 VDDC11_27 J7
GND_55 GND_239
AC17
M6 L8
C301
GND_56 GND_240
AE23 AD15 J30 AC18
VDD25_AUD_1 GND_54 VDD25_LVRX_1 VDDC11_28 J31
GND_57 GND_241
AC19
N6 L9 AF23 AD16 K7
GND_58 GND_242
AC20
VDD25_LTX
C288
VDD25_AUD_2 GND_55 VDD25_LVRX_2 VDDC11_29 K30
GND_59 GND_243
AC21
M13 L10 GND_60 GND_244
C274
L226 AE14 AD17 K31 AC22
VDD25_AAD GND_56 VTXPHY_VDD25_1 VDDC11_30 L30
GND_61 GND_245
AC23
F15 L11 BLM15BD121SN1 VDD25_XTAL AF14 AD18 L31
GND_62 GND_246
AC25
LTX_LVDD_1 GND_57 VTXPHY_VDD25_2 VDDC11_31 M7
GND_63 GND_247
AC30
F16 L13 N25 AD21 M12
GND_64 GND_248
AC31
LTX_LVDD_2 GND_58 VDD25_DR3PLL VDDC11_32 M13
GND_65 GND_249
AD8
H15 L14 VSS25_REF AD26 AD22 M14
GND_66 GND_250
AD12
SDRAM_VDDQ_1 GND_59 GPLL_AVDD25 VDDC11_33 M15
GND_67 GND_251
AD13
J15 L15 AD23 M16
GND_68 GND_252
AD19
SDRAM_VDDQ_2 GND_60 1005 size bead VDDC11_34 M17
GND_69 GND_253
AD20
J16 L16 H10 AD24 M18
GND_70 GND_254
AD25
SDRAM_VDDQ_3 GND_61 Bottom side of chip +1.2V_VDD GND_71 GND_255
AD31
K15 L17 VDD15_M0_1 VDDC11_35 M19
GND_72 GND_256
VDD12_VTXPHY H11 M20 AE12
SDRAM_VDDQ_4 GND_62 VDD15_M0_2 M24
GND_73 GND_257
AE13
K16 L18 +1.5V H12 M25
GND_74 GND_258
AE15
VDD10_XTAL SDRAM_VDDQ_5 GND_63 L201 VDD15_M0_3 M26
GND_75 GND_259
AE16
M1 H13 M30
GND_76 GND_260
AE17
GND_64 BLM18PG121SN1D VDD12_VTXPHY GND_77 GND_261
AE18
R18 M2 VDD15_M0_4 M32
GND_78 GND_262
H14 M33 AE19
VDD10_XTAL
0.1uF
0.1uF
GND_65 GND_79 GND_263
C205 4.7uF
AE20
G7 M3 VDD15_M0_5 M34
GND_80 GND_264
H15
OPT
VDDC10_1 +2.5V_Normal +2.5V_Normal VDDC15_M0 AB14 N12 AE21
GND_66 VDD25_LTX VDD25_AUD VDD15_M0_6 VTXPHY_VDD11_1 N13
GND_81 GND_265
AE22
G8 M4 H16 AC14 N14
GND_82 GND_266
AE24
VDDC10_2 GND_67 VDD15_M0_7 VTXPHY_VDD11_2 N15
GND_83 GND_267
AE25
VDDC10 G9 M5 H17 AD14 N16
GND_84 GND_268
AE26
VDDC10_3 GND_68 L207 L200 VDDC12_XTAL GND_85 GND_269
AE31
H7 M9 VDD15_M0_8 VTXPHY_VDD11_3 N17
C207
C206
BLM18PG121SN1D BLM18PG121SN1D H18 N18
GND_86 GND_270
AF12
VDDC10_4 GND_69 VDD15_M0_9 N19
GND_87 GND_271
AF13
H12 M10 GND_88 GND_272
0.1uF
0.1uF
H19 P25 N20 AF15
VDDC10_5 GND_70 GND_89 GND_273
C2164.7uF
4.7uF
AF16
VDD15_M0_10 AVDD11_DR3PLL N24
C2754.7uF
C200 4.7uF
J7 M11 H20 AA15 N30
GND_90 GND_274
AF17
VDDC10_6 GND_71 VDD15_M0_11 AVDD11_DCO N31
GND_91 GND_275
AF18
J12 M14 H21 AC26 +1.2V_VDD N32
GND_92 GND_276
AF19
VDDC10_7 GND_72 VDD15_M0_12 GPLL_VDD11 N33
GND_93 GND_277
AF20
K7 M15 H22 P7
GND_94 GND_278
AF21
VDDC10_8 GND_73 GND_95 GND_279
C223
C202
C204
P12 AF22
K12 M16 VDD15_M0_13 GND_96 GND_280
H23 P13 AF24
VDDC10_9 GND_74 VDD15_M0_14 P14
GND_97 GND_281
AF31
L7 N4 H24 P19
GND_98 GND_282
AG8
VDDC10_10 GND_75 VDD15_M0_15 P20
GND_99 GND_283
AG31
L12 N5 H25 P21
GND_100 GND_284
AH8
VDDC10_11 GND_76 VDD15_M0_16 P22
GND_101 GND_285
AH31
VDD10_XTAL M7 N14 P23
GND_102 GND_286
AJ8
VDDC10_12 GND_77 P24
GND_103 GND_287
AJ30
M12 N15 H7 P30
GND_104 GND_288
AK8
VDDC10_13 GND_78 VDD15_M1_1 P31
GND_105 GND_289
AK9
T17 N17 H8 R12
GND_106 GND_290
AK10
AVDD10_CVBS GND_79 VDD15_M1_2 R13
GND_107 GND_291
AK14
T18 P4 J8 R14
GND_108 GND_292
AK15
AVDD10_VSB GND_80 VDD15_M1_3 R16
GND_109 GND_293
AK16
M8 P5 K8 R17
GND_110 GND_294
AK17
AVDD10_LLPLL GND_81 VDD15_M1_4 R18
GND_111 GND_295
AK18
G10 P6 L7 R19
GND_112 GND_296
AK19
DVDD10_APLL_1 GND_82 VDD15_M1_5 R20
GND_113 GND_297
AK20
G11 P7 L8 R21
GND_114 GND_298
AK21
DVDD10_APLL_2 GND_83 VDD15_M1_6 R22
GND_115 GND_299
AK22
G12 P8
LTX_VDD GND_84
P9
+3.3V_Bypass Cap VDDC15_M1 M8
N7
VDD15_M1_7
R23
R24
R25
GND_116
GND_117
GND_118
GND_300
GND_301
GND_302
AK23
AK26
AK27
GND_85 VDD15_M1_8 R26
GND_119 GND_303
AK28
P10 +3.3V_NORMAL N8 R30
GND_120 GND_304
AK29
GND_86 VDD15_M1_9 R34
GND_121 GND_305
AK30
V5 P11 VDD33 P8 T7
GND_122 GND_306
AK31
VSS25_REF VSS25_REF GND_87 VDD15_M1_10 T12
GND_123 GND_307
AL8
C3 P14 R7 T13
GND_124 GND_308
AL12
GND_1 GND_88 L203 VDD15_M1_11 T14
GND_125 GND_309
AL13
D3 P15 R8 T16
GND_126 GND_310
AL14
GND_2 GND_89 BLM18PG121SN1D T17
GND_127 GND_311
AL15
D4 P16 VDD15_M1_12 GND_128 GND_312
T8 T18 AL16
GND_3
0.1uF
0.1uF
0.1uF
GND_90 VDD15_M1_13 T19
GND_129 GND_313
AL17
D17 R4 U8
GND_130 GND_314
C2014.7uF
T20 AL18
GND_4 GND_91 VDD15_M1_14 T21
GND_131 GND_315
AL19
E4 R7 V8 T25
GND_132 GND_316
AL20
GND_5 GND_92
F4
GND_6 GND_93
R8 +1.0V_Bypass Cap W8
VDD15_M1_15
VDD15_M1_16
T26
T30
T31
GND_133
GND_134
GND_135
GND_317
GND_318
GND_319
AL21
AL22
AL23
F7 R9
C203
C212
C215
GND_136 GND_320
T34 AL24
GND_7 GND_94 +1.0V_VDD VDD10_XTAL U7
GND_137 GND_321
AL25
F8 R10 U12
GND_138 GND_322
AL26
GND_8 GND_95 U13
GND_139 GND_323
AL27
F9 R11 U14
GND_140 GND_324
AL28
GND_9 GND_96 U16
GND_141 GND_325
AL29
F10 R12 L211 U17
GND_142 GND_326
AL30
GND_10 GND_97 BLM18PG121SN1D U18
GND_143 GND_327
AL31
F12 R13 U19
GND_144 GND_328
AM8
GND_11 GND_98 Place at the bottom side U20
GND_145 GND_329
AM13
0.1uF
F13 R14 U21
GND_146 GND_330
AM14
GND_12 GND_99 GND_147 GND_331
C2394.7uF
U25 AM15
F17 R15 U26
GND_148 GND_332
AM16
GND_13 GND_100 H13A_BRAZIL
U30
GND_149 GND_333
AM17
F18 R16 U31
GND_150 GND_334
AM18
GND_14 GND_101 IC101-*1 V7
GND_151 GND_335
AM19
G4 R17 LG1154AN_H13A_ISDB-T (LG1154AN-IT) V12
GND_152 GND_336
AM20
C246
GND_15 GND_102 V13
GND_153 GND_337
AM21
G6 T4 V14
GND_154 GND_338
AM22
GND_16 GND_103 P17 H18 V16
GND_155 GND_339
AM23
G13 T7 P18
XIN_SUB AAD_ADC_SIF
H17 V17
GND_156 GND_340
AM24
GND_17 GND_104 J17
XO_SUB AAD_ADC_SIFM
V18
GND_157 GND_341
AM25
G14 T8 VSB_AUX_XIN
P2 V19
GND_158 GND_342
AM26
GND_18 GND_105 N18
AUDA_VBG_EXT
N1 V20
GND_159 GND_343
AM27
G15 T9 D18
XTAL_BYPASS AUDA_OUTL
N2 V21
GND_160 GND_344
AM28
GND_19 GND_106 M18
CLK_24M AUDA_OUTR
N3 V25
GND_161 GND_345
AM29
G16 T10 M17
XTAL_SEL0 AUD_SCART_OUTL
P1 V26
GND_162 GND_346
AM30
GND_20 GND_107 XTAL_SEL1 AUD_SCART_OUTR
V30
GND_163 GND_347
AM31
G17 T11 P3 V31
GND_164 GND_348
AN6
GND_21 GND_108 +1.0V_VDD AUAD_L_CH4_IN
R1 W5
GND_165 GND_349
AN12
G18
H4
GND_22 GND_109
T12
T15
VDDC10 +2.5V_Bypass Cap E3
K3
PORES_N
AUAD_R_CH4_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN
R2
T1
U2
W6
W7
W12
GND_166
GND_167
GND_168
GND_350
GND_351
GND_352
AN13
AN15
AN16
GND_23 GND_110 +2.5V_Normal K2
OPM0 AUAD_L_CH2_IN
U3 W13
GND_169 GND_353
AN17
H5 T16 L206 +2.5V_Normal OPM1 AUAD_R_CH2_IN GND_170 GND_354
GND_24 GND_111 BLM18PG121SN1D VDD25_XTAL (1) VDD25_LVDS(4) A8
AUAD_L_CH1_IN
V2
V3
W14
W15
GND_171 GND_355
AN18
AN19
H6 U4 B8
H13A_SCL AUAD_R_CH1_IN
U1 W16
GND_172 GND_356
AN20
GND_25 GND_112 H13A_SDA AUAD_R_REF
T3 W17
GND_173 GND_357
AN21
0.1uF
H8 U6 L234 L238 AUAD_M_REF
T2 W18
GND_174 GND_358
AN22
C2144.7uF
GND_26 GND_113 BLM18PG121SN1D BLM18PG121SN1D AUAD_L_REF
R3 W19
GND_175 GND_359
AN23
H9 U18 U13
AUAD_REF_PO
W20
GND_176 GND_360
AN24
GND_27 GND_114 V14
CVBS_IN3
K17 W21
GND_177 GND_361
AN25
0.1uF
0.1uF
0.1uF
H10 V4 V15
CVBS_IN2 ANTCON
K18 W25
GND_178 GND_362
AN26
C3644.7uF
C3784.7uF
GND_28 GND_115 V13
CVBS_IN1 RFAGC
J18 W26
GND_179 GND_363
AN27
H11 V16 CVBS_VCM IFAGC GND_180 GND_364
C251
W30 AN28
GND_29 GND_116 U15 U16 W31
GND_181
GND_182
GND_365
GND_366
AN29
BUF_OUT1 ADC_I_INCOM
U14 U17 Y3 AN30
BUF_OUT2 ADC_I_INP GND_183 GND_367
V17 Y4 AN31
ADC_I_INN GND_184 GND_368
C368
C381
C217
F3
GPIO0
U7 F2
REFT GPIO1
V6 F1
REFB GPIO2
V7 G3
ADC1_COM GPIO3
U10 G2
ADC2_COM GPIO4
V12 G1
ADC3_COM GPIO5
T5 H3
SC1_SID GPIO6
T6 H2
SC1_FB GPIO7
U8 H1
Place at the bottom side V8
PB1_IN
Y1_IN
GPIO8
GPIO9
J3
V9 E18
SOY1_IN GPIO10
U9 E17
PR1_IN GPIO11
V10 H16
PB2_IN GPIO12
U11 J2
Y2_IN GPIO13
V11 J1
SOY2_IN GPIO14
U12 K1
PR2_IN GPIO15
+1.5V_DDR VDDC15_M0 +1.5V_Bypass Cap VDDC15_M0 VDDC15_M0
+1.5V_DDR VDDC15_M1
VDDC15_M1 VDDC15_M1
GND JIG POINT SMD TOP for EMI
VREF_M0_1 VREF_M1_0 VREF_M1_1
VREF_M0_0
R300
R302
1K 1%
1K 1%
R200
R202
1K 1%
1K 1%
L230 L228
JP203
JP204
JP202
JP205
BLM18PG121SN1D OPT OPT
BLM18PG121SN1D OPT OPT
0.1uF
C303 22uF
C299 22uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
SMD_GASKET_8.5T
0.1uF
0.1uF
1%
1%
OPT
OPT
OPT
OPT
OPT
OPT
SMD_GASKET_12.5T
1%
1%
GASKET_8.0X6.0X8.5H
R301
R303
GASKET_8.0X6.0X12.5H
R203
R201
M200 M200-*1
C307
C310
C304
1K
1K
C302
C306
C308
C305
C309
C311
C312
C313
C314
C350
C352
C354
C356
C357
C358
C359
C361
C362
C365
C366
C367
C369
C370
C371
C372
C353
C355
C360
C363
MDS62110209
C296
C344
1K
1K
MDS62110217
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-003-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN POWER
11/05/31
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC101 IC100
LG1154AN_H13A H13A_NON_BRAZIL LG1154D_H13D
OP MODE Setting INTR_GBB
E1 AT16
INTR_GBB STPI0_CLK/GPIO47
AK35
FE_DEMOD2_TS_CLK
+3.3V_NORMAL CLK_54M_VTT
Clock for H13A & Select XTAL Input +3.3V_NORMAL INTR_AFE3CH
E2 AU17
INTR_AFE3CH STPI0_SOP/GPIO46
AK36
FE_DEMOD2_TS_SYNC
D1 AT17 AK37
INTR_AGPIO INTR_AGPIO STPI0_VAL/GPIO45 FE_DEMOD2_TS_VAL
AJ35
10K
10K
10K
10K
STPI0_ERR/GPIO44 FE_DEMOD2_TS_ERROR
1/16W
A6 AT24 AJ36
R464
AUD_FS20CLK AUD_FS20CLK STPI0_DATA/GPIO43 FE_DEMOD2_TS_DATA
B6 AU24 AH35
1K
1%
MAIN Clock(24Mhz)
X-TAL_1
OPT
AUD_FS21CLK AUD_FS21CLK STPI1_CLK/GPIO42 D13_STPO_CLK
A5 AT23 AH37
GND_1
R482 OPT
R481 OPT
R484 OPT
12pF AUD_FS23CLK AUD_FS23CLK STPI1_SOP/GPIO41 D13_STPO_SOP
C404 XIN_SUB B5 AU23 AH36
1/16W
D13_STPO_VAL
R465
0.01uF C426 AUD_FS24CLK AUD_FS24CLK STPI1_VAL/GPIO40
390
OP MODE[0:1] : SW[2:1] A4 AT22 AG35
R483
50V
1%
2
00 => Normal Operaiton Mode AUD_FS25CLK AUD_FS25CLK STPI1_ERR/GPIO55 D13_STPO_ERR
1
C4 AG36
24MHz
R441
D13_STPO_DATA
X400
/T32 Debug Mode AUDCLK_OUT_SUB STPI1_DATA/GPIO54
1M
01 => Internal Test Purpose
10 => Internal Test Purpose 100 C18 AU36 AM36
R459 FE_DEMOD1_TS_CLK
3
4
DAC_START_PULLDOWN 11 => Internal Test Purpose OPM[0] AUD_HDMI_MCLK AUD_HDMI_MCLK TP_DVB_CLK
100 AL36
X-TAL_2
GND_2
R460 TP_DVB_SOP FE_DEMOD1_TS_SYNC
12pF OPM[1] A2 AT20 AL35
XTAL SEL[1:0] : SW[4:3]
1/16W
XOUT_SUB 100 AUD_DAC1_LRCK AUD_DAC1_LRCK TP_DVB_VAL FE_DEMOD1_TS_VAL
R466
00 => Xtal Input R461 XTAL_SEL[0] B2 AU20 AL37
C427 AUD_DAC1_SCK AUD_DAC1_SCK TP_DVB_ERR FE_DEMOD1_TS_ERROR
82
1%
01 => CLK 24M from H13D 100 B1 AT19 AM35
R462 XTAL_SEL[1] FE_DEMOD1_TS_DATA[0] FE_DEMOD1_TS_DATA[1-7]
10 => XTAL Bypass from H13D AUD_DAC1_LRCH AUD_DAC1_LRCH TP_DVB_DATA0
C2 AU19 AN36 FE_DEMOD1_TS_DATA[1]
AUD_DAC0_LRCK AUD_DAC0_LRCK TP_DVB_DATA1
FOR EMI C1 AT18 AN37 FE_DEMOD1_TS_DATA[2]
AUD_DAC0_SCK AUD_DAC0_SCK TP_DVB_DATA2
D2 AU18 AN35 FE_DEMOD1_TS_DATA[3]
AUD_DAC0_LRCH AUD_DAC0_LRCH TP_DVB_DATA3
B4 AU22 AP37 FE_DEMOD1_TS_DATA[4]
AUD_ADC_LRCK AUD_ADC_LRCK TP_DVB_DATA4
A3 AT21 AP36
Place JACK Side Place SOC Side IC101 H13A_NON_BRAZIL AUD_ADC_SCK
B3 AU21
AUD_ADC_SCK TP_DVB_DATA5
AR37
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
L408 1uH
LG1154AN_H13A AUD_ADC_LRCH AUD_ADC_LRCH TP_DVB_DATA6
AR36
R434 FE_DEMOD1_TS_DATA[7]
100 C424 0.047uF TP_DVB_DATA7
AV1_CVBS_IN AV1_CVBS_IN_SOC A7 AT25
5.5V C405 BB_SCL BB_SCL
C410 R410 B7 AU25 A28
D404 150pF 150pF 75 BB_SDA BB_SDA TPI_CLK TPI_CLK
P17 H18 C450 0.1uF E8 AP23 B29
50V 1% XIN_SUB XIN_SUB AAD_ADC_SIF TU_SIF BB_TP_CLK BB_TPI_CLK TPI_SOP TPI_SOP TP402 TPI_ERR
3216
XOUT_SUB R453 330P18 H17 C451 0.1uF
C457
D8 AR23 B28
TPI_VAL
XO_SUB AAD_ADC_SIFM BB_TP_ERR BB_TPI_ERR TPI_VAL
L409 1uH R433 J17 C452 10uF 1000pF C8 AP22 C28
100 C425 0.047uF
SC_CVBS_IN_SOC VSB_AUX_XIN BB_TP_SOP BB_TPI_SOP TPI_ERR TPI_ERR
TPI_DATA[0] TPI_DATA[0-7]
SC_CVBS_IN P2 C453 2.2uF OPT E7 AR22 B32
C408 AUDA_VBG_EXT BB_TP_VAL BB_TPI_VAL TPI_DATA0 TPI_DATA[1]
EU C462 N18 N1 D7 AP21 C31
150pF 150pF R411 XTAL_BYPASS AUDA_OUTL AUDA_OUTL BB_TP_DATA7 BB_TPI_DATA7 TPI_DATA1
D18 N2 C7 AR21 B31 TPI_DATA[2]
50V EU 75 SC_CVBS_IN_SOY AUDA_OUTR
1% CLK_24M AUDA_OUTR BB_TP_DATA6 BB_TPI_DATA6 TPI_DATA2 TPI_DATA[3]
EU M18 N3 E6 AP20 A31
3216 XTAL_SEL[0] XTAL_SEL0 AUD_SCART_OUTL SCART_Lout_SOC BB_TP_DATA5 BB_TPI_DATA5 TPI_DATA3
R432 M17 P1 EU 100 R479 D6 AR20 C30 TPI_DATA[4]
100 C423 0.047uF XTAL_SEL[1] XTAL_SEL1 AUD_SCART_OUTR SCART_Rout_SOC BB_TP_DATA4 BB_TPI_DATA4 TPI_DATA4
TU_CVBS TU_CVBS_SOC EU 100 R480 C6 AP19 A30 TPI_DATA[5]
0.01uF
0.01uF
C402 BB_TP_DATA3 BB_TPI_DATA3 TPI_DATA5
P3 E5 AR19 B30 TPI_DATA[6]
150pF
AUAD_L_CH4_IN BB_TP_DATA2 BB_TPI_DATA2 TPI_DATA6
EU R426
EU R442
50V R1 D5 AP18 C29 TPI_DATA[7]
22K
22K
OPT AUAD_R_CH4_IN BB_TP_DATA1 BB_TPI_DATA1 TPI_DATA7
E3 R2 C5 CLK_54M_VTT AR18
SOC_RESET PORES_N AUAD_L_CH3_IN AUAD_L_CH3_IN BB_TP_DATA0 BB_TPI_DATA0
T1 R467 82 D30 TPO_CLK
C458
TPO_ERR
C460
EU
EU
SCART_FB_DIRECT AUAD_R_CH3_IN AUAD_R_CH3_IN TPIO_CLK/GPIO53 TP400
C415 K3 U2 B10 1/16W 1% AU28 D31 TPO_SOP
R423 100 OPM[0] OPM0 AUAD_L_CH2_IN AUAD_L_CH2_IN CLK_F54M CLK_54M TPIO_SOP/GPIO52
SC_FB SC_FB_SOC 0.1uF K2 U3 C9 AR24 F30 TPO_VAL
OPM[1] OPM1 AUAD_R_CH2_IN AUAD_R_CH2_IN CVBS_GC2 CVBS_GC2 TPIO_VAL/GPIO51
10K EU V2 B9 AU27 E31 TPO_ERR
R435 AUAD_L_CH1_IN CVBS_GC1 CVBS_GC1 TPIO_ERR/GPIO50 TPO_DATA[0-7]
SC_ID SC_ID_SOC A8 V3 A9 AT27 E30 TPO_DATA[0]
H13A_SCL H13A_SCL AUAD_R_CH1_IN CVBS_GC0 CVBS_GC0 TPIO_DATA0/GPIO58
B8 U1 D9 AP24 F29 TPO_DATA[1]
SCART_FB_DIRECT
EU H13A_SDA H13A_SDA AUAD_R_REF AUAD_R_REF CVBS_UP CVBS_UP TPIO_DATA1/GPIO59
R422 NON_EU T3 E9 AR25 E29 TPO_DATA[2]
NON_EU R436 R436-*1 AUAD_M_REF AUAD_M_REF CVBS_DN CVBS_DN TPIO_DATA2/GPIO60
R422-*1 75 2.7K T2 F28 TPO_DATA[3]
0 0 AUAD_L_REF AUAD_L_REF Close to LG1154A TPIO_DATA3/GPIO61
R3 Close to IC4300 B11 R492 330 AU29 E28 TPO_DATA[4]
AUAD_REF_PO AUAD_REF_PO FS00CLK FS00CLK TPIO_DATA4/GPIO62
U13 A11 R407 330 AT29 D28 TPO_DATA[5]
AV1_CVBS_IN_SOC CVBS_IN3 AUDCLK_OUT H13A_AUDCLK_OUT TPIO_DATA5/GPIO63
V14 K17 DAC_START_PULLDOWN E27 TPO_DATA[6]
SC_CVBS_IN_SOC CVBS_IN2 ANTCON NON_TU_W_BR/TW/CO TPIO_DATA6/GPIO48
V15 K18 D11 AP27 D27 TPO_DATA[7]
TU_CVBS_SOC CVBS_IN1 RFAGC R487 DAC_START DAC_START TPIO_DATA7/GPIO49
C443 0.047uF V13 J18 C11 AR27 I2S_I/F
R400
33 C417 0.047uF CVBS_VCM IFAGC IF_AGC DAC_DATA4 DAC_DATA4
SC_B COMP1_PB_IN_SOC R450 68 0 E10 AP26 AD5 R495 100
R405 C418 0.047uF C459 DAC_DATA3 DAC_DATA3 AUDCLK_OUT AUD_MASTER_CLK
SC_G 33 COMP1_Y_IN_SOC DTV/MNT_V_OUT_SOC U15 U16 D10 AR26 AD6 R496 100
C428 1000pF C454 0.1uF 0.1uF AUD_LRCH To front, woofer,
COMP1_Y_IN_SOC_SOY BUF_OUT1 ADC_I_INCOM DAC_DATA2 DAC_DATA2 DACLRCH
SC_CVBS_IN_SOY U14 U17 TU_W_BR/TW/CO C10 AP25 Y6 R452 100
R427
33 C419 0.047uF C439 BUF_OUT2 ADC_I_INP ADC_I_INP DAC_DATA1 DAC_DATA1 DACSLRCH/GPIO127 AUD_LRCH1 center amp FOR UB98/UB9
SC_R COMP1_PR_IN_SOC OPT 100pF V17 A10 R451 AT28 Y7
330
OPT 50V 10pF
OPT 50V 10pF
C472
C473
OPT 50V 10pF
R414 1% 75
To height amp FOR UB98/UB9
R416 1% 75
EU
ADC_I_INN
1% 75
C474
50V ADC_I_INN DAC_DATA0 DAC_DATA0 PCMI3SCK/GPIO112
AC6 R497 100
EU
DACSCK AUD_SCK
Placed as close as possible to SOC F3 D13 AR30 AC5 R498 100
EU
GPIO0 BIT0 AAD_GC4 AAD_GC4 DACLRCK AUD_LRCK
U7 F2 C13 AP29 AA6 C411
R412
REFT REFT GPIO1 BIT1 TU_W_BR/TW/CO AAD_GC3 AAD_GC3 PCMI3LRCK/GPIO113 10pF
V6 F1 R487-*1 E12 AR29 AB7 50V
REFB REFB GPIO2 BIT2 AAD_GC2 AAD_GC2 PCMI3LRCH
R447 68 C440 0.047uF V7 G3 D12 AP28 AB5 OPT
ADC1_COM GPIO3 BIT3 10K AAD_GC1 AAD_GC1 DACCLFCH/GPIO126 URSA_RESET_SoC
R448 68 C441 0.047uF U10 G2 C12 AR28 AU14
R424 C420 0.047uF ADC2_COM GPIO4 BIT4 AAD_GC0 AAD_GC0 IEC958OUT SPDIF_OUT
COMP1_Pb 33 COMP2_PB_IN_SOC R449 68 C442 0.047uF V12 G1 AA32
R425 C421 0.047uF ADC3_COM GPIO5 BIT5 DACSUBMCLK
COMP1_Y 33 COMP2_Y_IN_SOC T5 H3 C17 AP35 AA34
C429 1000pF SC_ID_SOC SC1_SID GPIO6 BIT6 AAD_DATA9 AAD_DATA9 DACSUBLRCH
COMP2_Y_IN_SOC_SOY T6 H2 E16 AR35 AA33 AR403
BIT7
COMP1_Pr 33 C422 0.047uF
COMP2_PR_IN_SOC
SC_FB_SOC
U8
SC1_FB GPIO7
H1
AAD_DATA8
D16 AP34
AAD_DATA8 DACSUBSCK
AB34
33
D403
D406
1/16W
D401
BIT8
50V 10pF
50V 10pF
R415 1% 75
R417 1% 75
R431 COMP1_PB_IN_SOC
R413 1% 75
C430
C431
50V 10pF
PB1_IN GPIO8 AAD_DATA7 AAD_DATA7 DACSUBLRCK
C470
V8 J3 C16 AR34 AE32 +3.3V_NORMAL
COMP1_Y_IN_SOC Y1_IN GPIO9 BIT9 AAD_DATA6 AAD_DATA6 TEST1
V9 E18 E15 AP33 AE33
5.5V
5.5V
5.5V
COMP1_Y_IN_SOC_SOY SOY1_IN GPIO10 BIT10 AAD_DATA5 AAD_DATA5 TEST2
U9 E17 D15 AR33
COMP1_PR_IN_SOC PR1_IN GPIO11 AAD_DATA4 AAD_DATA4
V10 H16 C15 AP32 AT6
COMP2_PB_IN_SOC PB2_IN GPIO12 AAD_DATA3 AAD_DATA3 TX0N TXB0P/TX5P
U11 J2 E14 AR32 AU6
COMP2_Y_IN_SOC Y2_IN GPIO13 AAD_DATA2 AAD_DATA2 TX0P TXB0N/TX5N
V11 J1 D14 AP31 AT5
COMP2_Y_IN_SOC_SOY SOY2_IN GPIO14 AAD_DATA1 AAD_DATA1 TX1N TXB1P/TX4P
U12 K1 C14 AR31 AU5
Near Place Scart AMP COMP2_PR_IN_SOC PR2_IN GPIO15 SC_FB_BUF AAD_DATA0 AAD_DATA0 TX1P TXB1N/TX4N
E13 AP30 AT4
EU EU AAD_DATAEN AAD_DATAEN TX2N TXB2P/TX3P
AU4
SCART_AMP_R_FB TX2P TXB2N/TX3N
10K B18 AT36 AU3
25V 1uF ADCO_OUT_CLK ADCO_OUT_CLK TX3N TXBCLKP/TX2P
C6006 R6006 AU2
TX3P TXBCLKN/TX2N
A12 AT30 AT2
EU EU +2.5V_Normal HSR_AP0
B12 AU30
HSR_AP TX4N
AT1
TXB3P/TX1P
SCART_AMP_L_FB HSR_AM0 HSR_AM TX4P TXB3N/TX1N
Placed as close as possible to IC4300 A13 AT31 AR4
1uF 25V 10K HSR_BP0 HSR_BP TX5N TXB4P/TX0P
C6001 R6005 +3.3V_NORMAL B13 AU31 AR3
HSR_BM0 HSR_BM TX5P TXB4N/TX0N
A14 AT32 AP1
AUDIO IN L407 HSR_CP0
HSR_CM0
B14 AU32
HSR_CP
HSR_CM
TX6N
TX6P
AP2
TXA0P/TX11P
TXA0N/TX11N
AUAD_REF_PO A15 AT33 AP4
OPT HSR_CLKP0 HSR_CLKP TX7N TXA1P/TX10P
1% C447 1% C455 B15 AU33 AP3
IC400 R455 TXA1N/TX10N
R418 27K C432 4.7uF 1uF 10uF HSR_CLKM0 HSR_CLKM TX7P
SC_L_IN AUAD_L_CH3_IN NJM2561BF1 51K A16 AT34 AN4
25V HSR_DP0 HSR_DP TX8N TXA2P/TX9P
AUAD_L_REF 1% B16 AU34 AN3
R437 10K 1% HSR_DM0 HSR_DM TX8P TXA2N/TX9N
R457 A17 AT35 AM4
4.7uF C449
1% POWER_SAVE V+ 51K HSR_EP0 HSR_EP TX9N TXACLKP/TX8P
47K R456 1%
1 6 EU B17 AU35 AM3
R419 27K C433 4.7uF TXACLKN/TX8N
SC_R_IN AUAD_R_CH3_IN C412 HSR_EM0 HSR_EM TX9P
AL4
0.1uF TX10N TXA3P/TX7P
R438 10K 1% VOUT GND AT14 AL3
0.1uF
2 EU 5
C414
AUD_HPDRV_LRCH TX10P TXA3N/TX7N
AT15 AK1
DTV/MNT_V_OUT AUD_HPDRV_LRCK TX11N TXA4P/TX6P
NC AU15 AK2
EU
VSAG VIN AUD_HPDRV_SCK TX11P TXA4N/TX6N
3 4 AK4
TX12N TXD0P/TX17P
DTV/MNT_V_OUT_SOC AC7 AK3
AUAD_R_REF FRC_LR_O_SYNC_FLAG TX12P TXD0N/TX17N
R402 33 AN5
1% L/DIM0_VS L_VSOUT_LD
COMP1/AV1/DVI_L_IN AUAD_M_REF AR14 AJ4
R420 27K C434 4.7uF L/DIM0_SCLK TXD1P/TX16P
AUAD_L_CH2_IN AR404 DIM0_SCLK TX13N
AP14 AJ3
1/10W
L/DIM0_MOSI TXD1N/TX16N
DIM0_MOSI TX13P
R454
33
OPT
R439 10K 1% 1% C456 AN14 AH4
1% R458 TXD2P/TX15P
5%
COMP1/AV1/DVI_R_IN 4.7uF DIM1_SCLK TX14N
AP13
2
R421 27K C435 4.7uF 47K AH3
AUAD_R_CH2_IN 10V DIM1_MOSI TX14P TXD2N/TX15N
C448 OPT L/DIM0_VS AG4
4.7uF L/DIM0_SCLK TX15N TXDCLKP/TX14P
R440 10K 1% AF6 AG3
10V PWM0 TX15P TXDCLKN/TX14N
L/DIM0_MOSI PWM1 AF7 AF1
PWM1 TX16N TXD3P/TX13P
TU_W_BR/TW TU_W_BR/TW TU_W_BR/TW BPL_IN AD7 AF2
PWM2
R443-*1 R444-*1 C436-*1 PWM2 TX16P TXD3N/TX13N
AE6 AF4
100pF BPL_IN PWM_IN TX17N TXD4P/TX12P
220 220 AF3
NON_TU_W_BR/TW TX17P TXD4N/TX12N
+12V AP5 AE4
R443 C437 EPI_EO TX18N TXC0P/TX23P
AN8 AE3
ADC_I_INN IF_N EPI_VST TX18P TXC0N/TX23N
51 0.01uF AP8 AD4
NON_TU_W_BR/TW EPI_DPM TX19N TXC1P/TX22P
AR7 AD3
AFE 3CH REF Setting
100K
R403
100K
R408
EU
EU
C436 L406 EPI_MCLK TX19P TXC1N/TX22N
To ADC 22pF OPT AN7 AC4
TXC2P/TX21P
EPI_GCLK TX20N
SCART_FB_BUFFER
SCART_Lout EU NON_TU_W_BR/TW AC3
+3.3V_NORMAL R444 C438 TX20P TXC2N/TX21N
SCART_Lout_SOC AB1
C403
ADC_I_INP IF_P TX21N TXCCLKP/TX20P
51 0.01uF Placed as close as possible to IC4300 AB2
SCART_Rout 2.2uF EU TX21P TXCCLKN/TX20N
10V AB4
R446
4.7K
C444 TX22N TXC3P/TX19P
C406
SCART_Rout_SOC Tuner IF Filter Placed as close as possible to IC100
REFT
AB3
TX22P TXC3N/TX19N
100K
R404
AA4
100K
R409
EU
0.1uF
EU
2.2uF SC_FB_BUF TXC4P/TX18P
10V TX23N
C446 AA3
SCART_FB_BUFFER C Must be used TX23P TXC4N/TX18N
0.1uF
SC_FB R401 HP_OUT HP_OUT
470 B L400 C445 AR5
R6450 MMBT3904(NXP) L401
BLM18PG121SN1D BLM18PG121SN1D REFB TX_LOCKN
HP_LOUT_MAIN 100 1/16W Q400
HP_ROUT 0.1uF
AUDA_OUTL 5% E SCART_FB_BUFFER HP_LOUT
1K R406
SCART_FB_BUFFER
HP_LOUT_AMP HP_OUT HP_ROUT_AMP HP_OUT
R430
1/16W
C400 C409
22K
OPT
C407 Not Used Net (UB85/95/UC89)
0.01uF 0.22uF 0.22uF
1%
OPT 10V 10V
AUD_LRCH1
HP_ROUT_MAIN
R6451 DIMMING NON_OLED
100
AUDA_OUTR Place at JACK SIDE AR402
33
LG1154A LG1154D
R445
C401 1/16W
22K
OPT
0.01uF PWM2
PWM_DIM
OPT
PWM_DIM2 PWM1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-004-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
MAIN AUDIO/VIDEO
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DDR_VTT
IC100
LG1154D_H13D
IC500 IC502 M0_1_DDR_VREFCA IC504 M0_DDR_VREFCA_T
AR7 AR8 AR9 AR10 AR11 AR12
F15
M0_DDR_A0 H5TQ4G83AFR-PBC M0_DDR_VREFCA H5TQ4G83AFR-PBC H5TQ4G83AFR-PBC 56 56 56 56 56 56
R3104
56
IC505 M0_1_DDR_VREFCA_T
M0_DDR_A[0]
F13
M0_DDR_A1 M0_DDR_VREFDQ_T
H5TQ4G83AFR-PBC
M0_DDR_A[1] M0_1_DDR_VREFDQ
F17 M0_DDR_VREFDQ
M0_DDR_A[2]
F19
M0_DDR_A2
DDR3 DDR3 DDR3 M0_1_DDR_VREFDQ_T
K3 J8 K3 J8
M0_DDR_A[3]
E10
M0_DDR_A3
M0_DDR_A0
K3
A0 4Gbit VREFCA
J8 M0_DDR_A0 A0
4Gbit VREFCA M0_DDR_A0 A0 4Gbit VREFCA DDR3
M0_DDR_A4 L7 L7 L7 K3 J8
M0_DDR_A[4] M0_DDR_A1 A1 M0_DDR_A1 A1 M0_DDR_A0
E18
M0_DDR_A5
M0_DDR_A1
L3
A1 L3 L3 L7
A0 4Gbit VREFCA
M0_DDR_A[5] M0_DDR_A2 A2 M0_DDR_A2 A2 M0_DDR_A1 A1
E11 M0_DDR_A2 A2 K2 E1 K2 E1 L3
M0_DDR_A[6] M0_DDR_A6 K2 E1 M0_DDR_A3 M0_DDR_A3 M0_DDR_A2
F18 M0_DDR_A3 A3 VREFDQ A3 VREFDQ A3 VREFDQ A2
M0_DDR_A7 L8 L8 L8 K2 E1
M0_DDR_A[7] M0_DDR_A4 A4 M0_DDR_A4 A4 M0_DDR_A3 A3 VREFDQ
F11 M0_DDR_A4 A4 L2 L2 L8
M0_DDR_A[8] M0_DDR_A8 L2 M0_DDR_A5 VDDC15_M0 M0_DDR_A5 VDDC15_M0 M0_DDR_A4
F16 M0_DDR_A5 A5 R558 VDDC15_M0 A5 R560 A5 R559 A4
M0_DDR_A9 M8 H8 M8 H8 M8 H8 L2
M0_DDR_A[9] M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ M0_DDR_A5 A5 R561 VDDC15_M0
E9 M0_DDR_A6 A6 ZQ M2 M2 M8 H8
M0_DDR_A[10] M0_DDR_A10 M2 240 240 240
E12 M0_DDR_A7 M0_DDR_A7 A7 1% M0_DDR_A7 A7 1% M0_DDR_A6 A6 ZQ
A7 1% N8 N8 M2 240
M0_DDR_A[11] M0_DDR_A11 N8 M0_DDR_A8 M0_DDR_A8 M0_DDR_A7
E13 M0_DDR_A8 A8 A8 A8 A7 1%
M0_DDR_A12 M3 A2 M3 A2 M3 A2 N8
M0_DDR_A[12] M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1 M0_DDR_A8 A8
E16 M0_DDR_A9 A9 VDD_1 H7 A9 H7 A9 M3 A2
M0_DDR_A[13] M0_DDR_A13 H7 A9 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A9
F12 M0_DDR_A10 A10/AP VDD_2 A9 VDD_1
M0_DDR_A14 M7 D7 M7 D7 M7 D7 H7 A9
M0_DDR_A[14] M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 M0_DDR_A10 A10/AP VDD_2
F14 M0_DDR_A11 A11 VDD_3 K7 G2 K7 G2 M7 D7
M0_DDR_A[15] M0_DDR_A15 K7 G2
M0_DDR_A12 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A11 A11 VDD_3
A12/BC VDD_4 N3 G8 N3 G8 K7 G2
N3 G8 M0_DDR_A13 M0_DDR_A13 M0_DDR_A12
E19 M0_DDR_A13 A13 VDD_5 A13 VDD_5 A13 VDD_5 A12/BC VDD_4
M0_DDR_BA[0] M0_DDR_BA0 N7 K1 N7 K1 N7 K1 N3 G8
F10 M0_DDR_A14 M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 M0_DDR_A13 A13 VDD_5
A14 VDD_6 J7 K9 J7 K9 N7 K1
M0_DDR_BA[1] M0_DDR_BA1 J7 K9 M0_DDR_A15 M0_DDR_A15 M0_DDR_A14
E15 M0_DDR_A15 A15 VDD_7 A15 VDD_7 A15 VDD_7 A14 VDD_6
M0_DDR_BA[2] M0_DDR_BA2 M1 M1 M1 J7 K9
VDD_8 VDD_8 M0_DDR_A15 A15 VDD_7
VDD_8 J2 M9 J2 M9 M1
J2 M9 M0_DDR_BA0 M0_DDR_BA0
B10 M0_DDR_BA0 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 VDD_8
M0_U_CLK K8 K8 K8 J2 M9
M0_DDR_U_CLK M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_BA0 BA0 VDD_9
A10 M0_DDR_BA1 BA1 J3 J3 K8
M0_DDR_U_CLKN M0_U_CLKN J3 M0_DDR_BA2 M0_DDR_BA2 M0_DDR_BA1
A19 M0_DDR_BA2 BA2 BA2 BA2 BA1
M0_DDR_D_CLK M0_D_CLK B9 B9 B9 J3
B19 VDDQ_1 VDDQ_1 M0_DDR_BA2 BA2
VDDQ_1 F7 C1 F7 C1 B9
M0_DDR_D_CLKN M0_D_CLKN F7 C1 M0_D_CLK M0_U_CLK
E14 M0_D_CLK CK VDDQ_2 CK VDDQ_2 CK VDDQ_2 VDDQ_1
M0_DDR_CKE G7 E2 0.1uF G7 E2 C583 0.1uF G7 E2 C568 0.1uF F7 C1
M0_DDR_CKE C559 M0_D_CLKN CK VDDQ_3 M0_U_CLKN CK VDDQ_3 M0_U_CLK CK VDDQ_2
M0_D_CLKN CK VDDQ_3 G9 E9 0.1uF G9 E9 0.1uF G7 E2 0.1uF
G9 E9 C560 0.1uF C574 C569 C572
F21 M0_DDR_CKE M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 M0_U_CLKN CK VDDQ_3
CKE VDDQ_4 G9 E9 C577 0.1uF
M0_DDR_ODT M0_DDR_ODT M0_DDR_CKE
E21 CKE VDDQ_4
M0_DDR_RASN H2 H2 H2
M0_DDR_RASN CS CS
E20 CS G1 G1 H2
M0_DDR_CASN M0_DDR_CASN G1 M0_DDR_ODT ODT M0_DDR_ODT ODT
F20 M0_DDR_ODT ODT CS
M0_DDR_WEN F3 F3 F3 G1
M0_DDR_WEN M0_DDR_RASN RAS M0_DDR_RASN RAS M0_DDR_ODT ODT
M0_DDR_RASN RAS G3 G3 F3
G3 M0_DDR_CASN M0_DDR_CASN M0_DDR_RASN
E17 M0_DDR_CASN CAS CAS CAS RAS
M0_DDR_RESET_N H3 H3 H3 G3
M0_DDR_RESET_N M0_DDR_WEN WE M0_DDR_WEN WE M0_DDR_CASN CAS
M0_DDR_WEN WE H3
F9 R500 M0_DDR_WEN WE
240 N2 N2
M0_DDR_ZQCAL N2 M0_DDR_RESET_N RESET M0_DDR_RESET_N RESET
1% M0_DDR_RESET_N RESET N2
B20 M0_DDR_RESET_N RESET
M0_DDR_DQS[0] M0_DDR_DQS0
A20 C3 C3
M0_DDR_DQS_N[0] M0_DDR_DQS_N0 C3 M0_DDR_DQS1 M0_DDR_DQS2
C19 M0_DDR_DQS0 DQS DQS DQS
M0_DDR_DQS1 D3 D3 D3 C3
M0_DDR_DQS[1] M0_DDR_DQS_N1 DQS M0_DDR_DQS_N2 DQS M0_DDR_DQS3 DQS
D19 M0_DDR_DQS_N0 DQS D3
M0_DDR_DQS_N[1] M0_DDR_DQS_N1 M0_DDR_DQS_N3
A11 DQS
M0_DDR_DQS2 B7 A1 B7 A1 B7 A1
M0_DDR_DQS[2] M0_DDR_DM1 DM/TDQS VSS_1 M0_DDR_DM2 DM/TDQS VSS_1
B11 M0_DDR_DM0 DM/TDQS VSS_1 A7 A8 A7 A8 B7 A1
M0_DDR_DQS_N[2] M0_DDR_DQS_N2 A7 A8 M0_DDR_DM3
C10 NF/TDQS VSS_2 NF/TDQS VSS_2 NF/TDQS VSS_2 DM/TDQS VSS_1
M0_DDR_DQS[3] M0_DDR_DQS3 B1 B1 B1 A7 A8
D10 VSS_3 VSS_3 VSS_3 NF/TDQS VSS_2
M0_DDR_DQS_N[3] M0_DDR_DQS_N3 D8 D8 D8 B1
VSS_4 VSS_4 VSS_4 VSS_3
F2 F2 F2 D8
D18 VSS_5 VSS_5 VSS_5 VSS_4
M0_DDR_DM[0] M0_DDR_DM0 F8 F8 F8 F2
C20 VSS_6 VSS_6 VSS_6 VSS_5
M0_DDR_DM1 B3 J1 B3 J1 B3 J1 F8
M0_DDR_DM[1] M0_DDR_DQ8 DQ0 VSS_7 M0_DDR_DQ16 DQ0 VSS_7 VSS_6
D9 M0_DDR_DQ0 DQ0 VSS_7 C7 J9 C7 J9 B3 J1
M0_DDR_DM[2] M0_DDR_DM2 C7 J9 M0_DDR_DQ9 DQ1 M0_DDR_DQ17 DQ1 M0_DDR_DQ24
C11 M0_DDR_DQ1 DQ1 VSS_8 VSS_8 VSS_8 DQ0 VSS_7
M0_DDR_DM3 C2 L1 C2 L1 C2 L1 C7 J9
M0_DDR_DM[3] M0_DDR_DQ10 DQ2 VSS_9 M0_DDR_DQ18 DQ2 VSS_9 M0_DDR_DQ25 DQ1 VSS_8
M0_DDR_DQ2 DQ2 VSS_9 C8 L9 C8 L9 C2 L1
C8 L9 M0_DDR_DQ11 DQ3 M0_DDR_DQ19 DQ3 M0_DDR_DQ26
D22 M0_DDR_DQ3 DQ3 VSS_10 VSS_10 VSS_10 DQ2 VSS_9
M0_DDR_DQ0 E3 N1 E3 N1 E3 N1 C8 L9
M0_DDR_DQ[0] M0_DDR_DQ12 DQ4 VSS_11 M0_DDR_DQ20 DQ4 VSS_11 M0_DDR_DQ27 DQ3 VSS_10
C15 M0_DDR_DQ4 DQ4 VSS_11 E8 N9 E8 N9 E3 N1
M0_DDR_DQ[1] M0_DDR_DQ1 E8 N9 M0_DDR_DQ13 M0_DDR_DQ21 M0_DDR_DQ28
C23 M0_DDR_DQ5 DQ5 VSS_12 DQ5 VSS_12 DQ5 VSS_12 DQ4 VSS_11
M0_DDR_DQ2 D2 D2 D2 E8 N9
M0_DDR_DQ[2] M0_DDR_DQ14 DQ6 M0_DDR_DQ22 DQ6 M0_DDR_DQ29 DQ5 VSS_12
D16 M0_DDR_DQ6 DQ6 E7 E7 D2
M0_DDR_DQ[3] M0_DDR_DQ3 E7 M0_DDR_DQ15 M0_DDR_DQ23 M0_DDR_DQ30
B24 M0_DDR_DQ7 DQ7 DQ7 DQ7 DQ6
M0_DDR_DQ[4] M0_DDR_DQ4 B2 B2 B2 E7
B15 VSSQ_1 VSSQ_1 VSSQ_1 M0_DDR_DQ31 DQ7
M0_DDR_DQ5 A3 B8 A3 B8 A3 B8 B2
M0_DDR_DQ[5] NC_1 VSSQ_2 NC_1 VSSQ_2 VSSQ_1
D23 NC_1 VSSQ_2 F1 C9 F1 C9 A3 B8
M0_DDR_DQ[6] M0_DDR_DQ6 F1 C9
A15 NC_2 VSSQ_3 NC_2 VSSQ_3 NC_2 VSSQ_3 NC_1 VSSQ_2
M0_DDR_DQ7 F9 D1 F9 D1 F9 D1 F1 C9
M0_DDR_DQ[7] NC_3 VSSQ_4 NC_3 VSSQ_4 NC_2 VSSQ_3
C16 NC_3 VSSQ_4 H1 D9 H1 D9 F9 D1
M0_DDR_DQ[8] M0_DDR_DQ8 H1 D9
D21 NC_4 VSSQ_5 NC_4 VSSQ_5 NC_4 VSSQ_5 NC_3 VSSQ_4
M0_DDR_DQ9 H9 H9 H9 H1 D9
M0_DDR_DQ[9] NC_5 NC_5 NC_4 VSSQ_5
D17 NC_5 H9
M0_DDR_DQ[10] M0_DDR_DQ10
C22 NC_5
M0_DDR_DQ[11] M0_DDR_DQ11
C18
M0_DDR_DQ[12] M0_DDR_DQ12
C21
M0_DDR_DQ[13] M0_DDR_DQ13
C17
M0_DDR_DQ[14] M0_DDR_DQ14
D20
M0_DDR_DQ[15] M0_DDR_DQ15
C13
M0_DDR_DQ[16] M0_DDR_DQ16
D7
M0_DDR_DQ[17] M0_DDR_DQ17
D13
M0_DDR_DQ[18] M0_DDR_DQ18
C6
M0_DDR_DQ[19] M0_DDR_DQ19
D14
M0_DDR_DQ[20] M0_DDR_DQ20
D6
M0_DDR_DQ[21] M0_DDR_DQ21
C14
M0_DDR_DQ[22] M0_DDR_DQ22
A5
M0_DDR_DQ[23] M0_DDR_DQ23
C7
M0_DDR_DQ[24] M0_DDR_DQ24
D12 Real USE : 1Gbit
M0_DDR_DQ[25] M0_DDR_DQ25
D8
M0_DDR_DQ[26] M0_DDR_DQ26 H5TQ1G63DFR-PBC(x16)
B13
M0_DDR_DQ[27] M0_DDR_DQ27
C9
M0_DDR_DQ[28] M0_DDR_DQ28
C12 1Gbit : T7(NC_6) DDR_SAMSUNG
M0_DDR_DQ[29] M0_DDR_DQ29 DDR_SAMSUNG
C8
M0_DDR_DQ[30] M0_DDR_DQ30 IC501 4Gbit : T7(A14) IC503 DDR_HYNIX
D11 M1_DDR_VREFCA DDR_HYNIX M1_1_DDR_VREFCA IC503-*1
M0_DDR_DQ[31] M0_DDR_DQ31 K4B4G1646B-HCK0 IC501-*1 K4B4G1646B-HCK0 H5TQ4G63AFR-PBC
H5TQ4G63AFR-PBC
N3 M8
A0 VREFCA
P7
N3 M8 A1
A0 VREFCA P3
P7 A2
A1 N2 H1
P3 A3 VREFDQ
A2 P8
N2 H1 A4
M1_DDR_VREFDQ A3 VREFDQ
M1_1_DDR_VREFDQ P2
N3 DDR3 M8
P8
P2
R8
A4
A5
L8
M1_DDR_A0
N3
A0
DDR3 VREFCA
M8 R8
R2
A5
A6
A7
ZQ
L8
M1_DDR_A0 A0 VREFCA R2
A6 ZQ
P7
T8
A8
4Gbit
A7 R3 B2
T8 A9 VDD_1
P7 L7 D9
4Gbit
A8
M1_DDR_A1 A1
R3
L7
A9
A10/AP
VDD_1
VDD_2
B2
D9 M1_DDR_A1 A1 R7
N7
A10/AP
A11
VDD_2
VDD_3
G7
K2
R7 G7
P3 A12/BC VDD_4
M1_DDR_A2
P3
A2 (x16)
N7
T3
A11
A12/BC
A13
VDD_3
VDD_4
VDD_5
K2
K8 M1_DDR_A2 A2 (x16) T3
T7
M7
A13
A14
VDD_5
VDD_6
K8
N1
N9
N2 H1
T7
M7
A14
A15
VDD_6
VDD_7
N1
N9 N2 H1 M2
A15 VDD_7
VDD_8
R1
R9
M1_DDR_A3 A3 VREFDQ M2
VDD_8
R1
R9
M1_DDR_A3 A3 VREFDQ N8
BA0
BA1
VDD_9
P8 N8
BA0
BA1
VDD_9
P8 M3
BA2
A1
M1_DDR_A4 A4
M3
BA2
VDDQ_1
A1 M1_DDR_A4 A4 J7
K7
CK
VDDQ_1
VDDQ_2
A8
C1
IC100 P2
J7
K7
CK VDDQ_2
A8
C1
P2 K9
CK
CKE
VDDQ_3
VDDQ_4
C9
M1_DDR_A5 A5
K9
CK
CKE
VDDQ_3
VDDQ_4
C9 M1_DDR_A5 A5 L2
VDDQ_5
D2
E9
LG1154D_H13D R8 L8 R543 L2
VDDQ_5
D2
E9 R8 L8 R545 240
K1
J3
CS
ODT
VDDQ_6
VDDQ_7
F1
H2
M1_DDR_A6 240 K1
CS
ODT
VDDQ_6
VDDQ_7
F1
M1_DDR_A6 A6 ZQ K3
RAS VDDQ_8
H9
A6 ZQ J3
K3
RAS VDDQ_8
H2
H9 R2 L3
CAS
WE
VDDQ_9
R2 VDDC15_M1 L3
CAS VDDQ_9
M1_DDR_A7 NC_1
J1
M1_DDR_A7 A7
WE
NC_1
J1 A7 VDDC15_M1
T2
RESET NC_2
J9
L1
T8
T2
RESET NC_2
J9
L1
T8 NC_3
NC_4
L9
M1_DDR_A8 A8
NC_3
NC_4
L9 M1_DDR_A8 A8
F3
G3
DQSL
R3 B2
F3
G3
DQSL
DQSL
R3 B2 C7
DQSL
A9
N6 M1_DDR_A9 A9 VDD_1 C7 A9
M1_DDR_A9 A9 VDD_1 B7
DQSU
DQSU
VSS_1
VSS_2
B3
M1_DDR_A[0] M1_DDR_A0 L7 D9 B7
DQSU
DQSU
VSS_1
VSS_2
B3 L7 D9 E7
VSS_3
E1
G8
R6 M1_DDR_A10 A10/AP VDD_2 E7
DML
VSS_3
VSS_4
E1
G8 M1_DDR_A10 A10/AP VDD_2 D3
DML
DMU
VSS_4
VSS_5
J2
J8
M1_DDR_A[1] M1_DDR_A1 D3 J2
R7 G7 VSS_6
DDR3 1.5V bypass Cap - Place these caps near Memory
R7 G7 DMU VSS_5
J8
E3
DQL0 VSS_7
M1
DDR3 1.5V bypass Cap - Place these caps near Memory
L6 M1_DDR_A11 A11 VDD_3
E3
DQL0
VSS_6
VSS_7
M1 M1_DDR_A11 A11 VDD_3
F7
F2
DQL1 VSS_8
M9
P1
M1_DDR_A[2] M1_DDR_A2 N7 K2
F7
F2
DQL1
DQL2
VSS_8
VSS_9
M9
P1 N7 K2 F8
H3
DQL2
DQL3
VSS_9
VSS_10
P9
T1
J6 M1_DDR_A12 A12/BC VDD_4
F8
H3
DQL3 VSS_10
P9
T1
M1_DDR_A12 A12/BC VDD_4 H8
DQL4
DQL5
VSS_11
VSS_12
T9
M1_DDR_A[3] M1_DDR_A3 T3 K8 H8
DQL4
DQL5
VSS_11
VSS_12
T9 T3 K8 G2
H7
DQL6
U5 M1_DDR_A13 A13 VDD_5
G2
H7
DQL6
DQL7
M1_DDR_A13 A13 VDD_5 D7
DQL7
VSSQ_1
B1
B9
M1_DDR_A[4] M1_DDR_A4 T7 N1 D7
VSSQ_1
B1
B9
T7 N1 C3
DQU0
DQU1
VSSQ_2
VSSQ_3
D1
J5 M1_DDR_A14 A14 VDD_6
C3
DQU0
DQU1
VSSQ_2
VSSQ_3
D1 M1_DDR_A14 A14 VDD_6
C8
C2
DQU2 VSSQ_4
D8
E2
M1_DDR_A[5] M1_DDR_A5 M7 N9
C8
C2
DQU2 VSSQ_4
D8
E2 M7 N9 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
T5 VDDC15_M0 M0_DDR_CKE A7
DQU3 VSSQ_5
E8
M1_DDR_A15 A15 VDD_7
A2
DQU5 VSSQ_7
F9
M1_DDR_A6 M1_DDR_A15 A15 VDD_7 A2
DQU4 VSSQ_6
F9
R1
B8
A3
DQU6 VSSQ_8
G1
G9
M1_DDR_A[6] R1 B8
DQU5
DQU6
VSSQ_7
VSSQ_8
G1 DQU7 VSSQ_9
K6 VDD_8
A3
DQU7 VSSQ_9
G9
VDD_8
M1_DDR_A[7] M1_DDR_A7 M2 R9 M2 R9
U6 R541 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9
M1_DDR_A[8] M1_DDR_A8 R520 N8 N8
M6 10K M1_DDR_BA1 BA1 M1_DDR_BA1 BA1
M1_DDR_A[9] M1_DDR_A9 10K M3 M3
V5 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2
M1_DDR_A[10] M1_DDR_A10 A1 A1
R5 VDDQ_1 VDDQ_1
M1_DDR_A[11] M1_DDR_A11 M0_DDR_RESET_N J7 A8
P5 VDDC15_M1 M1_DDR_CKE J7 A8 M1_U_CLK
M1_D_CLK CK VDDQ_2 CK VDDQ_2
M1_DDR_A[12] M1_DDR_A12 K7 C1 K7 C1
L5 M1_D_CLKN CK VDDQ_3 M1_U_CLKN CK VDDQ_3
M1_DDR_A[13] M1_DDR_A13 K9 C9 K9 C9
T6 R540 M1_DDR_CKE CKE VDDQ_4 M1_DDR_CKE CKE VDDQ_4
M1_DDR_A[14] M1_DDR_A14 D2 D2
P6 M0_U_CLK R521 10K VDDQ_5 VDDQ_5
M1_DDR_A[15] M1_DDR_A15 M0_D_CLK L2 E9
L2 E9
10K CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1
200
R535
H5 M1_DDR_ODT
200
R519
M1_DDR_ODT ODT VDDQ_7 ODT VDDQ_7
M1_DDR_BA[0] M1_DDR_BA0 J3 H2 J3 H2 C561 0.1uF
V6 M1_DDR_RESET_N C529 0.1uF M1_DDR_RASN RAS VDDQ_8
M1_DDR_BA1 M1_DDR_RASN RAS VDDQ_8 K3 H9
M1_DDR_BA[1] K3 H9 C530 C562 0.1uF
M5 M1_DDR_CASN 0.1uF M1_DDR_CASN CAS VDDQ_9
M1_DDR_BA[2] M1_DDR_BA2 M0_U_CLKN CAS VDDQ_9 L3
M0_D_CLKN L3 M1_DDR_WEN
M1_DDR_WEN WE WE
J1 J1
R2 NC_1 NC_1
M1_DDR_U_CLK M1_U_CLK M0_U_CLK M1_D_CLK M1_U_CLK T2 J9 T2 J9
R1 M0_D_CLK M1_DDR_RESET_N RESET NC_2
M1_U_CLKN M1_DDR_RESET_N RESET NC_2 L1
M1_DDR_U_CLKN L1
100
F1 NC_3
100
200
R581
NC_3
R530
M1_D_CLK L9
200
R580
M1_DDR_D_CLK
R518
F2 L9
NC_4 NC_4
M1_DDR_D_CLKN M1_D_CLKN F3 F3
N5 M1_DDR_DQS0 DQSL M1_DDR_DQS2 DQSL
M1_DDR_CKE M1_DDR_CKE G3 G3
M0_U_CLKN M1_D_CLKN M1_U_CLKN M1_DDR_DQS_N0 M1_DDR_DQS_N2 DQSL
M0_D_CLKN DQSL
G6
M1_DDR_ODT M1_DDR_ODT C7 A9 C7 A9
F5 M1_DDR_DQS1 DQSU VSS_1 M1_DDR_DQS3 DQSU VSS_1
M1_DDR_RASN M1_DDR_RASN B7 B3 B7 B3
G5 M1_DDR_DQS_N1 DQSU VSS_2 M1_DDR_DQS_N3 DQSU VSS_2
M1_DDR_CASN M1_DDR_CASN E1 E1
H6 VSS_3 VSS_3
M1_DDR_WEN M1_DDR_WEN E7 G8 E7 G8
M1_DDR_DM0 DML VSS_4 M1_DDR_DM2 DML VSS_4
D3 J2 D3 J2
K5 M1_DDR_DM1 DMU VSS_5 M1_DDR_DM3 DMU VSS_5
M1_DDR_RESET_N M1_DDR_RESET_N J8 J8
VSS_6 VSS_6
E3 M1 E3 M1
F6 240 R501 M1_DDR_DQ0 DQL0 VSS_7 M1_DDR_DQ16 DQL0 VSS_7
M1_DDR_ZQCAL VDDC15_M0 F7 M9 F7 M9
1% VDDC15_M0 VDDC15_M1 VDDC15_M1 M1_DDR_DQ1 DQL1 VSS_8 M1_DDR_DQ17 DQL1 VSS_8
VDDC15_M0 F2 P1
E2 VDDC15_M0 F2 P1 M1_DDR_DQ18
M1_DDR_DQ2 DQL2 VSS_9 DQL2 VSS_9
M1_DDR_DQS[0] M1_DDR_DQS0 M0_1_DDR_VREFCA F8 P9 F8 P9
E1 M0_1_DDR_VREFCA_T M1_1_DDR_VREFCA M1_DDR_DQ3 M1_DDR_DQ19 DQL3 VSS_10
M1_DDR_DQS_N[0] M1_DDR_DQS_N0 M0_DDR_VREFCA M0_DDR_VREFCA_T M1_DDR_VREFCA DQL3 VSS_10 H3 T1
F3 H3 T1 M1_DDR_DQ20
M1_DDR_DQ4 DQL4 VSS_11 DQL4 VSS_11
R536
1K 1%
M1_DDR_DQS[1] M1_DDR_DQS1 H8 T9 H8 T9
R514
1K 1%
R531
F4 M1_DDR_DQ21
1K 1%
DQL5 VSS_12
R510
R554
1K 1%
1K 1%
M1_DDR_DQ5 DQL5 VSS_12
R550
M1_DDR_DQS_N1 G2
1K 1%
M1_DDR_DQS_N[1] G2
P1 M1_DDR_DQ6 DQL6 M1_DDR_DQ22 DQL6
M1_DDR_DQS[2] M1_DDR_DQS2 H7 H7
P2 M1_DDR_DQ7 DQL7 M1_DDR_DQ23 DQL7
M1_DDR_DQS_N[2] M1_DDR_DQS_N2 B1 B1
R3
0.1uF
VSSQ_1 VSSQ_1
0.1uF
M1_DDR_DQS3 D7 B9
0.1uF
M1_DDR_DQS[3]
1%
0.1uF
0.1uF
D7 B9
1%
R4 M1_DDR_DQ24
0.1uF
DQU0 VSSQ_2
1%
M1_DDR_DQ8
1%
1%
DQU0 VSSQ_2
R537
M1_DDR_DQS_N[3] M1_DDR_DQS_N3 C3 D1
1%
C3 D1
R515
R532
M1_DDR_DQ25 DQU1 VSSQ_3
R511
R555
M1_DDR_DQ9 DQU1 VSSQ_3
R551
C8 D8 C8 D8
C512
1K
G4 M1_DDR_DQ10 DQU2 VSSQ_4 M1_DDR_DQ26 DQU2 VSSQ_4
C504
1K
M1_DDR_DM0
C508
C2 E2
1K
M1_DDR_DM[0]
C500
C552
1K
1K
C2 E2
C550
E3 M1_DDR_DQ27
1K
M1_DDR_DQ11 DQU3 VSSQ_5 DQU3 VSSQ_5
M1_DDR_DM[1] M1_DDR_DM1 A7 E8 A7 E8
T4 M1_DDR_DQ12 DQU4 VSSQ_6 M1_DDR_DQ28 DQU4 VSSQ_6
M1_DDR_DM[2] M1_DDR_DM2 A2 F9 A2 F9
P3 M1_DDR_DQ13 DQU5 VSSQ_7 M1_DDR_DQ29 DQU5 VSSQ_7
M1_DDR_DM[3] M1_DDR_DM3 B8 G1 B8 G1
M1_DDR_DQ14 DQU6 VSSQ_8 M1_DDR_DQ30 DQU6 VSSQ_8
A3 G9 A3 G9
C4 M1_DDR_DQ15 DQU7 VSSQ_9 M1_DDR_DQ31 DQU7 VSSQ_9
M1_DDR_DQ[0] M1_DDR_DQ0
K3
M1_DDR_DQ[1] M1_DDR_DQ1
B3
M1_DDR_DQ[2] M1_DDR_DQ2
J4
M1_DDR_DQ[3] M1_DDR_DQ3
A3
M1_DDR_DQ[4] M1_DDR_DQ4 VDDC15_M0
K2 VDDC15_M0 VDDC15_M0 VDDC15_M1 VDDC15_M1 VDDC15_M1
M1_DDR_DQ[5] M1_DDR_DQ5 VDDC15_M0
B4
M1_DDR_DQ[6] M1_DDR_DQ6 M0_1_DDR_VREFDQ
K1 M0_1_DDR_VREFDQ_T M1_1_DDR_VREFDQ
M1_DDR_DQ[7] M1_DDR_DQ7 M0_DDR_VREFDQ M0_DDR_VREFDQ_T M1_DDR_VREFDQ
J3
M1_DDR_DQ8
R538
1K 1%
M1_DDR_DQ[8]
R516
1K 1%
R533
D4
1K 1%
* DDR_VTT
R512
R556
1K 1%
1K 1%
M1_DDR_DQ9
R552
1K 1%
M1_DDR_DQ[9]
H4
M1_DDR_DQ[10] M1_DDR_DQ10
C3
M1_DDR_DQ[11] M1_DDR_DQ11
G3
0.1uF
0.1uF
M1_DDR_DQ12
0.1uF
M1_DDR_DQ[12]
1%
0.1uF
0.1uF
1%
D3
0.1uF
1%
1%
1%
M1_DDR_DQ13
1uF
1uF
R539
M1_DDR_DQ[13]
1%
R517
R534
H3
R513
R557
M1_DDR_DQ14
R553
M1_DDR_DQ[14] VDDC15_M0
+3.3V_NORMAL
C513
1K
E4
C505
1K
M1_DDR_DQ15
C509
C502
C516
1K
M1_DDR_DQ[15]
C501
C553
1K
1K
C551
M3
1K
M1_DDR_DQ[16] M1_DDR_DQ16
V4 R546 IC506
M1_DDR_DQ[17] M1_DDR_DQ17 10K 1% TPS51200DRCR [EP] L501
M4 UBW2012-121F
M1_DDR_DQ[18] M1_DDR_DQ18
W3 R549 C510
M1_DDR_DQ[19] M1_DDR_DQ19 10K
L4 1000pF REFIN VIN
M1_DDR_DQ[20] M1_DDR_DQ20 1% 1 10
W4
THERMAL
M1_DDR_DQ[21] M1_DDR_DQ21
L3
M1_DDR_DQ22
11
M1_DDR_DQ[22] VLDOIN PGOOD C515
Y2 2 9 4700pF
M1_DDR_DQ[23] M1_DDR_DQ23
V3
M1_DDR_DQ[24] M1_DDR_DQ24 DDR_VTT
N4 C511 VO GND
M1_DDR_DQ[25] M1_DDR_DQ25 3 8
U4 22uF DDR_VTT
M1_DDR_DQ[26] M1_DDR_DQ26 Place at the bottom side 10V
M2
M1_DDR_DQ[27] M1_DDR_DQ27 PGND EN
T3 L500 4 7
M1_DDR_DQ[28] M1_DDR_DQ28 UBW2012-121F
N3
M1_DDR_DQ[29] M1_DDR_DQ29
U3 VOSNS REFOUT
M1_DDR_DQ[30] M1_DDR_DQ30 5 6 C519 C520 C521 C522
P4 0.1uF 0.1uF 0.1uF 0.1uF
M1_DDR_DQ[31] M1_DDR_DQ31 C503 C506 C507 C514 16V 16V 16V 16V
10uF 10uF 10uF 0.1uF
Close to REFOUT pin
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-005-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+5V_CI_ON
C702 C703 CI_DATA[0-7]
0.1uF 4.7uF
10V CI_UB85/95
CI JK700
CI
10125901-015LF
/PCM_CE1
35 1
R716 100 36 2 CI_DATA[3]
/CI_CD1
CI 37 3 CI_DATA[4]
CI_TS_DATA[3]
38 4 CI_DATA[5]
CI_TS_DATA[4]
39 5 CI_DATA[6]
CI_DATA[0-7]
CI_TS_DATA[5] CI
40 6 CI_DATA[7]
CI_TS_DATA[6] AR712
CI R721 33 CI_DATA[0] 33 EB_DATA[0]
CI_TS_DATA[7] 41 7
CI_ADDR[10] CI_DATA[1] EB_DATA[1]
/PCM_CE2 42 8 CI_ADDR[10]
/PCM_IORD CI_DATA[2] EB_DATA[2]
/PCM_IOWR 43 9 /PCM_OE
CI_ADDR[11] CI_DATA[3] EB_DATA[3]
44 10 CI_ADDR[11] +5V_CI_ON
CI_IN_TS_DATA[0-7] 45 11 CI_ADDR[9]
CI_ADDR[9]
46 12 CI_ADDR[8] CI
CI_ADDR[8]
@netLa
CI_IN_TS_DATA[0] CI_ADDR[13] R723 CI_DATA[4] AR713 EB_DATA[4]
47 13 CI_ADDR[13] 33
10K
CI_IN_TS_DATA[1] 48 14 CI_ADDR[14] CI_DATA[5] EB_DATA[5]
CI_ADDR[14] CI
CI_IN_TS_DATA[2] 49 15 CI_DATA[6] EB_DATA[6]
/PCM_WE
CI_IN_TS_DATA[3] 50 16 CI_DATA[7] EB_DATA[7]
/PCM_IRQA
51 17 C706 0.1uF C707
CI EB_DATA[0-7]
CI 0.1uF
+5V_CI_ON 52 18 16V
CI_IN_TS_DATA[4] 53 19
CI_DATA[0-7]
CI_IN_TS_DATA[5] 54 20
CI_IN_TS_DATA[6] 55 21 CI_ADDR[12]
R709 CI_ADDR[12]
10K CI_IN_TS_DATA[7] 56 22 CI_ADDR[7]
CI_ADDR[7]
CI 57 23 CI_ADDR[6]
CI_TS_CLK CI_ADDR[6]
R701 33 CI 58 24 CI_ADDR[5]
PCM_RESET CI_ADDR[5]
R702 33 CI 59 25 CI_ADDR[4]
/PCM_WAIT CI_ADDR[4]
60 26 CI_ADDR[3]
CI_ADDR[3]
/PCM_REG 61 27 CI_ADDR[2]
CI_ADDR[2]
CI_TS_VAL 62 28 CI_ADDR[1]
CI_ADDR[1]
CI_TS_SYNC 63 29 CI_ADDR[0]
CI_ADDR[0]
64 30 CI_DATA[0]
CI_TS_DATA[0]
65 31 CI_DATA[1]
CI_TS_DATA[1]
66 32 CI_DATA[2]
CI_TS_DATA[2]
/CI_CD2 R717 CI 100 67 33
68 34
/PCM_CE2
G2 69 G1
CI_IN_TS_VAL
CI_IN_TS_CLK
CI_IN_TS_SYNC
C705
12pF
50V
OPT
TPO_DATA[0-7] CI
AR701
TPO_DATA[0] 33
CI_IN_TS_DATA[0]
TPO_DATA[1]
CI_IN_TS_DATA[1]
TPO_DATA[2]
CI_IN_TS_DATA[2]
TPO_DATA[3]
CI_IN_TS_DATA[3]
TPO_DATA[4]
CI_IN_TS_DATA[4]
TPO_DATA[5]
CI_IN_TS_DATA[5]
TPO_DATA[6]
CI_IN_TS_DATA[6]
TPO_DATA[7]
CI_IN_TS_DATA[7]
AR706 CI
33 CI CI
AR707 AR711
33 33
CI CI_ADDR[3] EB_ADDR[3] CI_ADDR[12] EB_ADDR[12]
AR705
33 CI_ADDR[0] EB_ADDR[0] CI_ADDR[13] EB_ADDR[13]
TPO_CLK CI_IN_TS_CLK
CI_ADDR[2] EB_ADDR[2] CI_ADDR[14] EB_ADDR[14]
TPO_SOP CI_IN_TS_SYNC
CI_ADDR[1] EB_ADDR[1] /PCM_REG CAM_REG_N
TPO_VAL CI_IN_TS_VAL
CI
AR708 CI
33
CI_ADDR[4] EB_ADDR[4] AR710 JK700-*1
33 10125901-115LF
CI_ADDR[5] EB_ADDR[5] /PCM_OE EB_OE_N
1 CI_UB98/D9 35
CI_ADDR[6] EB_ADDR[6] /PCM_WE EB_WE_N 2 36
3 37
CI_ADDR[7] EB_ADDR[7] /PCM_IORD EB_BE_N1 4 38
5 39
/PCM_IOWR EB_BE_N0 6 40
+5V_NORMAL 7 41
8 42
CI 9 43
AR709 10 44
33 11 45
CI_ADDR[8] EB_ADDR[8] 12 46
13 47
CI_ADDR[9] EB_ADDR[9] 14 48
15 49
CI_ADDR[10] EB_ADDR[10] 16 50
17 51
R703
R705
AR702 CI_ADDR[11] EB_ADDR[11]
10K
18 52
10K
19 53
/PCM_WAIT CAM_WAIT_N
20 54
21 55
/PCM_IRQA CAM_IREQ_N 22 56
23 57
/CI_CD2 CAM_CD2_N
24 58
100 25 59
/CI_CD1 26 60
CAM_CD1_N 27 61
28 62
29 63
CI
CI 30 64
C700 C701
31 65
32 66
0.1uF 0.1uF 33 67
16V 16V AR703 CI 34 68
G1 69 G2
CI_TS_CLK TPI_CLK
CI_TS_VAL TPI_VAL C704
100
CI_TS_SYNC TPI_SOP 12pF
50V
OPT CI slot body (33mm)
for UB98 / D9
AR704 CI
CI_TS_DATA[7] TPI_DATA[7]
CI_TS_DATA[6] TPI_DATA[6]
CI_TS_DATA[5] TPI_DATA[5]
100 CI POWER ENABLE CONTROL
CI_TS_DATA[4] TPI_DATA[4]
IC700
+5V_NORMAL AP2151WG-7 +5V_CI_ON
AR700 CI
CI_TS_DATA[3] TPI_DATA[3] IN OUT
5 1
CI_TS_DATA[2] TPI_DATA[2] C709 CI
CI_TS_DATA[1] TPI_DATA[1] 0.1uF C708
100 50V GND
CI_TS_DATA[0] TPI_DATA[0] 2 1uF
CI CI R706
25V
10K
R704 CI
100 EN FLG CI
PCM_5V_CTL 4 3
R700
10K
CI
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-007-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCIA
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+12V RESET_IC_DIODES
PANEL_POWER TYP 6000mA Power_DET
IC2307-*1
APX803D29
MMBT3906(NXP)
RESET 2 3 VCC
+3.5V_ST
L2313 L2314
1
MLB-201209-0120P-N2 GND
MLB-201209-0120P-N2 PANEL_VCC PD_20_24V_DIODES
+12V +3.5V_ST +3.5V_ST IC2308-*1
10K
R2301
R2337
1
100K APX803D29
R2300
C2317 C2330
Q2300
RL_ON 10K C2322
10uF PD_+12V PD_+3.5V RESET_IC_ROHM R2338 RESET 2 3 VCC
0.1uF 0.01uF Q2302 R2325 R2330
25V 50V IC2307 10K
2
AO4423
+3.3V_NORMAL 25V 2.7K 0 1
OPT OPT
1% 5% BD48K28G GND
3
S1 D4
1 AO4423 8
P13002
SMAW200-H24S5 R2310 S2 D3 POWER_DET
1K R2318 C2331 C2333 2 7
VDD VOUT
3 2
10K 10uF 10uF S3 D2
3 6
R2309 25V 25V R2329 R2332 C2336 1
C2339 C2355
PWR ON INV CTL 100 INV_CTL G D1 2K 2K 10uF PD_+12V
1 2 4 5
0.1uF 0.1uF GND
L2304 OPT OPT 25V R2326 16V
+3.5V_ST UBW2012-121F PDIM#1 3 4 PDIM#2 25V
PWM_DIM PWM_DIM2 OPT 1.2K
PWR_DET_MERGE
3.5V GND R2324 1% C2365
5 6
0.1uF
R2315
C2307 3.5V 7 8 3.5V 1.8K 16V
0.1uF GND 9 10 GND C2334
16V C 10uF PD_20_24V not to RESET
0
12V 11 12 12V R2317
Q2302-*1
R2336 at 8kV ESD
25V AO4447A +24V
+12V 12V 12V 10K B Q2301 100K
UBW2012-121F 13 14
L2306 PANEL_CTL OPT S_1 D_4
12V GND +24V 2SC3052 1 AO4447 8 C2362
15 16 UBW2012-121F PD_20_24V_ROHM 0.1uF PWR_DET_SEPARATE
R2314
S_2 D_3
GND 17 18 24V E 2 7
OPT
C2306 L2303 PD_20V PD_24V IC2308 16V
24V 24V S_3 D_2
PD_UHD_24V
0.1uF 19 20 C2316 3 6
R2327-*2 R2327-*1 R2327 BD48K28G
0
UBW2012-121F L2315 5.6K 8.2K
50V 24V 21 22 24V UBW2012-121F 0.1uF G D_1 9.1K
4 5
1% 1% 1% R2316 POWER_DET_1
GND 23 24 GND 50V VDD VOUT 0
3 2
L2312
1 PWR_DET_SEPARATE
PD_UHD_24V PD_20V PD_24V C2356
25 GND
R2328-*2 R2328-*1 R2328 0.1uF
+12V 1.6K 1.3K 1.5K 16V 24V-->3.48V
1% 1% 1% PD_20_24V 20V-->3.51V
12V-->3.58V
ST_3.5V-->3.5V
C2352 C2354 C2357
10uF 10uF 10uF
16V 16V 16V
’14 UHD POWER +2.5V T2 : Max 1.7A +12V
else : Max 0.7A
Main +1.5V +1.5V_DDR
L2301
+2.5V_Normal BLM18PG121SN1D
IC2302
R2312
AP2132MP-2.5TRG1 [EP]
POWER_ON/OFF2_2
1.2K
R2321
DCDC_TI
10K
IC2303-*1
C2341 C2302 C2360 TPS54327DDAR [EP]GND
1 8 R2 10uF 0.1uF
eMMC POWER 0.1uF
16V DCDC_ROHM EN VIN
THERMAL
+3.3V_NORMAL PG GND 1 8
IC2303
THERMAL
VFB VBST
R2322
BD9D320EFJ
3.9K
9
9
2 7 R1 [EP]FIN 2 7
+3.3V_NORMAL 3.3V_EMMC ADJ VREG5 SW
EN 3 6
+3.3V_NORMAL POWER_ON/OFF2_3
SS GND
3 6 R2313 EN VIN 4 5
10K 1 8
VIN VOUT 16V
THERMAL
C2327 0.1uF
L2302 0.1uF +5V_NORMAL 4 2A 5 R2303 R2305 FB BOOT C2318
9
BLM18PG121SN1D R2341 2 7
R2346
16V
10K
11K
VCTRL NC
R1 18K 3.6K L2308
ZD2302
EAN61387601 C2342 1% 1% 2.2uH
VREG SW
OPT
5V
10uF 3 6
C2305
B
C2300 10V C2303
0.1uF
+3.5V_ST
22uF 100pF NR5040T2R2N
16V 50V
10V SS GND
C2337 1.0V_DCDC_TI 4
3A 5 C2320
22uF
C2321 ZD2303
C
E
22 1.5K 22uF 2.5V
1uF C2315-*1 10V 10V
R2333 LD2300 R2342 R2307 OPT
Q2303 3300pF
22K C2313 C2315
2SC3052 50V 1uF 2200pF
1% 10V 50V
1.0V_DCDC_ROHM
Vout=0.6*(1+R1/R2) R2
Vout=0.765*(1+R1/R2)=1.516V
+12V
LG1154A
+1.0V_VDD
L2300
BLM18PG121SN1D +1.0V_VDD
+1.2V_CORE
R2368
1/16W
+5.0V normal & USB
200
C2301 C2359
1%
10uF 0.1uF R2359
DCDC_ROHM 10K
16V IC2300 R1
BD9D320EFJ R2362
1%
R2348150K 1%
ZD2300
[EP]FIN R2
R2344 16K 1%
C2338
2.5V
OPT
R2363
1/16W
39K
5.1K
2200pF C2343 C2344
R2347 16K
OPT
+24V
1%
R2304 1/16W 50V
1%
1/16W
10K 100pF 0.047uF
6.8K
R2352
POWER_ON/OFF2_3 EN VIN 5% 50V 25V
1%
1/16W
91K
1 8 R2349
R2361
16V 10K
THERMAL
0.1uF C2370
[EP]
GND2
GND1
NC_3
TRIP
R2364
4.87K
1/16W
1% FB BOOT C2314 1000pF +12V
9
C2350
VO
2 7 C2351 C2358
50V R2
1%
1/16W
27K
NR5040T2R2N 10uF
1%
RSET2
RSET1
R2360
R2302 L2307 22uF 22uF
[EP]
AGND
RLIM
COMP
R1
1%
1/16W
20K
R2365
C2347 R1 10V 10V
28
27
26
25
24
2.2uH DCDC_TI
FB
SS
11K VREG SW IC2300-*1
L2310
3 6 RF 1 23 FB 120-ohm 82pF
C2308 TPS54327DDAR [EP]GND
1%
1/16W
51K
100pF THERMAL 50V
R2353
28
27
26
25
24
23
22
50V EN VIN PGOOD GND L2322
SS GND 1 8 2 29 22
VIN_1 LX_3
3A C2340 1 21 L2311
THERMAL
1.0V_DCDC_TI 4 5 C2348
22uF VFB VBST R2356 1K EN MODE
9
22uF 2 7
POWER_ON/OFF2_4 3 21 THERMAL 4.7uH
C2312-*1 R2306 10V 16V VIN_2 LX_2
10V 2 29 20
3300pF
VREG5
3 6
SW 0.1uF
VBST IC2309 VREG
33K C2310 C2312 4 20
50V
1uF 2200pF SS GND TPS53513RVER C2309 C2311 C2329 VIN_3 3 19 LX_1 C2346
R2358
10V 50V
4 5
C2372 NC_1 5 19 VDD 10uF 10uF 0.1uF
IC2304
R2350 0.047uF +5V_NORMAL
4.7
1% C2369 R2355 50V PGND_1 BST 0 25V
1.0V_DCDC_ROHM 35V 35V 4 18
R2 2K SW_1 6 18 NC_2 OPT SN1302001(TPS65286RHDR)
PGND_2 5 17 SW_IN2
0.1uF 1/16W C2374 C2376
Vout=0.765*(1+R1/R2) SW_2 7 17 VIN_3 C2375 C2349
R2351
1/16W
16V 5% 1uF
100K
100K
R2354
10uF PGND_3 SW_IN1
1/16W
10uF 6 16 1uF
5%
5%
10V
SW_3 VIN_2 16V 16V
6A 10V
+1.2V_VDD
L2321 8 16
1uH
SW_4 9
8A 15 VIN_1
V7V 7 15 NFAULT1
/USB_OCD3
25V
1uF
C2324
10
11
12
13
14
8
9
5%
1/16W
0
10
11
12
13
14
R2343
R2357
1/10W
MODE/SYNC
EN
SW_OUT2
SW_OUT1
SW_EN2
SW_EN1
NFAULT2
ZD2304
3.3
C2361 C2353 C2366
2.5V
D2301
5%
C2373
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
OPT
22uF 22uF
30V
22uF 2200pF
50V
C2371
470pF
/USB_OCD2
50V C2335
+5V_USB_2
+5V_USB_3
USB_CTL2
USB_CTL3
R2345
10K
0.0068uF
POWER_ON/OFF1
50V
Vout=0.6*(1+R1/R2) Vout=0.6*(1+R1/R2)=5.1V
POWER UP SEQUENCE
5V/3.3V->2.5V->1.5V/1.1V->1.0V
LG1154D : 3.3V->2.5V->1.5V->1.1V
LG1154AN : 3.3V->2.5V->1.0V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-023-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Renesas MICOM
For Debug
+3.5V_ST
CAM_PWR_ON_CMD
8pF
8pF
MICOM_DEBUG
R3013 1K
R3010 10K
C3002
C3003
LOGO_LIGHT
Don’t remove R3014,
MICOM_DEBUG
MICOM_DEBUG
LOGO_LIGHT
MICOM_RESET
P3000
12507WS-04L
not making float P40
X3000
1
32.768KHz +3.5V_ST
2
MICOM_DEBUG HDMI_WAUP:HDMI_INIT R3020
3
4.7M
4 MHL_DET OPT
MICOM_RESET TP3009
5
10K
MHL_DET
R3019
R3022
10K
POWER_DET_1
MICOM_RESET_SW
GND
MICOM_RESET_22OHM
SW3000
JTP-1127WEM
2 1
22
R3023
270K
CAM_PWR_ON_CMD
OPT
C3004
P124/XT2/EXCLKS
0.47uF
0.1uF
+3.5V_ST 4 3
16V
R3021
P122/X2/EXCLK
P41/TI07/TO07
C3001
P137/INTP0
P120/ANI19
P40/TOOL0
CAM_RESET CAM_RESET
P123/XT1
C3000
P121/X1
0.1uF
MICOM_RESET_33OHM
R3021-*1 33
RESET
+3.5V_ST
REGC
VDD
VSS
R3018
10K
GP4 High/MID Power SEQUENCE
48
47
46
45
44
43
42
41
40
39
38
37
P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
I2C_SCL_MICOM
POWER_ON/OFF! P61/SDAA0 P00/TI00/TXD1
I2C_SDA_MICOM
2 35 SCART_MUTE SCART_MUTE
P62 3 34 P01/TO00/RXD1 POWER_ON/OFF2_4
MODEL1_OPT_4 POWER_ON/OFF2_4
POWER_ON/OFF2_1
P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1
WOL/WIFI_POWER_ON 5 32 KEY2
IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB 31 P21/ANI1/AVREFM
POWER_ON/OFF2_2 KEY1
P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
HDMI_CEC
P73/KR3/SO01 MICOM_LEAD_Au P23/ANI3
POWER_ON/OFF2_3 POWER_ON/OFF2_2 8 29 MODEL1_OPT_3
POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4
MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5
POWER_ON/OFF2_4 EYE_SDA SIDE_HP_MUTE
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MODEL1_OPT_2
CAM_SLEEP CAM_SLEEP
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
TP3002 MODEL1_OPT_1
SOC_RESET
13
14
15
16
17
18
19
20
21
22
23
24
EYE_Q_10P
AR3000
+3.5V_ST
3.3K
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION
MICOM MODEL OPTION
+3.5V_ST
0 1
P124/XT2/EXCLKS
MODEL_OPT_0 NON LOGO LOGO For LOGO LIGHT
P122/X2/EXCLK
P41/TI07/TO07
MICOM_LOGO_LIGHT
P137/INTP0
P120/ANI19
MICOM_OLED_MAIN
MICOM_OLED_FRC
P40/TOOL0
MICOM_H13/H14
P123/XT1
10K
10K
10K
10K
10K
22K
56K
LCD / UHD
MICOM_OLED
P121/X1
MODEL_OPT_1 OLED Need to Assign ADC port
MICOM_GED
MICOM_EPI
RESET
REGC
VDD
VSS
R3000
R3002
R3004
R3006
R3011
R3006-*2
R3006-*1
MODEL_OPT_2 NON_EPI EPI
48
47
46
45
44
43
42
41
40
39
38
37
P60/SCLA0 1 36 P140/PCLBUZ0/INTP6
MODEL_OPT_3 M14 H13 / H14
P61/SDAA0 2 35 P00/TI00/TXD1
P62 3 34 P01/TO00/RXD1
MODEL_OPT_4 P63 4 33 P130
NON_GED GED
MODEL1_OPT_0
P31/TI03/TO03/INTP4 5
IC3000-*1 32 P20/ANI0/AVREFP
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM
MODEL1_OPT_1 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
P73/KR3/SO01 MICOM_LEAD_Cu P23/ANI3
8 29
MODEL1_OPT_2 P72/KR2/SO21 P24/ANI4
9 28
MODEL1_OPT_3 P71/KR1/SI21/SDA21 10 27 P25/ANI5
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
SOC_RX
POWER_DET
AMP_MUTE
CAM_CTL
CAM_CTL
WOL/ETH_POWER_ON
EDID_WP
INV_CTL
WOL_CTL
MODEL1_OPT_4
POWER_ON/OFF1
SOC_TX
P30/INTP3/RTC1HZ/SCK11/SCL11 P27/ANI7
LED_R
12 25
13
14
15
16
17
18
19
20
21
22
23
24
MICOM_NON_LOGO_LIGHT
MODEL_OPT_1 MODEL_OPT_3
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM_NON_GED
MICOM_LCD/UHD
MICOM_NON_EPI
0.1uF
10K
10K
10K
10K
10K
C3005
MICOM_M14
M14 FHD LCD 0 0
R3001
R3003
R3007
R3012
R3005
M14 FHD OLED 1 0 For CEC
LED_R
EDID_WP
H13/H14 UHD LCD 0 1
+3.5V_ST
SOC_RESET
H13/H14 UHD OLED 1 1
R3024 R3025
27K 120K
G
D3000
BAT54_SUZHO
CEC_REMOTE HDMI_CEC
D
S
Q3000
RUE003N02
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-030-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
5V_HDMI_1
5V_HDMI_1
HDMI_3.3V 3.3V_Sil9617 Current Limit 5V_HDMI_4
ESD_HDMI +5V_NORMAL 5V_MHL
+5V_NORMAL TX0SDA
VA3216
MN864778_RESET
R3298 R3234 IC3207
33 C3233 0 R3914
HDMI_HPD_1 5V_MHL TPS2553DBV 0
P_XOUT TX0SCL L3202 L3208
X3200 BLM18PG121SN1D BLM18PG121SN1D
20pF Test1_ANA_MON1
R3265
R3266
R3267
R3268
I2C_SDA5
I2C_SCL5
27MHz TX1SDA R3235
1.8K
1.8K
1.8K
1.8K
BODY_SHIELD X-TAL_1 GND_2 IN OUT D3211
R3241
P_XOUT
47K 1 6
2.2M
1 4 Test2_ANA_MON2
P_XIN
AR3207 TX1SCL C3218 C3249 ZD3200 30V
20 33 GND_1 X-TAL_2 C3219 C3236
2 3 0.1uF 0.1uF 5V 1% OPT C3242
10K
R3243
10K
R3244
1/16W Test3_ANA_MON3 R3269 0 22uF 0.1uF GND ILIM R3289
ESD_HDMI
16V OPT
VA3203
TX0SDA 16V 16V 2 5 10uF
DDC_SDA_1_R9531 C3214 10V 100K
19 R3270 0 20K 10V
HOT_PLUG_DETECT P_AVDD11
DDC_SCL_1_R9531 P_XIN TX0SCL P_VDD33 R3295
18 EN FAULT
VDD[+5V] 20pF R3271 0 MHL_DET 3 4
P_AVDD33 TX1SDA
P_VDD11 #MHL_OCP
0
0
17 R3272 0
DDC/CEC_GND VA3204 VA3207
ESD_HDMI R3294
ESD_HDMI TX1SCL P_VDD33 +1.0V_R9531 3.3V_Sil9617
16 10K
R3258
R3230
SDA
15
SCL
14 #MHL_OCP TP3203
RESERVED
CEC_REMOTE
13
AVDD10_2
CEC D3202
[EP]GND
VDD33_2
RSVD_16
RSVD_15
RSVD_14
RSVD_13
RSVD_12
RSVD_11
RSVD_10
VDD33_1
RSVD_9
12 IP4294CZ10-TBR
R1X2P
R1X2N
R1X1P
R1X1N
R1X0P
R1X0N
R1XCP
R1XCN
TMDS_CLK-
CH1ALRCLK
SYSCLK/XI
C3203 C3209 C3210 C3211
CH0AMCLK
CH1ABCLK
TX0ARCIN
TX1ARCIN
11 0.1uF 0.1uF 0.1uF
10uF 16V
VDD11_6
CH1ASD0
VDD11_5
VDD33_4
TMDS_CLK_SHIELD 1 10 10V
16V 16V
TX0SDA
TX0SCL
TX1SDA
TX1SCL
NRESET
RX3P5V
CK-_HDMI1_R9531 P_AVDDH33
10
NC_11
NC_10
LPSA0
LPSA1
NC/XO
HSDA0
HSCL0
NIRQ1
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
TMDS_CLK+ 2 9
[EP]
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
NC_1
CEC1
CEC5
9 CK+_HDMI1_R9531 AVDD10_1 1 57 R0X2P
VSS
D2+_HDMI4_JACK
TMDS_DATA0- 3 8 RSVD_1 2 56 R0X2N
8 OPT THERMAL D2-_HDMI4_JACK
RSVD_2 R0X1P
TMDS_DATA0_SHIELD 4 7 3 77 55 D1+_HDMI4_JACK
7 D0-_HDMI1_R9531 RSVD_3 4 54 R0X1N
D1-_HDMI4_JACK
TMDS_DATA0+ 5 6
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
RSVD_4 5 53 R0X0P
D0+_HDMI1_R9531 D0+_HDMI4_JACK
6 RSVD_5 R0X0N R3255 5.1
TMDS_DATA1- VDD33_1 1 108 VDD11_4 P_AVDDH11 6 52 D0-_HDMI4_JACK
5 D3203 RSVD_6 7 51 R0XCP R3256 5.1
TMDS_DATA1_SHIELD VDD11_1 AVDDH33_4 CK+_HDMI4_JACK
IP4294CZ10-TBR 2 107 RSVD_7 8 50 R0XCN
4 THERMAL RSVD_8 VDD10_2
CK-_HDMI4_JACK
TMDS_DATA1+ P1TX2P 3 106 P0RX2P 9 49 PWRMUX_OUT_SIL9617
HDMI_1_RX2+ 145 D2+_HDMI4_MHL VDD10_1 IC3206 ARC
3 1 10 10 48 R3227 I2C_SCL2 C3213
TMDS_DATA2- D1-_HDMI1_R9531 AVDD33_1 4 105 P0RX2M TAVDD10 SPDIF_IN 10K 10uF
2 9
D2-_HDMI4_MHL 11 SIL9617 47 I2C_SDA2
2 TX2P CSCL
TMDS_DATA2_SHIELD D1+_HDMI1_R9531 HDMI TX port 1 P1TX2M 5 104 P0RX1P D2+_HDMI4_MHL 12 46
HDMI_1_RX2- D1+_HDMI4_MHL TX2N CSDA
1 3 8 D2-_HDMI4_MHL 13 45 5V_HDMI_4
TMDS_DATA2+
OPT P1TX1P 6 103 P0RX1M TX1P PWRMUX_OUT +5V_NORMAL
HDMI_1_RX1+ D1-_HDMI4_MHL D1+_HDMI4_MHL 14 44
4 7 TX1N SBVCC5 R3249 10
D2-_HDMI1_R9531 AVDD11_1 7 102 AVDD11_12 D1-_HDMI4_MHL 15 43 R3251
TX0P R0PWR5V 10
05008WR-H19C. 5 6 D0+_HDMI4_MHL 16 42
D2+_HDMI1_R9531 P1TX1M 8 101 P0RX0P TX0N CBUS_HPD0
JK3203 HDMI_1_RX1- D0+_HDMI4_MHL D0-_HDMI4_MHL 17 41 HDMI_HPD_4_MHL C3220 R3250
P1TX0P P0RX0M TXCP 18 40 DSCL0
9 100 CK+_HDMI4_MHL DDC_SCL_MHL 1uF 5.1K
HDMI1 HDMI_1_RX0+
AVDD33_2 AVDD11_11
D0-_HDMI4_MHL
CK-_HDMI4_MHL
TXCN 19 39 DSDA0
DDC_SDA_MHL 10V
10 99
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
HDMI4
P_AVDD33
HDMI_1_RX0-
P1TX0M 11
IC3200 98 P0RXCP
CK+_HDMI4_MHL
TPWR_CI2CA
RSVDL_1
INT
RESET_N
CD_SENSE
DSDA4[VGA]
DSCL4[VGA]
RSVDH_1
RSVDH_2
RSVDL_2
RSVDL_3
RSVDH_3
RSVDH_4
RSVDL_4
RSVDL_5
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
P1TXCP 12 97 P0RXCM
5V_HDMI_2 HDMI_1_CLK+ CK-_HDMI4_MHL
AVDD11_2 P1RX2P
510
R3225
13 96
P1TXCM MN864778P P1RX2M
D2+_HDMI3
SIL9617_RESET
VA3205 R3205 AR3204 HDMI_1_CLK- 14 95 D2-_HDMI3
1K R3218 33
ESD_HDMI P1EXT_SWING P1RX1P
R3217 5.1K
R3216 5.1K
4.7K 1/16W 15 94 D1+_HDMI3
C
4.7K
R3233 HDMI_INT_EDID DDC_SDA_2 NC[ANA_MON3] P1RX1M
R3210
Q3200 16 93
MMBT3904(NXP) B 1K Test3_ANA_MON3 D1-_HDMI3
BODY_SHIELD HDMI_HPD_2 DDC_SCL_2
R3202
P0TX2P 17 92 AVDD11_10
HDMI_0_RX2+ +3.3V_NORMAL
100K R3247 VA3209 VA3214
20 E
ESD_HDMI AVDD33_3 18 91 P1RX0P
4.7K ESD_HDMI D0+_HDMI3
ESD_HDMI
VA3201
HDMI_EXT_EDID P0TX2M 19 90 P1RX0M
HDMI TX port 0
19 HDMI_0_RX2- D0-_HDMI3
HOT_PLUG_DETECT R3222 47K
P0TX1P 20 89 AVDD11_9
18 SIL9617_INT R3223 47K
HDMI3
HDMI_0_RX1+
VDD[+5V] +5V_NORMAL
5V_HDMI_2 AVDD11_3 21 88 P1RXCP +3.3V_NORMAL PWRMUX_OUT_SIL9617
17 CK+_HDMI3
DDC/CEC_GND S
P0TX1M P1RXCM Q3203
R3206
16 HDMI_0_RX1- 22 87 CK-_HDMI3
R3201
SI1012CR-T1-GE3
10K
OPT
SDA G R3224 R3226 R3229 R3246
P0TX0P AVDDH33_3
1K
C3200 23 86 47K 47K 47K
MHL_DET
15 SPDIF_OUT_ARC HDMI_0_RX0+ 47K
SCL 1uF D
AVDD33_4 24 85 NC[ANA_MON1]
14
R3207
10V OPT Test1_ANA_MON1 +3.3V_NORMAL
RESERVED
3.9K
D3204 VA3208 P_AVDD33 P0TX0M CEC0
OPT
CEC_REMOTE ESD_HDMI C3201 25 84
13
CEC
RCLAMP0544T.TCT 0.1uF HDMI_0_RX0- P_AVDDH33
6.5VTO11.0V 16V P0TXCP 26 83 CEC2
12 HDMI_0_CLK+
R3200
R3209
TMDS_CLK- 1 8
R3212 5.1K
R3215 5.1K
ARC AVDD11_4 CEC3 +5V_NORMAL
R3211 47K
47K
47K
CK-_HDMI2
510
R3228
27 82
R3213 47K
11
TMDS_CLK_SHIELD 2 7 AR3209
CK+_HDMI2 P0TXCM 28 81 CEC4 47K
10 HDMI_0_CLK-
TMDS_CLK+ 3 6 1/16W
D0-_HDMI2 P0EXT_SWING 29 80 RX0SCL
9
TMDS_DATA0- 4 5
D0+_HDMI2 CH0ABCLK 30 79 RX0SDA
8
TMDS_DATA0_SHIELD
9 OPT CH0ALRCLK 31 78 RX1SCL
7 DDC_SCL_3
TMDS_DATA0+
CH0ASD3 32 77 RX1SDA
6 DDC_SDA_3
TMDS_DATA1-
CH0ASD2 33 76 RX2SCL
5 DDC_SCL_2
TMDS_DATA1_SHIELD
D3205 CH0ASD1 34 75 RX2SDA
4 DDC_SDA_2
TMDS_DATA1+ RCLAMP0544T.TCT CH0ASD0 RX3SCL
3 6.5VTO11.0V 35 74 DDC_SCL_1
TMDS_DATA2-
1 8 VDD11_2 36 73 RX3SDA
2 D1-_HDMI2 DDC_SDA_1
TMDS_DATA2_SHIELD
2 7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1 D1+_HDMI2
TMDS_DATA2+
3 6
D2-_HDMI2 S3200
4 5 RAC33437501
VDD33_2
NIRQA0
NIRQA1
TX1HPD
TX0HPD
NTEST
PVDD33
NC[ANA_MON2]
AVDDH33_1
P3RXCM
P3RXCP
AVDD11_5
P3RX0M
P3RX0P
AVDD11_6
P3RX1M
P3RX1P
P3RX2M
P3RX2P
P2RXCM
P2RXCP
AVDD11_7
P2RX0M
P2RX0P
AVDD11_8
P2RX1M
P2RX1P
P2RX2M
P2RX2P
AVDDH33_2
VDD11_3
NC[VDDQ]
RX2P5V
VDD33_3
RX1P5V
RX0P5V
05008WR-H19C. D2+_HDMI2
JK3200
9 OPT S3201
HDMI2 with ARC RAC33437501 R3297
120K
SPI_CS_R9531 X3201
AR3208 DVDD10_R9531
SPI_DI_R9531
S3202 33 SPI_DO_R9531 27MHz
RAC33437501 X-TAL_1 GND_2
CK-_HDMI1
R9531_XTAL_IN
D2+_HDMI1
CK+_HDMI1
1 4
D0+_HDMI1
D1-_HDMI1
D1+_HDMI1
D2-_HDMI1
D0-_HDMI1
GND_1 X-TAL_2
5V_HDMI_3 C3267 2 3 R9531_XTAL_OUT
S3203 AVDD33_R9531 CVDD10_R9531 DVDD10_R9531 18pF
RAC33437501 50V C3270
R3219 18pF
VA3202 1K
R3220 50V
ESD_HDMI
C 4.7K P_PVDD33 S3204
R3245 HDMI_INT_EDID RAC33437501
Q3201 B 1K
HDMI_HPD_3 +1.1V_VDD_D14 +1.1V_VDD_D14 P_AVDDH11
SDI_GPIO11
SDO_GPIO10
MMBT3904(NXP)
RSVDNC_36
RSVDNC_35
RSVDNC_34
RSVDNC_33
RSVDNC_32
RSVDNC_31
RSVDNC_30
RSVDNC_29
RSVDNC_28
BODY_SHIELD R3203
SS_GPIO8
ARCRX_TX
CVDD10_3
100K E R3248
L3205
IOVCC33
TDVDD10
TPVDD10
20 4.7K
BLM18PG121SN1D
ESD_HDMI
VA3206
HDMI_EXT_EDID
T0X2+
T0X2-
T0X1+
T0X1-
T0X0+
T0X0-
T0XC+
T0XC-
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
[EP]
19 P_VDD33 Solder Preform
HOT_PLUG_DETECT
18
C3272 C3202
C3264 5V_HDMI_3 5V_HDMI_4
Attach at R9531 thermal pad
AR3205 22uF 0.33uF
VDD[+5V] 33 4.7uF 5V_HDMI_2
10V
Test2_ANA_MON2
C3222
C3224
C3226
C3227
C3253
C3254
C3255
C3256
17 1/16W 10V
DDC/CEC_GND R3236 R3238 R3240
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
DDC_SDA_3 R3231 0 0 0
16 R3204
SDA DDC_SCL_3 10K 33 SCLK_GPIO9 1 75 XTALGND
15 SPI_CK_R9531
SCL R3237 R3239 R3242 GPIO5 XTALIN
VA3210 VA3213 47K 47K 2 74 R9531_XTAL_IN
14 ESD_HDMI ESD_HDMI 47K THERMAL
RESERVED +1.1V_VDD_D14 P_VDD11 +1.1V_VDD_D14 P_AVDD11 SD0_IN_SPDIF0_IN 3 101 73 XTALOUT
CEC_REMOTE R9531_XTAL_OUT
13
CEC GPIO6 4 72 XTALVCC33
XTAL_VCC33_R9531
CK-_HDMI1
CK+_HDMI1
D0-_HDMI1
D0+_HDMI1
D1-_HDMI1
D1+_HDMI1
D2-_HDMI1
D2+_HDMI1
L3200 L3203
CK-_HDMI2
CK+_HDMI2
D0-_HDMI2
D0+_HDMI2
D1-_HDMI2
D1+_HDMI2
D2-_HDMI2
D2+_HDMI2
12
TMDS_CLK- D3206 BLM18PG121SN1D BLM18PG121SN1D RSVDL_1 APLL10
5 71 APLL10_R9531
RCLAMP0544T.TCT
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
11
4.7uF
TMDS_CLK_SHIELD R0XC- RSVD_9 +5V_NORMAL
6.5VTO11.0V CK-_HDMI1_R9531 6 70
10 R3257 5.1
TMDS_CLK+ 1 8 R0XC+ TX_HPD0 4.7K R3284
CK-_HDMI3 C3263
CK+_HDMI1_R9531 7 69
9 4.7uF
TMDS_DATA0- 2 7 HDMI1 HDMI2 R3263 5.1
R0X0- TX_DSCL0 4.7K R3285
8
IC3202 68
C3228
C3229
C3208
C3248
C3250
C3251
C3252
C3259
C3204
CK+_HDMI3 10V
D0-_HDMI1_R9531
OPT
OPT
OPT
OPT
OPT
OPT
8 R3264 5.1
OPT
OPT
TMDS_DATA0_SHIELD 3 6 R0X0+ TX_DSDA0 1.8K R3293
D0-_HDMI3 D0+_HDMI1_R9531 9 67
7
TMDS_DATA0+ 4 5 R3273 5.1
R0X1- RSVDNC_27 1.8K R3296
D0+_HDMI3 10 66
6
5
TMDS_DATA1-
9 OPT
D1-_HDMI1_R9531
D1+_HDMI1_R9531
R3274 5.1
R3276 5.1
R0X1+ 11 R9531AN 65 RSVDNC_26 R3912 0
DDC_SDA_1
DDC_SCL_1
TMDS_DATA1_SHIELD R0X2- 12 64 RSVD_8 R3913 0
4 D3207 HDMI_3.3V P_VDD33 HDMI_3.3V P_AVDD33
D2-_HDMI1_R9531
R3277 5.1
TMDS_DATA1+
RCLAMP0544T.TCT R0X2+ 13 63 RSVD_7 4.7K R3286
3 D2+_HDMI1_R9531
R3299 5.1
TMDS_DATA2- 6.5VTO11.0V L3201 R3214 CVDD10_1 14 62 RSVD_6 4.7K R3287
2 1 8 BLM18PG121SN1D 0 CVDD10_R9531
TMDS_DATA2_SHIELD D1-_HDMI3 AVDD10_1 15 61 RSVDNC_25 AVDD33_R9531
0.33uF
0.33uF
0.33uF
0.33uF
0.33uF
2 7 DVDD10_R9531
3.3V Power Separation
0.1uF
0.1uF
4.7uF
4.7uF
1
TMDS_DATA2+ D1+_HDMI3 AVDD33_1 RSVD_5
3 6 AVDD33_R9531 16 60
D2-_HDMI3
+3.3V_NORMAL +5V_NORMAL HDMI_3.3V
RSVDNC_1 17 59 RSVD_4 4.7K R3288
4 5
C3205
C3206
C3207
C3216
C3215
C3217
C3258
C3265
C3212
05008WR-H19C. D2+_HDMI3 RSVDNC_2 18 58 RSVD_3 4.7K R3290
JK3201
R3208
9 OPT RSVDNC_3 RSVDNC_24
19 57
HDMI3
10K
RSVDNC_4 20 56 RSVD_2
RSVDNC_5 RSVD_1 4.7K R3291
G
21 55
HDMI_3.3V HDMI_3.3V
P_AVDDH33 P_PVDD33 RSVDNC_6 22 54 CSDA 4.7K R3292
I2C_SDA2
S
D
RSVDNC_7 23 53 CSCL
L3204 R3221 AO3438 I2C_SCL2
ADLC 5S 02 015
BLM18PG121SN1D 0 C3269 Q3204 RSVDNC_8 RSVDL_2
C3268 24 52 +5V_NORMAL
22uF C3235
0.33uF
100uF
C3261 0.33uF
C3230 0.33uF
C3231 0.33uF
0.1uF
0.1uF
0.1uF
4.7uF
6.3V 10V 10uF RSVDNC_9 SBVCC5V
HDMI_HPD_4_MHL 10V 25 51
ADLC 5S 02 015 OPT
VA3200
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
C3273 C3274
C3221
C3260
C3223
C3225
C3232
5V_HDMI_4 10uF 0.1uF
10V 16V
BODY_SHIELD
RSVDNC_10
RSVDNC_11
RSVDNC_12
RSVDNC_13
RSVDNC_14
RSVDNC_15
CVDD10_2
AVDD10_2
AVDD33_2
RSVDNC_16
RSVDNC_17
RSVDNC_18
RSVDNC_19
RSVDNC_20
RSVDNC_21
RSVDNC_22
RSVDNC_23
RESET_N
CI2CA_TPWR
INT
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
VCC33_OUT
20
VA3211
PWRMUX_OUT
OPT
19
HOT_PLUG_DETECT
18 AR3206
VDD[+5V]
10K
33
4.7K
17 1/16W DDC pull-up R9531_RESET
DDC/CEC_GND
DDC_SDA_MHL C3276 C3277
16 +3.3V_NORMAL 10uF 0.1uF
DDC_SDA_1_R9531
DDC_SCL_1_R9531
R3283
R3282
HDMI_HPD_1
SDA DDC_SCL_MHL S 10V 16V
15 +5V_NORMAL +5V_NORMAL Q3202
SCL VA3215 D3200 5V_HDMI_2 +5V_NORMAL +5V_NORMAL
+3.5V_ST PWRMUX_OUT CVDD10_R9531 DVDD10_R9531 AVDD33_R9531
5V_HDMI_1 5V_HDMI_3 SI1012CR-T1-GE3
14 ESD_HDMI
IP4294CZ10-TBR 5V_HDMI_4 G
RESERVED VA3212
AVDD33_R9531
CEC_REMOTE D R3252
13 ESD_HDMI 10K R3254
1 10
A1
A2
A1
A2
A1
A2
A1
A2
CEC
A1
A2
10
CK-_HDMI4_JACK 5V_HDMI_1
12 MMBD6100 MMBD6100 MMBD6100 MMBD6100 MMBD6100
TMDS_CLK- 2 9
CK+_HDMI4_JACK D3218 D3208 D3219 D3209 D3210 C3275 R3253
11 5.1K
C
C
C
C
3 8
C
TMDS_CLK_SHIELD 1uF
10 OPT
TMDS_CLK+ 4 7
D0-_HDMI4_JACK
9
5 6
AR3201
AR3200
AR3202
AR3203
TMDS_DATA0-
1/16W
1/16W
1/16W
1/16W
D0+_HDMI4_JACK +1.0V_R9531
8 CVDD10_R9531 HDMI_3.3V AVDD33_R9531
else : Max 0.7A
47K
47K
47K
47K
TMDS_DATA0_SHIELD
7
6
TMDS_DATA0+
D3201
IP4294CZ10-TBR
DDC_SDA_1_R9531 DDC_SDA_2 DDC_SDA_3 DDC_SCL_MHL
R9531 +1.0V L3210
BLM18PG121SN1D
L3215
BLM18PG121SN1D
TMDS_DATA1- +1.0V_R9531
+3.3V_NORMAL IC3204
5 1 10 DDC_SCL_1_R9531 DDC_SCL_2 DDC_SCL_3 DDC_SDA_MHL C3246 C3279 C3284 C3289 C3292 C3294 C3298 C3299 C3271
TMDS_DATA1_SHIELD D1-_HDMI4_JACK
AP2132MP-2.5TRG1 [EP] 10uF 10uF 0.1uF 0.1uF 10uF 10uF 0.1uF 0.1uF 0.1uF
4 2 9 10V 10V 16V 16V 10V 10V 16V 16V 16V
1.8K
R3280
TMDS_DATA1+ D1+_HDMI4_JACK
+3.5V_ST
3 3 8
TMDS_DATA2- OPT R3279 1 8 R2 SPI FLASH (2MBit) +3.3V_NORMAL
4 7
THERMAL
2 PG GND
R3261
TMDS_DATA2_SHIELD D2-_HDMI4_JACK
5 6 10K IC3203
10K
APLL10_R9531 XTAL_VCC33_R9531
R3281
1.2K
9
1 2 7 R1 L3213
TMDS_DATA2+ D2+_HDMI4_JACK C3243 L3207 BLM18PG121SN1D
W25X20CLSNIG
E MMBT3906(NXP) EN ADJ BLM18PG121SN1D C3239
R3262 0.1uF
10K Q3206 0.1uF
3 6
05008WR-H19C. C3290 C3293 CS VCC
B VOUT 1 8
VIN C3244 C3282 10uF 0.1uF SPI_CS_R9531
R3278
JK3202 C3240
C C 0.1uF 2A 10uF 0.1uF 10V 16V
10K
R3260 4 5 10V 16V R3275 C3281
1K 16V +5V_NORMAL 33 DO[IO1] HOLD
B 2 7
MHL_DET VCTRL NC SPI_DO_R9531
1/16W Q3205 C3262 0.1uF
EAN61387601 ZD3202
10uF
R3232
HDMI4 with MHL C3234 5% MMBT3904(NXP) E
(CD_SENCE) 2.5V WP CLK
180K
0.1uF 10V DVDD10_R9531 3 6
OPT R9531_FLASH_WP SPI_CK_R9531
16V L3211
OPT BLM18PG121SN1D
C3241 GND DIO[IO0]
R3259
4 5
120K
1uF SPI_DI_R9531
C3257 C3278 C3280 C3288 C3245 C3266
10uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF
10V 10V 16V 16V 16V 16V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES Vout=0.6*(1+R1/R2)
BSD-14Y-UD-032-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 32
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
JK3401
+3.3V_NORMAL JSTIB15 R3404
150
VIN HP_LOUT
SPDIF OUT A 1/10W JK3403
Fiber Optic
5% +3.3V_NORMAL PEJ038-3B61
VCC GND 5
B
R3406
R3400 HP_OUT 10K L 4
33 GND C HP_OUT
SPDIF_OUT R3409
VA3400 C3400 100 DETECT 3
4 HP_DET
C3402 5.5V 0.1uF
1/16W
47pF 16V
SHIELD
5% R 1
50V OPT R3405
150
ADUC 5S 02 0R5L HP_ROUT EAG61030015
1/10W
5%
VA3405
5.6V
COMPONENT 1 PHONE JACK +3.3V_NORMAL CVBS 1 PHONE JACK
OPT
+3.3V_NORMAL
C3401
18pF
R3402
10K R3403
R3407 330K
100 R3408
COMP1_DET 100
1/16W AV1_CVBS_DET
5% 1/16W
VA3401 C3403 5%
VA3402
5.6V 5.6V 0.1uF
16V
JK3400 JK3402 for audio Hum noise (L)
PEJ038-3B6111 PEJ038-3B611
5 M5_GND 5 M5_GND
4 M4 COMP1_Y 4 M4
COMP1/AV1/DVI_L_IN
3 M3_DETECT 3 M3_DETECT
VA3403 C3405
5.6V 0.01uF
1 M1 1 M1 25V
6 M6 6 M6
EAG61030017 EAG61030016
COMP1_Pb
COMP1/AV1/DVI_R_IN
VA3404
C3404
5.6V
0.01uF
25V
COMP1_Pr
AV1_CVBS_IN
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-034-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JACK HIGH/MID 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
UB85/95/UC97 only
USB NET Change: UB85/95/UC97
TX1SDA
TX1SCL
TX0SDA
TX0SCL
HDMI0_DDC_DA HDMI1_DDC_DA
+3.3V_MUX
+3.3V_NORMAL +3.3V_MUX HDMI1_DDC_CK
HDMI0_DDC_CK
+3.3V_MUX R4419
0
TI 2:1 Mux L13413
BLM18PG121SN1D
HUB_DP USB_DP2
C3301 C3300 +3.3V_MUX R4418
[EP]GND
+3.3V_MUX 0.1uF 10uF 0
[EP]GND
16V 10V C3314 C3502 C3503 HUB_DM USB_DM2
SDA_B
SCL_B
SDA_A
SCL_A
22uF IC3501 0.1uF 10uF
SDA_B
SCL_B
SDA_A
SCL_A
IC3302 10V 16V 10V
+3.3V_NORMAL
TS3DV642A0RUAR
R3505
3.3K
TS3DV642A0RUAR HDMI OUTPUT_1 DDC to URSA9
R3318
+3.3V_NORMAL R4421
3.3K
OPT OPT 0
39
40
41
42
CAMERA_DP USB_DP3
39
40
41
42
D0+A R3507 R3508
OPT OPT 38 1 VCC 10K
D0+A 10K
38 1 VCC R3502 R3503 OPT
10K HDMI1_TX2P
D0-A 37 2 EN R3504 33
10K
THERMAL
D0-A 37 2 EN OPT RXASCL_URSA9 R4420
From D13
HDMI0_TX2P HDMI1_TX2N D1+A SCL OPT
THERMAL
R3500 33 36 3 R3506 33 0
D1+A SCL
43
HDMI0_TX2N 36 3 RXBSCL_URSA9 HDMI1_TX1P D1-A SDA RXASDA_URSA9 CAMERA_DM USB_DM3
OPT 35 4
43
HDMI0_TX1P D1-A SDA R3501 33
35 4 RXBSDA_URSA9 HDMI1_TX1N D2+A D0+
34 5
HDMI OUTPUT to URSA9_1
HDMI0_TX1N HDMI_RX2+_URSA9_1_RP
D2+A 34 5 D0+ HDMI1_TX0P
HDMI0_TX0P HDMI_RX2+_URSA9_0_RP D2-A 33 6 D0- HDMI_RX2-_URSA9_1_RP
D2-A D0- HDMI1_TX0N
HDMI0_TX0N 33 6 HDMI_RX2-_URSA9_0_RP HDMI OUTPUT_0 DDC to URSA9 D3+A D1+ HDMI_RX1+_URSA9_1_RP
HDMI1_TXCP 32 7
HDMI0_TXCP D3+A 32 7 D1+ HDMI_RX1-_URSA9_1_RP
HDMI_RX1+_URSA9_0_RP D3-A 31 8 D1-
D3-A D1- HDMI1_TXCN HDMI_RX0+_URSA9_1_RP
HDMI0_TXCN 31 8 HDMI_RX1-_URSA9_0_RP NC_2 NC_1
30 9 HDMI_RX0-_URSA9_1_RP
NC_2 30 9 NC_1 HDMI_RX0+_URSA9_0_RP
D0+B D2+
HDMI OUTPUT to Splitter
HDMI_RX0-_URSA9_0_RP 29 10 HDMI_CLK+_URSA9_1_RP
HDMI_0_RX2+ D0+B 29 10 D2+
D0-B D2- HDMI_CLK-_URSA9_1_RP
From MN864778
HDMI_CLK+_URSA9_0_RP HDMI_1_RX2+ 28 11
HDMI_0_RX2- D0-B 28 11 D2-
HDMI_CLK-_URSA9_0_RP HDMI_1_RX2-
B1+B 27 12 D3+ +3.3V_NORMAL
HDMI_0_RX1+ B1+B D3+
27 12 +3.3V_NORMAL
HDMI_1_RX1+ B1-B D3-
HDMI_0_RX1- 26 13
R3509
B1-B 26 13 D3-
HDMI_0_RX0+ HDMI_1_RX1- D2+B 25 14 HPD
10K
R3319
D2+B 25 14 HPD HDMI_1_RX0+
10K
HDMI_0_RX0- D2-B 24 15 CEC
HDMI_0_CLK+ D2-B 24 15 CEC HDMI_1_RX0-
D3+B 23 16 SEL1
HDMI_0_CLK- D3+B SEL1 HDMI_1_CLK+ +1.5V_U_DDR
23 16
HDMI_1_CLK-
D3-B 22 17 SEL2 VDDC15_M0 H13 DDR VDD Decap (For EMI) VDDC15_D14 D14 DDR VDD Decap (For EMI) URSA9 DDR VDD Decap (For EMI)
D3-B 22 17 SEL2 4Layer 4Layer
4Layer
21
20
19
18
HDMI_MUX_SEL
21
20
19
18
HDMI_MUX_SEL
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
HPD_B
CEC_B
HPD_A
CEC_A
SEL2(GPIO30) Function
HPD_B
CEC_B
HPD_A
CEC_A
Low CH A (HEVC decoder) enable
C3306
C3312
C3333
C3337
C3341
C3345
C3303
C3309
C3313
C3334
C3338
C3342
C3346
C3349
C3352
C3353
C3305
C3311
C3331
C3336
C3340
C3344
C3348
C3351
High CH B (HDMI S/W) enable OPT OPT OPT OPT OPT OPT OPT OPT
VDDC15_M1
330pF
330pF
330pF
330pF
330pF
330pF
330pF
330pF
C3304
C3310
C3321
C3335
C3339
C3343
C3347
C3350
+3.3V_PS8401
Jitter Cleaning Repeater
R3323 R3325 R3327 R3329 R3346 R3348 R3350
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
PS8407_URSA9_0 PS8407_URSA0_1 OPT OPT OPT OPT OPT
4.7K
OPT
I2C_CTL_EN
DDCBUF
+1.2V_PS8401
+3.3V_PS8401
+1.2V_PS8401
ISET
+1.2V_PS8401
+3.3V_PS8401
+1.2V_PS8401
DCIN_EN
ISET
EQ/I2CADDR_0
SMD bottom for ESD_UB85 10.5T
PRE
SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85
ISET GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M2300 M2302 M2305 M2308 M2312 M2315 M2318 M2321
C3317 C3318 C3319 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225
0.1uF 0.1uF 0.1uF C3328 CFG/I2C_ADDR1
16V 16V 16V C3327 C3329
0.1uF 0.1uF 0.1uF
16V 16V 16V
SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85 SMD_GASKET_for_ESD_UB85
[EP]GND
VDDRX_2
SDA_SRC
SCL_SRC
VDD33_2
SDA_SNK
SCL_SNK
VDDTX_2
[EP]GND
VDDRX_2
SDA_SRC
SCL_SRC
VDD33_2
SDA_SNK
SCL_SNK
VDDTX_2
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
GND_2
ISET
M2301 M2303 M2306 M2311 M2313 M2316 M2319 SMD_GASKET_for_ESD_UB85
GND_2
R3324 R3326 R3328 R3330 R3347 R3349 R3351
ISET
R3354
PD
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K GASKET_8.0X6.0X9.5H
4.7K MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225
OPT
R3322
PD
M2307
1K
OPT
OPT
1K
40
39
38
37
36
35
34
33
32
31
MDS62110214
40
39
38
37
36
35
34
33
32
31
IN_D2P 1 30 OUT_D2P +5V_NORMAL
HDMI_RX2+_URSA9_0_RP HDMI_RX2+_URSA9_0 IN_D2P OUT_D2P
IN_D2N 2 29 OUT_D2N 1 30 HDMI_RX2+_URSA9_1 +5V_NORMAL
HDMI_RX2-_URSA9_0_RP THERMAL HDMI_RX2-_URSA9_0 HDMI_RX2+_URSA9_1_RP
R3353 IN_D2N 2 29 OUT_D2N
HPD_SRC 3 41 28 HPD_SNK THERMAL HDMI_RX2-_URSA9_1
HDMI_RX2-_URSA9_1_RP R3334
IN_D1P OUT_D1P HPD_SRC 3 41 28 HPD_SNK
4 27 HDMI_RX1+_URSA9_0 1K SMD_GASKET_for_ESD_UB85
HDMI_RX1+_URSA9_0_RP IN_D1P OUT_D1P
IN_D1N 5 IC3301 26 OUT_D1N 4 27 HDMI_RX1+_URSA9_1 1K
GASKET_8.0X6.0X9.5H
HDMI OUTPUT to URSA9_0
HDMI_RX1-_URSA9_0_RP HDMI_RX1-_URSA9_0 HDMI_RX1+_URSA9_1_RP IN_D1N OUT_D1N OPT OPT OPT OPT OPT
HDMI OUTPUT to URSA9_1
IN_D0P 6 PS8401A 25 OUT_D0P 5 IC3303 26 HDMI_RX1-_URSA9_1 M2314
HDMI_RX0+_URSA9_0_RP HDMI_RX0+_URSA9_0 HDMI_RX1-_URSA9_1_RP
IN_D0N OUT_D0N IN_D0P 6 PS8401A 25 OUT_D0P HDMI_RX0+_URSA9_1 GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
7 24 HDMI_RX0-_URSA9_0 HDMI_RX0+_URSA9_1_RP MDS62110214
HDMI_RX0-_URSA9_0_RP IN_D0N OUT_D0N M2304 M2309 M2310 M2317 M2320
I2C_CTL_EN 8 23 CFG/I2C_ADDR1 7 24 HDMI_RX0-_URSA9_1
I2C_CTL_EN CFG/I2C_ADDR1 HDMI_RX0-_URSA9_1_RP
IN_CKP OUT_CKP I2C_CTL_EN 8 23 CFG/I2C_ADDR1 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225
9 22 HDMI_CLK+_URSA9_0 I2C_CTL_EN CFG/I2C_ADDR1
HDMI_CLK+_URSA9_0_RP
IN_CKN 10 21 OUT_CKN HDMI_CLK+_URSA9_1_RP
IN_CKP 9 22 OUT_CKP
HDMI_CLK+_URSA9_1 9.5T Center of B/D
HDMI_CLK-_URSA9_0_RP HDMI_CLK-_URSA9_0 IN_CKN 10 21 OUT_CKN
HDMI_CLK-_URSA9_1 IC3304
11
12
13
14
15
16
17
18
19
20
HDMI_CLK-_URSA9_1_RP
+3.3V_NORMAL
11
12
13
14
15
16
17
18
19
20
+1.2V
AZ1117EH-1.2TRG1
VDD33_1
VDDRX_1
DCIN_EN/SCL_CTL
DDCBUF/SDA_CTL
GND_1
PRE
EQ/I2C_ADDR0
REXT
VDDRA
VDDTX_1
VDD33_1
VDDRX_1
DCIN_EN/SCL_CTL
DDCBUF/SDA_CTL
GND_1
PRE
EQ/I2C_ADDR0
REXT
VDDRA
VDDTX_1
IN 3 2 OUT
R3335
4.99K R3333
1% 4.99K
1% 1
R3352
1 SMD bottom for ESD_UB95 8.5T
ZD3300
ADJ/GND
2.5V
OPT
C3315 C3316 C3325 C3326
0.1uF 0.1uF C3307 C3308 10uF 10uF
16V 16V 0.1uF 0.1uF SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95
10V 10V
R3300 16V 16V
22 GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H
C3322 R3331 M2300-*1 M2302-*1 M2306-*1 M2308-*1 M2312-*1 M2314-*1 M2318-*1 M2321-*1
I2C_SCL2 0.1uF 22
16V C3332
OPT I2C_SCL2 0.1uF MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209
I2C_SDA2 OPT 16V
R3336 I2C_SDA2
22 C3320
0.1uF R3332
OPT 22 C3330
16V 0.1uF
OPT 16V
+1.2V_PS8401
+1.2V_PS8401
+1.2V_PS8401
+3.3V_PS8401
+3.3V_PS8401
+1.2V_PS8401
+1.2V_PS8401
+1.2V_PS8401
SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95 SMD_GASKET_for_ESD_UB95
DCIN_EN
DDCBUF
PRE
EQ/I2CADDR_0
+3.3V_NORMAL +3.3V_PS8401 +1.2V +1.2V_PS8401 GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H
DCIN_EN
DDCBUF
PRE
EQ/I2CADDR_0
M2301-*1 M2303-*1 M2307-*1 M2311-*1 M2313-*1 M2315-*1 M2319-*1
SMD_GASKET_for_ESD_UB95
MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209 GASKET_8.0X6.0X7.5H
C3302 L3301 L3302 M2305-*1
10uF 120-ohm C3323 120-ohm C3324
0.1uF 0.1uF MDS62110205
10V
SMD_GASKET_for_ESD_UB95
GASKET_8.0X6.0X7.5H
OPT OPT OPT OPT OPT M2316-*1
GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H
M2304-*1 M2309-*1 M2310-*1 M2317-*1 M2320-*1 MDS62110205
MDS62110209 MDS62110209 MDS62110209 MDS62110209 MDS62110209
7.5T Center of B/D
Separation of +3.3_NORMAL (For CST)
MAX A
SMD bottom for ESD_UC97 10.5T/6T/5.5T
+3.3V_NORMAL +3.3V_NORMAL
+12V
SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97
L2309 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8
L2305 IC2301 2uH M2300-*2 M2306-*2 M2308-*2 M2313-*2 M2315-*2 M2318-*2 M2321-*2
BLM18PG121SN1D BD86106EFJ [EP]
MDS62110206 MDS62110206 MDS62110206 MDS62110206 MDS62110206 MDS62110206 MDS62110206
PGND SW_2
1 8 DEV_NEOCAP
R2319
THERMAL
1.5K
1%
Placed on SMD-TOP VIN SW_1 C2319 C2323
9
2 7
10uF 100uF
C2332
AGND EN
0.0068uF 10V 6.3V C2345
C2304 C2325 C2326
3 6
R2308 47pF R1 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97
R2320
1/16W
10uF 10uF 0.1uF 50V 50V
6.8K OPT SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8 SMR-T-6-6.5-8
FB
6A COMP
30K
16V 16V 16V 4 5
1%
OPT M2305-*2 M2307-*2 M2311-*2 M2314-*2 M2316-*2 M2319-*2
MDS62110206 MDS62110206 MDS62110206 MDS62110206 MDS62110206 MDS62110206
ZD2301
5V
6T
OPT
R2323
R2311 POWER_ON/OFF2_1
10K
10K
C2328 R2
1%
0.1uF
16V
SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 OPT OPT OPT
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X5.5H SMR-T-6-6.5-8 SMR-T-6-6.5-8
M2301-*2 M2303-*2 M2304-*2 M2309-*2 M2320-*2
MDS62110225 MDS62110225 MDS62110204 MDS62110206 MDS62110206
Vout=0.8*(1+R1/R2)
SMD_GASKET_for_ESD_UC97 SMD_GASKET_for_ESD_UC97 OPT OPT
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X5.5H SMR-T-6-6.5-8
M2302-*2 M2312-*2 M2317-*2 M2310-*2
MDS62110225 MDS62110225 MDS62110204 MDS62110206
10.5T 5.5T OPT 6T OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-033_02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
UB85/95/UC97 only
Place Near Micom
+3.5V_ST LOGO_LIGHT
AR4000
33
1/16W
LOGO_LIGHT_WAFER
10K
R4000
OPT
C
B Q4000
LOGO_LIGHT MMBT3904(NXP)
LOGO_LIGHT
1K
LOGO_LIGHT
R4004 LOGO_LIGHT
R4003
E
C4000 LOGO_LIGHT
10K
0.1uF
16V
P4000
SMAW200-H18S5 L4000 120-ohm
+3.5V_WOL
BLM18PG121SN1D
C4006
C4010 C4005 22uF
3300pF 0.1uF
GND 1 2 +3.5V_WOL 10V
R4001
M_RFModule_RESET
100 BT_RESET 3 4 USB_DM WIFI_DM
RCLAMP0502BA
C4003
0.1uF NC 5 6 USB_DP
Place Near Wafer WIFI_DP
R4002 +3.5V_ST
WOL GND
D4000
WOL/WIFI_POWER_ON
100
7 8 C4016
5pF
C4015
5pF
R4010
100
C4004
0.1uF
SDA 9 10 GND OPT
50V 50V
R4008 R4009
EYE_SDA 10K 10K
R4011 R4006
EYE_SCL
100 SCL 11 12 KEY1 5% 5%
100
KEY1
+3.5V_ST R4007
R4005 GND 13 14 KEY2 100
10K KEY2
5%
IR 15 16 +3.5V_ST +3.5V_ST
IR
C4007 C4001 C4002
100pF LED_R 17 18 GND C4008
1000pF
0.1uF 0.1uF
50V 50V OPT OPT
NON_LOGO_LIGHT OPT
R4015
1.8K
LED_R
19
GND
OPT
LOGO_LIGHT C4009
R4012 0.1uF
0 16V
LOGO_LIGHT_WAFER
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-040_02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS IR / KEY 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
OCP USB1
+5V_USB_2 USB3 (2.0) +5V_USB_3
USB2 (2.0)
+5V_USB_1
MAX 1.0A MAX 1.0A
+3.3V_NORMAL
+5V_NORMAL
3AU04S-385-ZC-(LG). 3AU04S-385-ZC-(LG).
IC4400 JK4302 JK4300
BD2242G
1
1
USB DOWN STREAM
USB DOWN STREAM
R4401 VIN VOUT
4.7K 1 6
2
2
USB_DM2 USB_DM3
C4401 GND ILIM
RCLAMP0502BA
0.1uF 2 5
3
3
16V USB_DP2 USB_DP3
14K
R4402
1%
RCLAMP0502BA
EN OC
RCLAMP0502BA
RCLAMP0502BA
/USB_OCD1 3 4 C4414 C4322 ZD4300
D4300
D4302
5V C4416 C4310
4
4
22uF 10uF ZD4302
22uF 10uF 5V
10V
5
5
10V
OPT
USB_CTL1 10V 10V
OPT
R4400
10K
RCLAMP0582B
RCLAMP0582B
D4302-*1
D4300-*1
RCLAMP0582B
RCLAMP0582B
+3.3V_NORMAL
R4410
R4414
R4412
R4416
OPT 4.7K
OPT 4.7K
OPT 4.7K
OPT 4.7K
R4411
R4413
R4415
R4417
OPT 4.7K
4.7K
OPT 4.7K
OPT 4.7K
USB3.0 redriver IC EQ setting
-> EQ2: Low / DE1: Low +3.3V_NORMAL
+5V_USB_1
EN_RXD
VCC_2
NC_5
OS1
DE1
EQ1
USB1 (3.0)
18
17
16
SN65LVPE502A 15
14
13
USB3_TX0P
HOST_RX1-
19 12
NC_4
C4413
0.1uF
MAX 1.2A
USB3_TX0M ZD4301
20 11 5V
IC4402
HOST_RX1+ DEVICE_TX1- C4415 C4402
22uF 10uF JK4400
C4409
OPT
21 10 0.1uF
0.1uF GND_2 DEVICE_TX1+ 10V 10V PC2R009NJA1.
C4412 OPT
USB3_RX0P 22 9
THERMAL
HOST_TX2- GND_1
25
USB3_RX0M 23 8 VBUS
C4407 HOST_TX2+ DEVICE_RX2- 1
0.1uF 24 7
NC_6 DEVICE_RX2+
D-
1
2
3
4
5
6
USB3_DM 2
[EP]GND +3.3V_NORMAL
NC_1
NC_2
VCC_1
DE2
EQ2
NC_3
D+
USB3_DP 3
OPT
OPT
+3.3V_NORMAL GND
R4404
R4406
4
4.7K
4.7K
STDA_SSRX-
5
STDA_SSRX+
4.7K OPT
6
R4405
R4407
4.7K
GND_DRAIN
7
+3.3V_NORMAL +3.3V_NORMAL
STDA_SSTX-
8
STDA_SSTX+
9
C4400 C4403 C4404 C4405 C4406 C4408 C4410 C4411
RCLAMP0502BA
RCLAMP0502BA
1uF 1uF 0.1uF 0.01uF 1uF 1uF 0.1uF 0.01uF
RCLAMP0502BA
RCLAMP0502BA
RCLAMP0502BA
RCLAMP0502BA
10
RCLAMP0582B
RCLAMP0582B
RCLAMP0582B
RCLAMP0582B
RCLAMP0582B
RCLAMP0582B
D4400
D4402
D4401
D4400-*1
D4401-*1
D4402-*1
SHIELD
Place under DUT Near SN65LVPE502CP PIN VCC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-044-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
USB JACK
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
EU
R4801
Full Scart(18 Pin Gender) 10K CLOSE TO JUNCTION
EU
R4802
100
SC_DET
EU 1/16W
C4804 5%
VA4801
5.6V 0.1uF
EU
SC_CVBS_IN
VA4807
SHIELD 5.5V
EU
19
AV_DET 75 R4800
18
COM_GND EU
VA4808 DTV/MNT_V_OUT
17 5.5V
SYNC_IN OPT
16
SYNC_OUT
15
SYNC_GND
14
RGB_IO
13 SC_FB
R_OUT VA4802
12 5.6V
R_GND EU
11
G_OUT
10
G_GND
9 SC_R
ID
8 VA4803
B_OUT
5.5V
7
AUDIO_L_IN EU
6
B_GND
5 SC_G
AUDIO_GND
4 VA4804
AUDIO_L_OUT
5.5V
3
AUDIO_R_IN EU
2
AUDIO_R_OUT
1
SC_B
VA4805
5.5V
DA1R018H91E
EU
JK4800
EU
SC_ID
SC_L_IN
VA4800 VA4809
5.6V
20V EU
EU
SC_R_IN
VA4806
5.6V
EU
BLM18PG121SN1D
L4800
DTV/MNT_L_OUT
EU EU EU
C4800 C4802
1000pF 4700pF
50V
BLM18PG121SN1D
L4801
DTV/MNT_R_OUT
EU
EU EU C4803
C4801 4700pF
1000pF
50V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-048-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART GENDER
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
LAN_JACK_POWER
C5100 C5101 C5102 C5103
0.1uF 0.01uF 0.1uF 0.01uF
16V 50V 16V 50V
JK5100
BS-R570098
LAN_UDE
P1[CT]
1
P2[TD+]
2
EPHY_TDP
P3[TD-]
3
EPHY_TDN
P4[RD+]
4
EPHY_RDP
P5[RD-]
5
EPHY_RDN
P6[CT] VA5100 VA5101 VA5102 VA5103
6
5.5V 5.5V 5.5V 5.5V
P7
7
P8
8
9
9 EMI
R5100
P10[GND] 0
10
P11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
12
SHIELD
JK5100-*1
TLA-6T764
LAN_TDK
R1
1
R2
2
R3
3
R4
4
R5
5
R6
6
R7
7
R8
8
R9
9
R10[GND]
10
R11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
12
SHIELD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-051-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LAN_VERTICAL 2012.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 51
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
+3.5V_WOL
3.3K
R5215
EPHY_ACTIVITY
ET_RXER
R5217 3.3K
LAN_JACK_POWER
Place this cap. near IC
+3.5V_WOL
C5208
ET_COL/SNI 0.1uF
ZD5201
C5200 C5201 C5203 16V
5V
4.7uF 0.1uF 0.1uF
16V 16V
OPT
10V
EPHY_ACTIVITY
EPHY_CRS_DV
Place 0.1uF close to each power pins
ET_COL/SNI
ET_RXER
XTAL_1
GND_1
C5206
8pF +3.5V_WOL
50V
1M R5202
R5218
2
1
25MHz
X5200
R5210
0
OPT
3
4
XTAL_2
GND_2
33
+3.5V_WOL
LED1/PHYAD[1]
Place this cap. near IC C5207
CRS/CRS_DV
DVDD10OUT
RXER/FXEN
8pF
AVDD33_2
CKXTAL2
CKXTAL1
50V
R5212
1/16W
R5219
1/16W
R5205
[EP]
3.3K
1.5K
C5205
COL
10K
Place this Res. near IC
1%
5%
0.1uF
16V
32
31
30
29
28
27
26
25
R5204
2.49K 1% WOL/ETH_POWER_ON
RSET 1 24 LED0/PHYAD[0]/PMEB
THERMAL
AVDD10OUT 2 33 23 MDIO EPHY_MDIO
Route Single 50 Ohm, Differential 100 Ohm MDI+[0] MDC
3 22 EPHY_MDC
EPHY_RDP
MDI-[0] IC5200 PHYRSTB
4 21 /RST_PHY (from SOC)
EPHY_RDN RTL8201F-VB-CG
MDI+[1] 5 20 TXEN
EPHY_TDP EPHY_EN
+3.5V_WOL MDI-[1] 6 19 TXD[3]
EPHY_TDN C5212
AVDD33_1 TXD[2] 0.1uF
7 18
OPT
R5203 RXDV TXD[1]
8 17 EPHY_TXD1
3.3K
10
11
12
13
14
15
16
9
RXD[0]
RXD[1]
33 RXD[2]/INTB
RXD[3]/CLK_CTL
RXC
DVDD33
TXC
TXD[0]
+3.5V_WOL
+3.5V_WOL
AR5200
R5200
3.3K
C5211
OPT
0.1uF
C5209
R5201
16V
33
R5209
33pF
51
EPHY_TXD0
C5202
3.3K
EPHY_RXD1
EPHY_RXD0
EPHY_INT
Place near IC
5pF
R5208
WOL POWER ENABLE CONTROL
EPHY_REFCLK
+3.5V_WOL
+3.5V_ST IC5201
AP2191WG-7
IN OUT
5 1
C5204
0.1uF GND
2
WOL_CTL R5211 33 EN FLG
4 3
R5213
10K
OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-052-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETHERNET
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+12V
EU
AUD_OUT >> EU/CHINA_HOTEL_OPT
IC6000 L6000
AZ4580MTR-E1
EU
EU
2.2K R6000 OUT1 8 VCC C6004
DTV/MNT_L_OUT 1
EU
C6000 OPT
0.1uF
50V R6011
EU
C6008
[SCART AUDIO MUTE]
OPT R6002 EU IN1- OUT2 SIGN60000003 2.2K
1uF 33K R6004 2 7
25V C6002 470K DTV/MNT_R_OUT
EU 6800pF
33pF C6003
IN1+
3
EU 6 IN2- R6008
EU
33K
OPT
R6010
OPT
C6007
1uF DTV/MNT_L_OUT
EU 25V
470K
6800pF
EU
VEE 5 IN2+ C
4 C6005 EU R6013
33pF Q6000 B 1K
SCART_AMP_L_FB MMBT3904(NXP)
EU_SCART_MUTE_ISAHAYA
SCART_AMP_R_FB E EU Q6002
RT1P141C-T112
SCART_MUTE
C
E
B
SCART_Lout
SCART_Rout
DTV/MNT_R_OUT
PDTA114ET
Q6002-*1
EU
C
E
C
R6014
Q6001 B 1K
MMBT3904(NXP)
B
E EU EU_SCART_MUTE_NXP
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-060-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS SCART AUDIO AMP 2012.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 60
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
HP_OUT_H13 HP_OUT_H13
C6104-*1 C6109-*1
EARPHONE AMP 18pF
18pF
IC6100
TPA6138A2
HP_OUT_MTK +INR +INL HP_OUT_MTK
C6104 1 14 C6109
HP_OUT
C6100 180pF HP_OUT HP_OUT 180pF HP_OUT C6101
1uF R6100 R6106 R6104 R6101 1uF
-INR -INL HP_OUT
HP_OUT 10K
10V 43K HP_OUT 2 13
43K 10K 10V
HP_OUT
HP_ROUT_MAIN HP_LOUT_MAIN
R6103 1% C6108 C6106 1% R6102
33K 10pF OUTR OUTL 10pF 33K
HP_OUT_MTK 50V 3 12 50V HP_OUT_MTK HP_OUT_H13
HP_OUT_H13 HP_LOUT_AMP R6102-*1
R6103-*1 HP_ROUT_AMP 43K
+3.3V_NORMAL GND_1 UVP
43K 4 11 +3.3V_NORMAL
1%
1%
HP_OUT
MUTE GND_2
4.7K
HP_OUT
5 10 L6100
R6105
120-ohm
SIDE_HP_MUTE VSS VDD BLM18PG121SN1D
6 9
HP_OUT HP_OUT
HP_OUT
C6105 C6107
C6102 CN CP 1uF 0.1uF
1uF 7 8
10V 16V
10V
C6103
1uF
10V
HP_OUT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-061-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. 2013.12.17
HEADPHONE AMP
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 61
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
B-CAS (SMART CARD) INTERFACE
+3.3V_NORMAL INT CMDVCC : STATUS
+3.3V_NORMAL ---------------------------------
HIGH HIGH CARD PRESENT
LOW HIGH CARD not PRESENT
SIGN63000018
IC6300
TDA8024TT
2.7K
2.7K
R6301
R6303
R6305
JAPAN
JAPAN
CLKDIV1 CLKDIV2 : F_CRD_CLK
OPT
-----------------------------
1 0 CLKIN CLKDIV1 AUX2UC
1 28
JAPAN
JAPAN
JAPAN
R6317
R6318
R6315
R6319
R6316
OPT
OPT
1.2K
1.2K
1.2K
1.2K
1.2K
CLKDIV2 AUX1UC
2 27
JAPAN
5V/3V I/OUC JAPAN
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1] R6300 22 3 26 R6307 22 SMARTCARD_DATA/SD_EMMC_CLK
2.7K
R6302
R6304
R6306
JAPAN
OPT
OPT
PGND XTAL2 JAPAN
+5V_NORMAL 4 25 R6308 22 SMARTCARD_CLK/SD_EMMC_DATA[0]
S2 XTAL1 JAPAN
JAPAN 5 24 R6309 22 SMARTCARD_DET/SD_EMMC_DATA[3]
L6300
BLM18PG121SN1D VDDP OFF JAPAN
JAPAN 6 23 R6310 22 SMARTCARD_RST/SD_EMMC_DATA[2]
JAPAN
JAPAN C6301 C6303
C6300 0.1uF S1 GND JAPAN
10uF
0.1uF 10V 16V 7 22 R6311 22 SMARTCARD_VCC/SD_EMMC_CMD
16V L6301 JAPAN
+3.3V_NORMAL
JAPAN
VUP VDD BLM18PG121SN1D
8 21
JAPAN
JAPAN JAPAN
C6302 PRES RSTIN C6305 C6306
0.1uF 9 20 0.1uF 0.1uF
16V 16V 16V
B-CAS SLOT
PRES CMDVCC
10 19
P6300
I/O PORADJ 10057542-1311FLF(B CAS Slot)
11 18
AUX2 VCC JAPAN VCC
12 17 C1
C6307
0.33uF
AUX1 RST 16V RST
13 16 C2
CGND CLK Place CLK C3 far from C2,C7,C4 and C8 CLK
14 15 C3
JAPAN
C6304 RESERVED_1
0.1uF C4
16V
GND
C5
VPP JAPAN
C6
JAPAN
R6313
75 I/O
C7
75 ohm in I/O is for short circuit Protection
RESERVED
C8
SW1
S1
+3.3V_NORMAL
JAPAN
JAPAN
10K
R6312
R6314
1K SW2
S2
ZD6300 ZD6301
JAPAN
JAPAN
5V 5V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-063-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JAPAN_BCAS 63
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
Signal to Signal Width = 12mils
+3.3V_TU Ground Width >= 24mils
L6500
BLM18PG121SN1D close to TUNER
1 +3.3V_LNA_TU C6519
0.1uF R6504 1K
TU_M/W_TW/BR/CO/CN TU_M/W_TW/BR/CO/CN TU_M/W_TW/BR/CO/CN
2 RF_SWITCH_CTL_TU RF_SWITCH_CTL
C6502 R6502
0.1uF 10K
TU_ALL_IntDemod R6503 +3.3V_NORMAL
BLM18PG121SN1D
IF_AGC_TU 100 IF_AGC +3.3V_TU
3 C6500 TU_ALL_IntDemod
0.1uF
close to Tuner
L6502
16V +3.3V_TU
TU_Non_BR/TW
R6515-*1
BLM18PG121SN1D
TU_ALL_2178B
R6515 33
I2C_SCL6_TU I2C_SCL6 200
4 C6503
15pF TU_Non_BR/TW TU_H/W/W_KR/US/BR/TW
L6504
50V R6510 33 TU_ALL_2178B C6516
C6506 C6515
5 I2C_SDA6_TU I2C_SDA6 R6510-*1 0.1uF
C6501 OPT 200 1608 perallel 22uF 0.1uF
16V 10V 16V
15pF because of derating
50V TU_H/W/W_KR/US/BR/TW 85C
OPT
TU_ALL_IntDemod R6505 R6506 TU_ALL_2178B
TU_ALL_2178B 200 200
R6516 10
6 IF_P_TU IF_P
TU_ALL_IntDemod
should be guarded by ground,Match GND VIA TU_CVBS
R6517 10
7 IF_N_TU IF_N
E
8 TU_CVBS_TU TU_ALL_2178B
TU_ALL_2178B B Q6500
TU_SIF MMBT3906(NXP)
R6518 0 C
9 TU_SIF_TU
R6518-*1
TU_M/W
150 L6501 +3.3V_TU
BLM18PG121SN1D T2 : Max 1.7A
TU_H/M_KR/US/TW/BR/EU
else : Max 0.7A
11 +3.3V_TUNER
C6509
0.1uF
FE_DEMOD1_TS_ERROR FE_DEMOD1_TS_ERROR TU_M/W TU_M/W
12
+3.3V_NORMAL IC6500 Demod_Core
TU_M/W_1.2V
R6514TU_M 0 AP2132MP-2.5TRG1 [EP]
TU_M/W_1.1V TU_M/W_1.1V
R6509-*1 R6508-*1
14 FE_DEMOD1_1_TS_CLK FE_DEMOD1_TS_CLK
R6508
1/16W
10K
R6512 0
1/16W
1%
FE_DEMOD1_2_TS_CLK TU_M/W R2
1 8
18K
FE_DEMOD1_TS_SYNC TU_W FE_DEMOD1_TS_SYNC
15
1%
TU_M/W C6513
TU_M/W_1.2V
THERMAL
0.1uF PG GND
C6517
R6509
1/16W
0.1uF
9
2 7 R1
1/16W
16 FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL
10K
16V TU_M/W
1%
ADJ
16K
R6507 EN
1%
10K
R6513 0 3 6
17 FE_DEMOD1_1_TS_DATA[0] TU_M // W_AJ
FE_DEMOD1_TS_DATA[0]
VOUT
R6521 0 VIN
FE_DEMOD1_2_TS_DATA[0]
R6511 0
TU_W_Non_AJ
18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[1-7]
+5V_NORMAL 4 2A 5
FE_DEMOD1_TS_DATA[7] VCTRL NC
TU_W_AJ EAN61387601
FE_DEMOD1_TS_DATA[2] TU_M/W
19 FE_DEMOD1_TS_DATA[1]
C6514
FE_DEMOD1_TS_DATA[2] 10uF
FE_DEMOD1_TS_DATA[3] TU_M/W 10V
20 FE_DEMOD1_TS_DATA[3]
C6508
1uF
FE_DEMOD1_TS_DATA[4]
21 FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
Global F/E Option Name
1. TU
22 FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[7]
Vout=0.6*(1+R1/R2)
2. Tuner Name = TDS’S’,TDS’Q’...
23 FE_DEMOD1_TS_DATA[6]
3. Country Name = T,T2,S2,KR,US,BR ...
Example of Option name 24 FE_DEMOD1_TS_DATA[7]
TU_Q_T2 = apply TDSQ type tuner and T2 country R6500
/TU_RESET1
100
TU_M/W = apply TDSM&TDSW Type Tuner 25 /TU_RESET1_TU
L6503 +3.3V_TU TU_M/W_NonBr
C6505
BLM18PG121SN1D 16V
13’ Tuner Type for Global 26 +3.3V_DEMOD_TU 0.1uF
TU_M/W
TDS’S’-G501D : T/C Half NIM Horizontal Type R6520 C6510 TU_M/W TU_M/W_NonBr
TDS’Q’-G501D : T/C/S2 Combo Horizontal type 33 0.1uF
27 I2C_SCL4_TU TU_M/W
TDS’Q’-G601D : T2/C/S2 Combo Horizontal Type L6505 Demod_Core
BLM18PG121SN1D C6512
TDS’Q’-G651D : T2/C/S2 Combo Vertical Type 15pF
I2C_SCL4
TDS’M’-C601D : China NIM with Isolater Type 28 D_Demod_Core 50V
OPT
TU_M/W
TDS’W’-J551F : Japan Dual NIM C6504
0.1uF
TDS’W’-B651F : Brazil 2Tuner 29 LNB_TX LNB_TX
TU_M/W TU_M/W
TDS’W’-A651F : Taiwan 2Tuner R6519
TDS’W’-K651F : Colombia DVB-T2 2Tuner 33
30 I2C_SDA4_TU
C6511
15pF I2C_SDA4
LNB_OUT 50V
31 LNB_OUT OPT
C6520 C6521
0.1uF 18pF
34 FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_ERROR LNB
LNB
36 FE_DEMOD2_TS_SYNC FE_DEMOD2_TS_SYNC
R6522 0
37 FE_DEMOD2_TS_CLK_TU FE_DEMOD2_TS_CLK
L6506 +2.5V_Normal
BLM18PG121SN1D
38 +2.5V_DEMOD
C6518 TU_JP
0.1uF
39 FE_DEMOD2_TS_VAL FE_DEMOD2_TS_VAL
TU_JP
40 FE_DEMOD2_TS_DATA FE_DEMOD2_TS_DATA
R6501
100 /TU_RESET2
45 /TU_RESET2_TU
C6507 TU_W
16V
0.1uF
TU_W
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-065-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TUNER 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 65
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
TDJW_A151D TU_TDJW TDJM_G251D TDJM_H151F TDJH_H251F
TU6800 TU6700 TU6707 TU6701 TU6703
TDJW-A151D TDJW-J251F TDJM-G251D TDJM-H151F TDJH-H251F
B1[+3.3V] B1[+3.3V] B1[+3.3V] B1[+3.3V] B1[+3.3V]
1 1 1 1 1 +3.3V_LNA_TU
NC_1 NC_1 NC_1 NC_1 NC
2 2 2 2 2 RF_SWITCH_CTL_TU
NC_2 NC_2 NC_2 M_DIF_AGC DIF_AGC
3 3 3 3 3 IF_AGC_TU
SCL_RF SCL_RF SCL_RF SCL_RF SCL
4 4 4 4 4 I2C_SCL6_TU
SDA_RF SDA_RF SDA_RF SDA_RF SDA
5 5 5 5 5 I2C_SDA6_TU
NC_3 NC_3 NC_3 M_DIF[P] DIF[P]
6 6 6 6 6 IF_P_TU
NC_4 NC_4 NC_4 M_DIF[N] DIF[N]
7 7 7 7 7 IF_N_TU
M_SIF NC_5 SIF S_SIF SIF
8 8 8 8 8 TU_SIF_TU
M_CVBS NC_6 CVBS S_CVBS CVBS
9 9 9 9 9 TU_CVBS_TU
NC_5 NC_7 NC_5 NC_2
10 10 10 10
B2[+3.3V] B2[+3.3V] B2[+3.3V] B2[+3.3V] A1 B1
11 11 11 11 +3.3V_TUNER A1 B1
NC_6 NC_8 ERROR S_ERROR 47
12 12 12 12 FE_DEMOD1_TS_ERROR
GROUND_1 GND_1 GND_1 GND_1
TU_GND_A
13 13 13 13 SHIELD
TU_GND_B
MCLK S_MCLK
14 14 FE_DEMOD1_1_TS_CLK
SYNC S_SYNC
15 15 FE_DEMOD1_TS_SYNC
VAILD S_VAILD
16 16 FE_DEMOD1_TS_VAL
D0 S_DATA
17 17 FE_DEMOD1_1_TS_DATA[0]
D1 NC_3
18 18 FE_DEMOD1_TS_DATA[1]
D2 NC_4
19 19 FE_DEMOD1_TS_DATA[2]
D3 NC_5
20 20 FE_DEMOD1_TS_DATA[3]
D4 NC_6
21 21 FE_DEMOD1_TS_DATA[4]
D5 NC_7
22 22 FE_DEMOD1_TS_DATA[5]
D6 NC_8
23 23 FE_DEMOD1_TS_DATA[6]
D7 NC_9
24 24 FE_DEMOD1_TS_DATA[7]
M_RESET_DEMOD M_RESET_DEMOD RESET_DEMOD S_RESET_DEMOD
25 25 25 25 /TU_RESET1_TU
B3[+3.3V] B3[+3.3V] B3[+3.3V] B3[+3.3V]
26 26 26 26 +3.3V_DEMOD_TU
SCL_DEMOD SCL_DEMOD SCL_DEMOD SCL_DEMOD
27 27 27 27 I2C_SCL4_TU
B4[+1.2V] B4[+1.2V] B4[+1.1V] B4[+1.1V]
28 28 28 28 D_Demod_Core
NC_7 NC_9 F22_OUTPUT NC_10
29 29 29 29 LNB_TX
SDA_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD
30 30 30 30 I2C_SDA4_TU
LNB LNB
31 31 LNB_OUT
GND_2 GND_2 A1 B1
32 32 A1 B1
NC_8 NC_10 47
33 33
M_ERROR M_ERROR A1 B1
TU_GND_A
34 34 A1 B1 SHIELD
TU_GND_B
FE_DEMOD2_TS_ERROR
GROUND_2 GND_3 47
35 35
TU6800-*2 TU6800-*3
M_SYNC M_SYNC TU6800-*1
TU_GND_A
TDJW-K151F TDJW-H151F TDJW-B251F
36 36 SHIELD
TU_GND_B
FE_DEMOD2_TS_SYNC TDJW_K151F DEV_KR_T2 TDJW-B251F
B1[+3.3V] B1[+3.3V] B1[+3.3V]
1 1
M_MCLK M_MCLK 1
SWITCH_CTR 2
NC_1
2
RF_S/W_CTL
37 37 FE_DEMOD2_TS_CLK_TU
2
3
NC_1 3
M_DIF_AGC
3
NC_1
SCL_RF SCL_RF SCL_RF
4 4
NC_9 B5[+2.5V] 4
SDA_RF 5
SDA_RF
5
SDA_RF
38 38 +2.5V_DEMOD
5
6
NC_2 6
M_DIF[P]
6
NC_2
NC_3 M_DIF[N] NC_3
7 7
M_VALID M_VALID 7
TU_GND_A
TU_GND_B
S_SIF S_SIF M_SIF
8 8
39 39 FE_DEMOD2_TS_VAL
8
9
S_CVBS 9
S_CVBS
9
M_CVBS
NC_4 NC_2 NC_4
10 10
M_DATA M_DATA 10
B2[+3.3V] 11
B2[+3.3V]
11
B2[+3.3V]
40 40 FE_DEMOD2_TS_DATA
11
12
NC_5 12
NC_3
12
NC_5
TU6707-*1 GND_1 13
GND_1
13
GND_1
S_ERROR S_ERROR TDJM-G251D
13
41 41 FE_DEMOD1_TS_ERROR TDJM-G251D
B1[+3.3V]
TU6701-*1
1 TDJM-C351D
S_SYNC S_SYNC 2
NC_1
TDJM_C351D
42 42 NC_2 B1[+3.3V]
0
0
3 1
FE_DEMOD1_TS_SYNC C6700 C6701 C6703 C6705 SCL_RF RF_SW_CTL
4 2
1000pF 1000pF 1000pF 1000pF
R6703
S_MCLK S_MCLK SDA_RF NC_1
R6702
5 3
TU_GND_B
630V 630V 630V 630V
43 43 FE_DEMOD1_2_TS_CLK TU_M/W_EU TU_M/W_EU 6
NC_3
NC_4
4
SCL_RF
SDA_RF
7 5
S_VALID S_VALID 8
SIF
6
NC_2
TU_M/W_CN/HK/TW/BR/EU_1000pF
TU_H/M/W_KR/US/CN/JP/TW/BR/AJ_1000pF
44 44 CVBS NC_3
TU_H/M_KR/US/JP/EU
9 7
TU_H/M_KR/US/JP/EU
FE_DEMOD1_TS_VAL NC_5 SIF
10 8
C6700-*1
TU_M/W_EU
RESET1_DEMOD M_RESET_DEMOD
C6701-*1 C6703-*1
M_RESET_DEMOD 25 25
S_RESET_DEMOD S_RESET_DEMOD 3300pF
11
B2[+3.3V]
9
CVBS 25
B3[+3.3V] 26
B3[+3.3V]
26
B3[+3.3V]
45 45 3300pF 0.022uF ERROR NC_4 26
1000pF
12 10 SCL_DEMOD SCL_DEMOD
/TU_RESET2_TU SCL_DEMOD 27 27
C6704
630V 630V 630V 13
GND_1
11
NC_5 27
630V
B4[+1.2V] B4[+1.1V] B4[+1.1V]
28 28
TU_M/W_CN/HK/TW/BR/EU_3300pF
S_DATA_7 S_DATA TU_W_AJ MCLK ERROR 28
0 R6701
TU_H/M/W_KR/US/CN/JP/TW/BR/AJ_3300pF
14 12 NC_4 NC_6
NC_6 29 29
46 46 FE_DEMOD1_2_TS_DATA[0]
15
SYNC
VAILD
13
GND_1
MCLK
29
30
SDA_DEMOD 30
SDA_DEMOD
30
SDA_DEMOD
16 14
S_DATA_0 17
D0
15
SYNC
47 FE_DEMOD1_1_TS_DATA[0]
18
D1
D2
16
VAILD
D0 33
NC_7 33
NC_5
33
NC_7
19 17 NC_6 M_ERROR
M_ERROR 34 34
S_DATA_1 A1 B1 GND_3
20
D3
18
D1 34
GND_2 35
GND_2
35
GND_2
48 FE_DEMOD1_TS_DATA[1] A1 B1 21
D4
D5
19
D2
D3
35
36
M_SYNC 36
NC_7
36
M_SYNC
22 20 NC_8 M_MCLK
M_MCLK 37 37
S_DATA_2 47 23
D6
21
D4 37
NC_8 38
NC_9
38
NC_8
49 FE_DEMOD1_TS_DATA[2]
24
D7
RESET_DEMOD
22
D5
D6
38
39
M_VALID 39
NC_10
39
M_VALID
25 23 NC_11 M_DATA
TU_GND_A
TU_GND_B
M_DATA 40 40
S_DATA_3 26
B3[+3.3V]
24
D7 40
S_ERROR 41
ERROR
41
S_ERROR
50 FE_DEMOD1_TS_DATA[3] SHIELD 27
SCL_DEMOD
B4[+1.1V]
25
RESET_DEMOD
B2[+3.3V]
41
42
S_SYNC 42
SYNC
42
S_SYNC
28 26 MCLK S_MCLK
S_MCLK 43 43
S_DATA_4 29
F22_OUTPUT
27
SCL_DEMOD 43
S_VALID 44
VALID
44
S_VALID
51 FE_DEMOD1_TS_DATA[4] GND_3 30
SDA_DEMOD
LNB
28
B3[+1.1V]
NC_6
44
45
S_RESET_DEMOD 45
RESET2_DEMOD
45
S_RESET_DEMOD
31 29 DATA S_DATA
S_DATA
TU_GND_A
46 46
S_DATA_5 32
GND_2
30
SDA_DEMOD 46
52 FE_DEMOD1_TS_DATA[5]
for tuner EMS (S4) testing A1 B1 A1
A1 B1
B1 A1
A1 B1
B1
A1 B1 A1 B1 A1 B1
A1 B1 A1 B1 47 47
47
S_DATA_6 47 47
SHIELD SHIELD
53 FE_DEMOD1_TS_DATA[6]
SHIELD SHIELD
SHIELD
A1 B1
A1 B1
0
0
0
0
0
0
0
0
0
0
54
OPTR6700
OPTR6704
OPTR6705
OPTR6706
R6707
OPTR6708
OPTR6709
OPTR6710
OPTR6711
OPTR6712
TU_GND_A
OPT
TU_GND_B
SHIELD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-067-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TU_SYMBOL 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
RS-232C Control INTERFACE JK6801
SPG13-SD-0402
5
9
4
R6820 8
100
+3.5V_ST 3
7
R6821
100
2
6
1
C6812 OPT 10
0.33uF ZD6802 OPT
ADUC 20S 02 010L ZD6803
20V ADUC 20S 02 010L
OPT 20V
C6813
IC6801 0.1uF
MAX3232CDR
C1+ VCC
1 16
C6808
0.1uF V+ GND
2 15
C6809
0.1uF C1- DOUT1
3 14
C2+ RIN1
4 13
C6810
0.1uF C2- ROUT1
5 12
SOC_RX
V- DIN1
6 11
SOC_TX
C6811
0.1uF DOUT2 DIN2
7 10
RIN2 ROUT2
8 9
EAN41348201
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-068-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C 68
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DVB-S2 LNB Part Allegro
(Option:LNB) Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A
3A
+12V
2A
D6904-*1
Max 1.3A
40V
LNB_SX34
D6902
3.5A
LNB D6904
30V 40V
LNB
15uH
SP-7850_15
L6900
LNB_SMAB34
C6909
10uF
C6903 C6905 C6906 C6907 25V
0.01uF 10uF 10uF 10uF LNB
50V 25V 25V 25V
LNB LNB LNB LNB
C6908 0.1uF
close to Boost pin(#1) A_GND
A_GND
LNB
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND
BOOST
GNDLX
R6904
NC_3
NC_2
C6910 0
A_GND
LX
0.1uF
50V
20
19
18
17
16
LNB
D6901 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT 21
30V LNB
D6903 NC_1 3 13 VREG
LNB C6904
0.1uF LNB_SMAB34 IC6900 R6903
C6900 C6901 R6900 TDI A8303SESTR-T ISET 39K
LNB 50V 40V 4 12
18pF 33pF 2.2K
D6900 1W LNB 1/16W
LNB LNB C6902 TDO 5 11 TCAP C6912
LNB LNB 0.22uF 1%
LNB 25V D6903-*1
10
LNB
LNB_SX34
6
7
8
9
0.1uF
40V
IRQ
SCL
SDA
ADD
TONECTRL
0.22uF
Close to Tuner A_GND
A_GND
Surge protectioin
LNB
C6911
R6901 33
R6902 33
LNB
LNB
I2C_SCL4
I2C_SDA4
LNB_TX
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-069-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
LNB 2013.12.17
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
69
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC8100-*4
IC8100-*1 IC8100-*2 IC8100-*3
THGBM5G7A2JBAIR
THGBM5G5A1JBAIR H26M21001ECR KLM2G1HE3F-B001
A3 C8
A3 C8 A3 C8 A3 C8 DAT0 NC_23
DAT0 NC_23 DAT0 NC_25 DAT0 NC_25 A4 C9
A4 C9 A4 C9 A4 C9 DAT1 NC_24
eMMC I/F A5
B2
DAT1
DAT2
DAT3
NC_24
NC_25
NC_26
C10
C11
A5
B2
DAT1
DAT2
DAT3
NC_26
NC_27
NC_28
C10
C11
A5
B2
DAT1
DAT2
DAT3
NC_26
NC_27
NC_28
C10
C11
A5
B2
B3
DAT2
DAT3
NC_25
NC_26
C10
C11
C12
B3 C12 B3 C12 B3 C12 DAT4 NC_27
DAT4 NC_27 DAT4 NC_29 DAT4 NC_29 B4 C13
EMMC DATA LINE 47K PULL/UP 3.3V_EMMC B4 C13 B4 C13 B4 C13 DAT5 NC_28
DAT5 NC_28 DAT5 NC_30 DAT5 NC_30 B5 C14
B5 C14 B5 C14 B5 C14 DAT6 NC_29
47K
47K
47K
47K
47K
47K
47K
47K
DAT6 NC_29 DAT6 NC_31 DAT6 NC_31 B6 D1
B6 D1 B6 D1 B6 D1 DAT7 NC_30
DAT7 NC_30 DAT7 NC_32 DAT7 NC_32 D2
D2 D2 D2 NC_31
NC_31 NC_33 NC_33 D3
D3 D3 D3 NC_32
R8107-*1
R8100-*1
R8101-*1
R8102-*1
R8103-*1
R8104-*1
R8105-*1
R8106-*1
NC_32 NC_34 NC_34 M6 D4
R8117
R8116
10K
10K
10K
10K
10K
10K
10K
10K
EMMC DATA LINE M6 D4 M6 D4 M6 D4 CLK NC_33
CLK NC_33 CLK NC_35 CLK NC_35 M5 D12
10K
10K
10K PULL/UP M5 D12 M5 D12 M5 D12 CMD NC_34
FOR M13 CMD NC_34 CMD NC_36 CMD NC_36 D13
R8103
R8100
R8101
R8102
R8104
R8105
R8106
R8107
D13 D13 D13 NC_35
NC_35 NC_37 NC_37 D14
IC8100 D14 D14 D14 NC_36
NC_36 NC_38 NC_38 A6 E1
EMMC_SERIAL_22 H26M31002GPR A6 E1 A6 E1 A6 E1 RFU_1 NC_37
EMMC_DATA[0-7] RFU_1 NC_37 NC_3 NC_39 NC_3 NC_39 A7 E2
AR8100 A7 E2 A7 E2 A7 E2 RFU_2 NC_38
22 RFU_2 NC_38 NC_4 NC_40 NC_4 NC_40 C5 E3
1/16W C5 E3 C5 E3 C5 E3 NC_21 NC_39
NC_21 NC_39 NC_23 NC_41 NC_23 NC_41 E5 E12
EMMC_DATA[0] A3 C8 E5 E12 E5 E12 E5 E12 RFU_3 NC_40
DAT0 NC_25 RFU_3 NC_40 NC_42 NC_46 NC_42 NC_46 E8 E13
EMMC_DATA[1] A4 C9 E8 E13 E8 E13 E8 E13 RFU_4 NC_41
DAT1 NC_26 RFU_4 NC_41 NC_43 NC_47 NC_43 NC_47 E9 E14
EMMC_DATA[2] A5 C10 E9 E14 E9 E14 E9 E14 RFU_5 NC_42
DAT2 NC_27 RFU_5 NC_42 NC_44 NC_48 NC_44 NC_48 E10 F1
EMMC_DATA[3] B2 C11 E10 F1 E10 F1 E10 F1 RFU_6 NC_43
EMMC_DATA[4] DAT3 NC_28 RFU_6 NC_43 NC_45 NC_49 NC_45 NC_49 F10 F2
B3 C12 F10 F2 F10 F2 F10 F2 RFU_7 NC_44
EMMC_DATA[5] DAT4 NC_29 RFU_7 NC_44 NC_52 NC_50 NC_52 NC_50 G3 F3
B4 C13 G3 F3 G3 F3 G3 F3 RFU_8 NC_45
EMMC_DATA[6] DAT5 NC_30 RFU_8 NC_45 NC_58 NC_51 NC_58 NC_51 G10 F12
EMMC_SERIAL_22 B5 C14 G10 F12 G10 F12 G10 F12 RFU_9 NC_46
EMMC_DATA[7] AR8101 DAT6 NC_31 RFU_9 NC_46 NC_59 NC_53 NC_59 NC_53 H5 F13
22 B6 D1 H5 F13 H5 F13 H5 F13 RFU_10 NC_47
1/16W DAT7 NC_32 DAT5 RFU_10 NC_47 NC_66 NC_54 NC_66 NC_54 J5 F14
D2 J5 F14 J5 F14 J5 F14 RFU_11 NC_48
NC_33 RFU_11 NC_48 NC_73 NC_55 NC_73 NC_55 K6 G1
D3 K6 G1 K6 G1 K6 G1 RFU_12 NC_49
NC_34 RFU_12 NC_49 NC_80 NC_56 NC_80 NC_56 K7 G2
M6 D4 K7 G2 K7 G2 K7 G2 RFU_13 NC_50
CLK NC_35 RFU_13 NC_50 NC_81 NC_57 NC_81 NC_57 K10 G12
M5 D12 K10 G12 K10 G12 K10 G12 RFU_14 NC_51
CMD NC_36 RFU_14 NC_51 NC_82 NC_60 NC_82 NC_60 P7 G13
D13 P7 G13 P7 G13 P7 G13 RFU_15 NC_52
NC_37 RFU_15 NC_52 NC_116 NC_61 NC_116 NC_61 P10 G14
D14 P10 G14 P10 G14 P10 G14 RFU_16 NC_53
NC_38 RFU_16 NC_53 NC_119 NC_62 NC_119 NC_62 H1
HYNIX_EMMC_2GB
A6 E1 H1 H1 H1 NC_54
TOSHIBA_EMMC_4GB
NC_3 NC_39 NC_54 NC_63 NC_63 H2
A7 E2 H2 H2 H2 NC_55
NC_4 NC_40 NC_55 NC_64 NC_64 K5 H3
TOSHIBA_EMMC_16GB
C5 E3 K5 H3 K5 H3 K5 H3 RSTN NC_56
NC_23 NC_41 RST_N NC_56 RESET NC_65 RSTN NC_65 H12
SAMSUNG_EMMC_2GB
E5 E12 H12 H12 H12 NC_57
NC_42 NC_46 NC_57 NC_67 NC_67 H13
EMMC_SERIAL_22 E8 E13 H13 H13 H13 NC_58
NC_43 NC_47 NC_58 NC_68 NC_68 C6 H14
AR8102 22 E9 E14 C6 H14 C6 H14 C6 H14 VCCQ_1 NC_59
EMMC_CLK NC_44 NC_48 VCCQ_1 NC_59 VCCQ_1 NC_69 VDD_1 NC_69 M4 J1
E10 F1 M4 J1 M4 J1 M4 J1 VCCQ_2 NC_60
EMMC_CMD NC_45 NC_49 DAT6 VCCQ_2 NC_60 VCCQ_2 NC_70 VDD_2 NC_70 N4 J2
F10 F2 N4 J2 N4 J2 N4 J2 VCCQ_3 NC_61
EMMC_RST NC_52 NC_50 VCCQ_3 NC_61 VCCQ_3 NC_71 VDD_3 NC_71 P3 J3
G3 F3 P3 J3 P3 J3 P3 J3 VCCQ_4 NC_62
NC_58 NC_51 VCCQ_4 NC_62 VCCQ_4 NC_72 VDD_4 NC_72 P5 J12
G10 F12 P5 J12 P5 J12 P5 J12 VCCQ_5 NC_63
NC_59 NC_53 VCCQ_5 NC_63 VCCQ_5 NC_74 VDD_5 NC_74 J13
H5 F13 J13 J13 J13 NC_64
NC_66 NC_54 NC_64 NC_75 NC_75 J14
J5 F14 J14 J14 J14 NC_65
C8107 NC_73 NC_55 NC_65 NC_76 NC_76 E6 K1
eMMC serial 100 ohm option OPT 10pF K6 G1 E6 K1 E6 K1 E6 K1 VCC_1 NC_66
NC_80 NC_56 VCC_1 NC_66 VCC_1 NC_77 VDDF_1 NC_77 F5 K2
50V K7 G2 F5 K2 F5 K2 F5 K2 VCC_2 NC_67
NC_81 NC_57 VCC_2 NC_67 VCC_2 NC_78 VDDF_2 NC_78 J10 K3
K10 G12 J10 K3 J10 K3 J10 K3 VCC_3 NC_68
AR8100-*1 AR8101-*1 AR8102-*1 NC_82 NC_60 VCC_3 NC_68 VCC_3 NC_79 VDDF_3 NC_79 K9 K12
100 100 100 P7 G13 K9 K12 K9 K12 K9 K12 VCC_4 NC_69
1/16W 1/16W 1/16W NC_116 NC_61 VCC_4 NC_69 VCC_4 NC_83 VDDF_4 NC_83 K13
EMMC_SERIAL_100
EMMC_SERIAL_100
EMMC_SERIAL_100
P10 G14 K13 K13 K13 NC_70
NC_119 NC_62 NC_70 NC_84 NC_84 K14
H1 K14 K14 K14 NC_71
NC_63 NC_71 NC_85 NC_85 C2 L1
H2 C2 L1 C2 L1 C2 L1 VDDI NC_72
NC_64 VDDI NC_72 VDDI NC_86 VDDI NC_86 L2
K5 H3 L2 L2 L2 NC_73
RESET NC_65 NC_73 NC_87 NC_87 L3
H12 L3 L3 L3 NC_74
C8100 NC_67 NC_74 NC_88 NC_88 E7 L12
OPT 0.1uF H13 E7 L12 E7 L12 C4 L12 VSS_1 NC_75
NC_68 VSS_1 NC_75 VSS_1 NC_89 VSS_1 NC_89 G5 L13
16V C6 H14 G5 L13 G5 L13 E7 L13 VSS_2 NC_76
VCCQ_1 NC_69 VSS_2 NC_76 VSS_2 NC_90 VSS_2 NC_90 H10 L14
3.3V_EMMC M4 J1 H10 L14 H10 L14 G5 L14 VSS_3 NC_77
HYNIX_EMMC_4GB
VCCQ_2 NC_70 VSS_3 NC_77 VSS_3 NC_91 VSS_3 NC_91 K8 M1
N4 J2 K8 M1 K8 M1 H10 M1 VSS_4 NC_78
VCCQ_3 NC_71 VSS_4 NC_78 VSS_4 NC_92 VSS_4 NC_92 C4 M2
P3 J3 C4 M2 C4 M2 K8 M2 VSSQ_1 NC_79
VCCQ_4 NC_72 VSSQ_1 NC_79 VSSQ_1 NC_93 VSS_5 NC_93 N2 M3
P5 J12 N2 M3 N2 M3 N2 M3 VSSQ_2 NC_80
VCCQ_5 NC_74 VSSQ_2 NC_80 VSSQ_2 NC_94 VSS_6 NC_94 N5 M7
DAT3
DAT4
DAT5
DAT6
EMMC_CLK_BALL
EMMC_RESET_BALL
EMMC_CMD_BALL
J13 N5 M7 N5 M7 N5 M7 VSSQ_3 NC_81
NC_75 VSSQ_3 NC_81 VSSQ_3 NC_95 VSS_7 NC_95 P4 M8
J14 EMMC_RESET_BALL P4 M8 P4 M8 P4 M8 VSSQ_4 NC_82
NC_76 VSSQ_4 NC_82 VSSQ_4 NC_96 VSS_8 NC_96 P6 M9
E6 K1 P6 M9 P6 M9 P6 M9 VSSQ_5 NC_83
VCC_1 NC_77 VSSQ_5 NC_83 VSSQ_5 NC_97 VSS_9 NC_97 M10
F5 K2 M10 M10 M10 NC_84
VCC_2 NC_78 NC_84 NC_98 NC_98 M11
J10 K3 M11 M11 M11 NC_85
VCC_3 NC_79 NC_85 NC_99 NC_99 M12
K9 K12 M12 M12 M12 NC_86
VCC_4 NC_83 NC_86 NC_100 NC_100 A1 M13
K13 A1 M13 A1 M13 A1 M13 NC_1 NC_87
NC_84 NC_1 NC_87 NC_1 NC_101 NC_1 NC_101 A2 M14
EMMC_VDDI K14 A2 M14 A2 M14 A2 M14 NC_2 NC_88
NC_85 NC_2 NC_88 NC_2 NC_102 NC_2 NC_102 A8 N1
C2 L1 A8 N1 A8 N1 A8 N1 NC_3 NC_89
VDDI NC_86 NC_3 NC_89 NC_5 NC_103 NC_5 NC_103 A9 N3
L2 A9 N3 A9 N3 A9 N3 NC_4 NC_90
C8104 NC_87 NC_4 NC_90 NC_6 NC_104 NC_6 NC_104 A10 N6
1uF L3 A10 N6 A10 N6 A10 N6 NC_5 NC_91
NC_88 NC_5 NC_91 NC_7 NC_105 NC_7 NC_105 A11 N7
10V E7 L12 A11 N7 A11 N7 A11 N7 NC_6 NC_92
VSS_1 NC_89 NC_6 NC_92 NC_8 NC_106 NC_8 NC_106 A12 N8
G5 L13 A12 N8 A12 N8 A12 N8 NC_7 NC_93
VSS_2 NC_90 NC_7 NC_93 NC_9 NC_107 NC_9 NC_107 A13 N9
H10 L14 A13 N9 A13 N9 A13 N9 NC_8 NC_94
VSS_3 NC_91 NC_8 NC_94 NC_10 NC_108 NC_10 NC_108 A14 N10
K8 M1 A14 N10 A14 N10 A14 N10 NC_9 NC_95
VSS_4 NC_92 NC_9 NC_95 NC_11 NC_109 NC_11 NC_109 B1 N11
C4 M2 B1 N11 B1 N11 B1 N11 NC_10 NC_96
VSSQ_1 NC_93 NC_10 NC_96 NC_12 NC_110 NC_12 NC_110 B7 N12
N2 M3 B7 N12 B7 N12 B7 N12 NC_11 NC_97
VSSQ_2 NC_94 NC_11 NC_97 NC_13 NC_111 NC_13 NC_111 B8 N13
N5 M7 B8 N13 B8 N13 B8 N13 NC_12 NC_98
VSSQ_3 NC_95 NC_12 NC_98 NC_14 NC_112 NC_14 NC_112 B9 N14
P4 M8 B9 N14 B9 N14 B9 N14 NC_13 NC_99
VSSQ_4 NC_96 NC_13 NC_99 NC_15 NC_113 NC_15 NC_113 B10 P1
P6 M9 B10 P1 B10 P1 B10 P1 NC_14 NC_100
VSSQ_5 NC_97 NC_14 NC_100 NC_16 NC_114 NC_16 NC_114 B11 P2
M10 B11 P2 B11 P2 B11 P2 NC_15 NC_101
NC_98 NC_15 NC_101 NC_17 NC_115 NC_17 NC_115 B12 P8
M11 B12 P8 B12 P8 B12 P8 NC_16 NC_102
NC_99 NC_16 NC_102 NC_18 NC_117 NC_18 NC_117 B13 P9
M12 B13 P9 B13 P9 B13 P9 NC_17 NC_103
NC_100 NC_17 NC_103 NC_19 NC_118 NC_19 NC_118 B14 P11
A1 M13 B14 P11 B14 P11 B14 P11 NC_18 NC_104
DAT3 NC_1 NC_101 NC_18 NC_104 NC_20 NC_120 NC_20 NC_120 C1 P12
A2 M14 C1 P12 C1 P12 C1 P12 NC_19 NC_105
DAT4 NC_2 NC_102 NC_19 NC_105 NC_21 NC_121 NC_21 NC_121 C3 P13
A8 N1 C3 P13 C3 P13 C3 P13 NC_20 NC_106
NC_5 NC_103 NC_20 NC_106 NC_22 NC_122 NC_22 NC_122 C7 P14
A9 N3 EMMC_CMD_BALL C7 P14 C7 P14 C7 P14 NC_22 NC_107
NC_6 NC_104 NC_22 NC_107 NC_24 NC_123 NC_24 NC_123
A10 N6
NC_7 NC_105
A11 N7
NC_8 NC_106
A12 N8
NC_9 NC_107
A13 N9
NC_10 NC_108
A14 N10
NC_11 NC_109
B1 N11
NC_12 NC_110
B7 N12
NC_13 NC_111
B8 N13
NC_14 NC_112
B9 N14
NC_15 NC_113
B10 P1 IC8100-*8 IC8100-*9 IC8100-*10 IC8100-*11
NC_16 NC_114 H26M42002GMR THGBMAG5A1JBAIR THGBMAG6A2JBAIR THGBMAG7A2JBAIR
B11 P2 EMMC_CLK_BALL IC8100-*5
KLM4G1FE3B-B001
IC8100-*6
THGBM5G6A2JBAIR
IC8100-*7
KLMAG2GE4A-A001
NC_17 NC_115 A3 C8 A3 C8 A3 C8 A3 C8
B12 P8 A3 C8 A3 C8 A3 C8
A4
DAT0
DAT1
NC_25
NC_26
C9 A4
DAT0
DAT1
NC_23
NC_24
C9 A4
DAT0
DAT1
NC_23
NC_24
C9 A4
DAT0
DAT1
NC_23
NC_24
C9
NC_18 NC_117 A4
DAT0 NC_25
C9 A4
DAT0 NC_23
C9 A4
DAT0 NC_22
C9
A5 C10 A5 C10 A5 C10 A5 C10
TOSHIBA_EMMC_16GB_V4.5
DAT2 NC_27 DAT2 NC_25 DAT2 NC_25 DAT2 NC_25
SAMSUNG_EMMC_16G
Don’t Connect Power At VDDI
DAT1 NC_26 DAT1 NC_24 DAT1 NC_23 B2 C11 B2 C11 B2 C11 B2 C11
EMMC_VDDI B13 P9 A5
DAT2 NC_27
C10 A5
DAT2 NC_25
C10 A5
DAT2 NC_24
C10
B3
DAT3 NC_28
C12 B3
DAT3 NC_26
C12 B3
DAT3 NC_26
C12 B3
DAT3 NC_26
C12
HYNIX_EMMC_8GB
B2 C11 B2 C11 B2 C11
DAT3 NC_28 DAT3 NC_26 DAT3 NC_25 DAT4 NC_29 DAT4 NC_27 DAT4 NC_27 DAT4 NC_27
NC_19 NC_118 B3
DAT4
C12 B3 C12 B3 C12 B4 C13 B4 C13 B4 C13 B4 C13
SAMSUNG_EMMC_4GB
TOSHIBA_EMMC_8GB
NC_29 DAT4 NC_27 DAT4 NC_26 DAT5 NC_30 DAT5 NC_28 DAT5 NC_28 DAT5 NC_28
TOSHIBA_EMMC_4GB_V4.5
TOSHIBA_EMMC_8GB_V4.5
B4 C13 B4 C13 B4 C13
B14 P11 B5
B6
DAT5
DAT6
NC_30
NC_31
C14
D1
B5
B6
DAT5
DAT6
NC_28
NC_29
C14
D1
B5
B6
DAT5
DAT6
NC_27
NC_28
C14
D1
B5
B6
DAT6 NC_31
C14
D1
B5
B6
DAT6 NC_29
C14
D1
B5
B6
DAT6 NC_29
C14
D1
B5
B6
DAT6 NC_29
C14
D1
NC_20 NC_120 DAT7 NC_32
D2
DAT7 NC_30
D2
DAT7 NC_29
D2
DAT7 NC_32
NC_33
D2
DAT7 NC_30
NC_31
D2
DAT7 NC_30
NC_31
D2
DAT7 NC_30
NC_31
D2
C1 P12 M6
NC_33
NC_34
D3
D4 M6
NC_31
NC_32
D3
D4 M6
NC_30
NC_31
D3
D4 M6
NC_34
D3
D4 M6
NC_32
D3
D4 M6
NC_32
D3
D4 M6
NC_32
D3
D4
NC_21 NC_121 M5
CLK
CMD
NC_35
NC_36
D12 M5
CLK
CMD
NC_33
NC_34
D12 M5
CLK
CMD
NC_32
NC_33
D12 M5
CLK NC_35
D12 M5
CLK NC_33
D12 M5
CLK NC_33
D12 M5
CLK NC_33
D12
(Just Interal LDO Capacitor)
CMD NC_36 CMD NC_34 CMD NC_34 CMD NC_34
C3 P13 NC_37
D13
D14
NC_35
D13
D14
NC_34
D13
D14 NC_37
D13
D14
NC_35
D13
D14
NC_35
D13
D14
NC_35
D13
D14
DAT5 NC_22 NC_122 A6
A7
NC_3
NC_38
NC_39
E1
E2
A6
A7
RFU_1
NC_36
NC_37
E1
E2
A6
A7
RFU_1
NC_35
NC_36
E1
E2
A6
NC_38
E1 A6
NC_36
E1 A6
NC_36
E1 A6
NC_36
E1
C7 P14 C5
E5
NC_4
NC_23
NC_40
NC_41
E3
E12
C5
E5
RFU_2
NC_21
NC_38
NC_39
E3
E12
C5
E5
RFU_2
RFU_3
NC_37
NC_38
E3
E12
A7
C5
NC_3
NC_4
NC_39
NC_40
E2
E3
A7
C5
RFU_1
RFU_2
NC_37
NC_38
E2
E3
A7
C5
RFU_1
RFU_2
NC_37
NC_38
E2
E3
A7
C5
RFU_1
RFU_2
NC_37
NC_38
E2
E3
NC_24 NC_123 E8
E9
NC_42
NC_43
NC_46
NC_47
E13
E14
E8
E9
RFU_3
RFU_4
NC_40
NC_41
E13
E14
E8
E9
RFU_4
RFU_5
NC_40
NC_41
E13
E14
E5
NC_23
NC_42
NC_41
NC_46
E12 E5
NC_21
RFU_3
NC_39
NC_40
E12 E5
NC_21
RFU_3
NC_39
NC_40
E12 E5
NC_21
RFU_3
NC_39
NC_40
E12
NC_44 NC_48 RFU_5 NC_42 RFU_6 NC_42 E8 E13 E8 E13 E8 E13 E8 E13
E10 F1 E10 F1 E10 F1 NC_43 NC_47 RFU_4 NC_41 RFU_4 NC_41 RFU_4 NC_41
NC_45 NC_49 RFU_6 NC_43 NC_39 NC_43 E9 E14 E9 E14 E9 E14 E9 E14
F10 F2 F10 F2 F10 F2 NC_44 NC_48 RFU_5 NC_42 RFU_5 NC_42 RFU_5 NC_42
G3
NC_52 NC_50 RFU_7 NC_44 RFU_7 NC_44 E10 F1 E10 F1 E10 F1 E10 F1
F3 G3 F3 G3 F3 NC_45 NC_49 RFU_6 NC_43 RFU_6 NC_43 RFU_6 NC_43
NC_58 NC_51 RFU_8 NC_45 RFU_8 NC_45 F10 F2 F10 F2 F10 F2 F10 F2
G10 F12 G10 F12 G10 F12
NC_59 NC_53 RFU_9 NC_46 RFU_9 NC_46 NC_52 NC_50 RFU_7 NC_44 RFU_7 NC_44 RFU_7 NC_44
H5 F13 H5 F13 H5 F13 G3 F3 G3 F3 G3 F3 G3 F3
J5
NC_66 NC_54
F14 J5
RFU_10 NC_47
F14 J5
RFU_10 NC_47
F14
NC_58 NC_51 RFU_8 NC_45 RFU_8 NC_45 RFU_8 NC_45
G10 F12 G10 F12 G10 F12 G10 F12
NC_73 NC_55 RFU_11 NC_48 RFU_11 NC_48 NC_59 NC_53 RFU_9 NC_46 RFU_9 NC_46 RFU_9 NC_46
K6 G1 K6 G1 K6 G1 H5 F13 H5 F13 H5 F13 H5 F13
NC_80 NC_56 RFU_12 NC_49 RFU_12 NC_49
K7 G2 K7 G2 K7 G2 NC_66 NC_54 RFU_10 NC_47 RFU_10 NC_47 RFU_10 NC_47
NC_81 NC_57 RFU_13 NC_50 RFU_13 NC_50 J5 F14 J5 F14 J5 F14 J5 F14
K10 G12 K10 G12 K10 G12 NC_73 NC_55 RFU_11 NC_48 RFU_11 NC_48 RFU_11 NC_48
P7
NC_82 NC_60 RFU_14 NC_51 RFU_14 NC_51 K6 G1 K6 G1 K6 G1 K6 G1
G13 P7 G13 P7 G13 NC_80 NC_56 RFU_12 NC_49 RFU_12 NC_49 RFU_12 NC_49
NC_116 NC_61 RFU_15 NC_52 RFU_15 NC_52 K7 G2 K7 G2 K7 G2 K7 G2
P10 G14 P10 G14 P10 G14
NC_119 NC_62 RFU_16 NC_53 NC_104 NC_53 NC_81 NC_57 RFU_13 NC_50 RFU_13 NC_50 RFU_13 NC_50
H1 H1 H1 K10 G12 K10 G12 K10 G12 K10 G12
NC_63 NC_54 NC_54 NC_82 NC_60 RFU_14 NC_51 RFU_14 NC_51 RFU_14 NC_51
DU1 DU9 K5
RSTN
NC_64
NC_65
H2
H3 K5
RSTN
NC_55
NC_56
H2
H3 K5
RESET
NC_55
NC_56
H2
H3
P7
P10
NC_116 NC_61
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
DUMMY_1 DUMMY_9 NC_67
H12
H13
NC_57
H12
H13
NC_57
H12
H13
NC_119 NC_62
NC_63
H1
RFU_16 NC_53
NC_54
H1
RFU_16 NC_53
NC_54
H1
RFU_16 NC_53
NC_54
H1
DU2 DU10 C6
M4
VDD_1
NC_68
NC_69
H14
J1
C6
M4
VCCQ_1
NC_58
NC_59
H14
J1
C6
M4
VDD_1
NC_58
NC_59
H14
J1 K5
NC_64
H2
H3 K5
NC_55
H2
H3 K5
NC_55
H2
H3 K5
NC_55
H2
H3
DUMMY_2 DUMMY_10 N4
VDD_2 NC_70
J2 N4
VCCQ_2 NC_60
J2 N4
VDD_2 NC_60
J2
RESET NC_65
H12
RST_N NC_56
H12
RST_N NC_56
H12
RST_N NC_56
H12
DU3 DU11 P3
P5
VDD_3
VDD_4
NC_71
NC_72
J3
J12
P3
P5
VCCQ_3
VCCQ_4
NC_61
NC_62
J3
J12
P3
P5
VDD_3
VDD_4
NC_61
NC_62
J3
J12 C6
NC_67
NC_68
H13
H14 C6
NC_57
NC_58
H13
H14 C6
NC_57
NC_58
H13
H14 C6
NC_57
NC_58
H13
H14
DUMMY_3 DUMMY_11 VDD_5 NC_74
NC_75
J13
VCCQ_5 NC_63
NC_64
J13
VDD_5 NC_63
NC_64
J13
M4
VCCQ_1 NC_69
J1 M4
VCCQ_1 NC_59
J1 M4
VCCQ_1 NC_59
J1 M4
VCCQ_1 NC_59
J1
DU4 DU12 E6
VDDF_1
NC_76
NC_77
J14
K1 E6
VCC_1
NC_65
NC_66
J14
K1 E6
VDDF_1
NC_65
NC_66
J14
K1
N4
P3
VCCQ_2
VCCQ_3
NC_70
NC_71
J2
J3
N4
P3
VCCQ_2
VCCQ_3
NC_60
NC_61
J2
J3
N4
P3
VCCQ_2
VCCQ_3
NC_60
NC_61
J2
J3
N4
P3
VCCQ_2
VCCQ_3
NC_60
NC_61
J2
J3
DUMMY_4 DUMMY_12 F5
J10
VDDF_2 NC_78
K2
K3
F5
J10
VCC_2 NC_67
K2
K3 J10
F5
VDDF_2 NC_67
K2
K3 P5
VCCQ_4 NC_72
J12 P5
VCCQ_4 NC_62
J12 P5
VCCQ_4 NC_62
J12 P5
VCCQ_4 NC_62
J12
DU5 DU13 K9
VDDF_3
VDDF_4
NC_79
NC_83
K12
K13
K9
VCC_3
VCC_4
NC_68
NC_69
K12
K13
K9
VDDF_3
VDDF_4
NC_68
NC_69
K12
K13
VCCQ_5 NC_74
NC_75
J13
VCCQ_5 NC_63
NC_64
J13
VCCQ_5 NC_63
NC_64
J13
VCCQ_5 NC_63
NC_64
J13
DUMMY_5 DUMMY_13 NC_84
K14
NC_70
K14
NC_70
K14
E6
NC_76
J14
K1 E6
NC_65
J14
K1 E6
NC_65
J14
K1 E6
NC_65
J14
K1
DU6 DU14 C2
VDDI
NC_85
NC_86
L1
L2
C2
VDDI
NC_71
NC_72
L1
L2
C2
VDDI
NC_71
NC_72
L1
L2
F5
VCC_1
VCC_2
NC_77
NC_78
K2 F5
VCC_1
VCC_2
NC_66
NC_67
K2 F5
VCC_1
VCC_2
NC_66
NC_67
K2 F5
VCC_1
VCC_2
NC_66
NC_67
K2
DUMMY_6 DUMMY_14 NC_87
NC_88
L3
NC_73
NC_74
L3
NC_73
NC_74
L3 J10
VCC_3 NC_79
K3 J10
VCC_3 NC_68
K3 J10
VCC_3 NC_68
K3 J10
VCC_3 NC_68
K3
DU7 DU15 E7
G5
VSS_2
VSS_3
NC_89
NC_90
L12
L13
E7
G5
VSS_1
VSS_2
NC_75
NC_76
L12
L13
E7
G5
VSS_2
VSS_3
NC_75
NC_76
L12
L13
K9
VCC_4 NC_83
NC_84
K12
K13
K9
VCC_4 NC_69
NC_70
K12
K13
K9
VCC_4 NC_69
NC_70
K12
K13
K9
VCC_4 NC_69
NC_70
K12
K13
DUMMY_7 DUMMY_15 H10
K8
VSS_4 NC_91
L14
M1
H10
K8
VSS_3 NC_77
L14
M1
H10
K8
VSS_4 NC_77
L14
M1 NC_85
K14
NC_71
K14
NC_71
K14
NC_71
K14
DU8 DU16 C4
N2
VSS_5
VSS_1
NC_92
NC_93
M2
M3
C4
N2
VSS_4
VSSQ_1
NC_78
NC_79
M2
M3
C4
N2
VSS_9
VSS_1
NC_78
NC_79
M2
M3
C2
VDDI NC_86
L1
L2
C2
VDDI NC_72
L1
L2
C2
VDDI NC_72
L1
L2
C2
VDDI NC_72
L1
L2
DUMMY_8 DUMMY_16 N5
P4
VSS_6
VSS_7
NC_94
NC_95
M7
M8
N5
P4
VSSQ_2
VSSQ_3
NC_80
NC_81
M7
M8
N5
P4
VSS_5
VSS_6
NC_80
NC_81
M7
M8 E7
NC_87
NC_88
L3
L12 E7
NC_73
NC_74
L3
L12 E7
NC_73
NC_74
L3
L12 E7
NC_73
NC_74
L3
L12
P6
VSS_8 NC_96
P6
VSSQ_4 NC_82
P6
VSS_7 NC_82 VSS_1 NC_89 VSS_1 NC_75 VSS_1 NC_75 VSS_1 NC_75
M9 M9 M9 G5 L13 G5 L13 G5 L13 G5 L13
VSS_9 NC_97 VSSQ_5 NC_83 VSS_8 NC_83 VSS_2 NC_90 VSS_2 NC_76 VSS_2 NC_76 VSS_2 NC_76
M10 M10 M10 H10 L14 H10 L14 H10 L14 H10 L14
NC_98 NC_84 NC_84
M11 M11 M11 VSS_3 NC_91 VSS_3 NC_77 VSS_3 NC_77 VSS_3 NC_77
NC_99 NC_85 NC_85 K8 M1 K8 M1 K8 M1 K8 M1
M12 M12 M12 VSS_4 NC_92 VSS_4 NC_78 VSS_4 NC_78 VSS_4 NC_78
A1
NC_100
A1
NC_86
A1
NC_86 C4 M2 C4 M2 C4 M2 C4 M2
M13 M13 M13 VSSQ_1 NC_93 VSSQ_1 NC_79 VSSQ_1 NC_79 VSSQ_1 NC_79
NC_1 NC_101 NC_1 NC_87 NC_1 NC_87 N2 M3 N2 M3 N2 M3 N2 M3
A2 M14 A2 M14 A2 M14
NC_2 NC_102 NC_2 NC_88 NC_2 NC_88 VSSQ_2 NC_94 VSSQ_2 NC_80 VSSQ_2 NC_80 VSSQ_2 NC_80
A8 N1 A8 N1 A8 N1 N5 M7 N5 M7 N5 M7 N5 M7
A9
NC_5 NC_103
A9
NC_3 NC_89
A9
NC_3 NC_89 VSSQ_3 NC_95 VSSQ_3 NC_81 VSSQ_3 NC_81 VSSQ_3 NC_81
N3 N3 N3 P4 M8 P4 M8 P4 M8 P4 M8
NC_6 NC_104 NC_4 NC_90 NC_4 NC_90 VSSQ_4 NC_96 VSSQ_4 NC_82 VSSQ_4 NC_82 VSSQ_4 NC_82
A10 N6 A10 N6 A10 N6 P6 M9 P6 M9 P6 M9 P6 M9
NC_7 NC_105 NC_5 NC_91 NC_5 NC_91
A11 N7 A11 N7 A11 N7 VSSQ_5 NC_97 VSSQ_5 NC_83 VSSQ_5 NC_83 VSSQ_5 NC_83
NC_8 NC_106 NC_6 NC_92 NC_6 NC_92 M10 M10 M10 M10
A12 N8 A12 N8 A12 N8 NC_98 NC_84 NC_84 NC_84
A13
NC_9 NC_107
A13
NC_7 NC_93
A13
NC_7 NC_93 M11 M11 M11 M11
N9 N9 N9 NC_99 NC_85 NC_85 NC_85
NC_10 NC_108 NC_8 NC_94 NC_8 NC_94 M12 M12 M12 M12
A14 N10 A14 N10 A14 N10
NC_11 NC_109 NC_9 NC_95 NC_9 NC_95 NC_100 NC_86 NC_86 NC_86
B1 N11 B1 N11 B1 N11 A1 M13 A1 M13 A1 M13 A1 M13
B7
NC_12 NC_110
B7
NC_10 NC_96
B7
NC_10 NC_96 NC_1 NC_101 NC_1 NC_87 NC_1 NC_87 NC_1 NC_87
N12 N12 N12 A2 M14 A2 M14 A2 M14 A2 M14
NC_13 NC_111 NC_11 NC_97 NC_11 NC_97 NC_2 NC_102 NC_2 NC_88 NC_2 NC_88 NC_2 NC_88
B8 N13 B8 N13 B8 N13 A8 N1 A8 N1 A8 N1 A8 N1
NC_14 NC_112 NC_12 NC_98 NC_12 NC_98
B9 N14 B9 N14 B9 N14 NC_5 NC_103 NC_3 NC_89 NC_3 NC_89 NC_3 NC_89
NC_15 NC_113 NC_13 NC_99 NC_13 NC_99 A9 N3 A9 N3 A9 N3 A9 N3
B10 P1 B10 P1 B10 P1 NC_6 NC_104 NC_4 NC_90 NC_4 NC_90 NC_4 NC_90
B11
NC_16 NC_114
B11
NC_14 NC_100
B11
NC_14 NC_100 A10 N6 A10 N6 A10 N6 A10 N6
P2 P2 P2 NC_7 NC_105 NC_5 NC_91 NC_5 NC_91 NC_5 NC_91
NC_17 NC_115 NC_15 NC_101 NC_15 NC_101 A11 N7 A11 N7 A11 N7 A11 N7
B12 P8 B12 P8 B12 P8
NC_18 NC_117 NC_16 NC_102 NC_16 NC_102 NC_8 NC_106 NC_6 NC_92 NC_6 NC_92 NC_6 NC_92
B13 P9 B13 P9 B13 P9 A12 N8 A12 N8 A12 N8 A12 N8
B14
NC_19 NC_118
B14
NC_17 NC_103
B14
NC_17 NC_103 NC_9 NC_107 NC_7 NC_93 NC_7 NC_93 NC_7 NC_93
P11 P11 P11 A13 N9 A13 N9 A13 N9 A13 N9
NC_20 NC_120 NC_18 NC_104 NC_18 RFU_16 NC_10 NC_108 NC_8 NC_94 NC_8 NC_94 NC_8 NC_94
C1 P12 C1 P12 C1 P12 A14 N10 A14 N10 A14 N10 A14 N10
NC_21 NC_121 NC_19 NC_105 NC_19 NC_105
C3 P13 C3 P13 C3 P13 NC_11 NC_109 NC_9 NC_95 NC_9 NC_95 NC_9 NC_95
NC_22 NC_122 NC_20 NC_106 NC_20 NC_106 B1 N11 B1 N11 B1 N11 B1 N11
C7 P14 C7 P14 C7 P14 NC_12 NC_110 NC_10 NC_96 NC_10 NC_96 NC_10 NC_96
NC_24 NC_123 NC_22 NC_107 NC_21 NC_107 B7 N12 B7 N12 B7 N12 B7 N12
NC_13 NC_111 NC_11 NC_97 NC_11 NC_97 NC_11 NC_97
B8 N13 B8 N13 B8 N13 B8 N13
NC_14 NC_112 NC_12 NC_98 NC_12 NC_98 NC_12 NC_98
B9 N14 B9 N14 B9 N14 B9 N14
NC_15 NC_113 NC_13 NC_99 NC_13 NC_99 NC_13 NC_99
B10 P1 B10 P1 B10 P1 B10 P1
DU1 DU9 NC_16 NC_114 NC_14 NC_100 NC_14 NC_100 NC_14 NC_100
DUMMY_1 DUMMY_9 B11 P2 B11 P2 B11 P2 B11 P2
DU2 DU10 NC_17 NC_115 NC_15 NC_101 NC_15 NC_101 NC_15 NC_101
DUMMY_2 DUMMY_10 B12 P8 B12 P8 B12 P8 B12 P8
DU3 DU11 NC_18 NC_117 NC_16 NC_102 NC_16 NC_102 NC_16 NC_102
DUMMY_3 DUMMY_11 B13 P9 B13 P9 B13 P9 B13 P9
DU4 DU12 NC_19 NC_118 NC_17 NC_103 NC_17 NC_103 NC_17 NC_103
DUMMY_4 DUMMY_12 B14 P11 B14 P11 B14 P11 B14 P11
DU5 DU13
DUMMY_5 DUMMY_13 NC_20 NC_120 NC_18 NC_104 NC_18 NC_104 NC_18 NC_104
DU6 DU14 C1 P12 C1 P12 C1 P12 C1 P12
DUMMY_6 DUMMY_14 NC_21 NC_121 NC_19 NC_105 NC_19 NC_105 NC_19 NC_105
DU7 DU15 C3 P13 C3 P13 C3 P13 C3 P13
DUMMY_7 DUMMY_15 NC_22 NC_122 NC_20 NC_106 NC_20 NC_106 NC_20 NC_106
DU8 DU16 C7 P14 C7 P14 C7 P14 C7 P14
DUMMY_8 DUMMY_16
NC_24 NC_123 NC_22 NC_107 NC_22 NC_107 NC_22 NC_107
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-081-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS eMMC 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
81
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
XTAL(24.75MHz)
SPI/I2C For Aardvak Interface JTAG1 for HEVC JTAG2 for HEVC
R12004
1M
+3.3V_NORMAL +3.3V_NORMAL
X12000
24.75MHz SW12000 P12006
X-TAL_1 GND_2 JTP-1127WEM Serial Flash Boot Test
XTAL_IN 1 4 12507WS-08L
R12022 +3.3V_NORMAL
GND_1 X-TAL_2 330 D14_HWRESET
C12000 2 3 XTAL_OUT P12001 C12010 C12008
1
3
24pF 12507WS-10L 0.1uF 0.1uF
50V C12003 R12068 1 16V 16V
C12001
24pF 0.1uF 1K
50V 16V
2
4
1 2
TDI_2 TDI_1
R12063 0 3
2 SPI_CS_M
TMS_2 TMS_1
R12064 0 4
3 SPI_MOSI_M
TCK_2 TCK_1
R12065 0 5
4 SPI_SCLK_M
TDO_2 TDO_1
R12027 R12066 0 6
10 5 SPI_MISO_M
D13_INT TRST_N_2 TRST_N_1
GPIO[5]
+3.3V_NORMAL - 1 : Serial Flash Boot R12067 0
6 7
- 0 : Live Boot SPI_DL_MODE
+3.3V_NORMAL
IC12000
R12023 GPIO[5] OPT 8
3.3K LG1512D GPIO[4] 7 R12069 0
R12038 15K
R12095 15K
R12096 15K
R12097 15K
R12098 15K
OPT GPIO[3]
GPIO[2] OPT
9
GPIO[1] +3.3V_NORMAL 8 R12070 0 FLASH_WP
B3 Y22 GPIO[0]
XTAL_IN XTALI GPIO[7]
A3 W20 R12071 0
XTAL_OUT XTALO GPIO[6] FLASH_WP 9
W21 I2C_SDA2
D14_HWRESET GPIO[5] GPIO[5]
AR12000 A6 V20
SPI_DL_MODE 33 PORES_N GPIO[4] GPIO[4] R12072 0
R12039 27K
V21
2K
2K
1K
GPIO[3] 10 I2C_SCL2
GPIO[3]
0.1uF C12002 B6 V22
TRST_N_0 TRST_0 GPIO[2] GPIO[2]
R12032
R12099
R12003
B7 U20 11
10K R12000 TMS_0 TMS_0 GPIO[1] GPIO[1]
C6 U21
TCK_0 TCK_0 GPIO[0] GPIO[0]
C7
TDI_0 TDI_0
A8 C18
TDO_0 TDO_0 HDMI0_DDC_CK HDMI0_DDC_CK
H21 A18
TRST_N_1 TRST_1 HDMI0_DDC_DA HDMI0_DDC_DA
K22 B18 UART0 For system
TMS_1 TMS_1 HDMI0_HPD UART1 For HEVC
H20 C17
TCK_1 TCK_1 HDMI0_REXT +3.3V_NORMAL +3.3V_NORMAL
J21 B19 HDMI0_DDC_CK P12007
TDI_1 TDI_1 HDMI0_CEC
J20 C19 HDMI0_DDC_DA 12507WS-04L
TDO_1
Closed to D13
1.6K 1%
TDO_1 HDMI0_DDC_CEC
R12044
P19 HDMI1_DDC_CK
TRST_N_2 TRST_2
M19 B15 HDMI1_DDC_DA R12103
TMS_2 TMS_2 HDMI0_TX0N HDMI0_TX0N R12089
L19 C15 +3.3V_NORMAL 1 4.7K
TCK_2 TCK_2 HDMI0_TX0P HDMI0_TX0P 4.7K
N19 B16
TRST_N_0 TDI_2 TDI_2 HDMI0_TX1N HDMI0_TX1N
K19 C16
TMS_0 TDO_2 TDO_2 HDMI0_TX1P HDMI0_TX1P 2
R12042 27K
B17 +3.3V_NORMAL UART_RX_0 UART_RX_1
R12036 2K
R12037 2K
1K
TCK_0 HDMI0_TX2N HDMI0_TX2N SPI FLASH(4MByte)
T22 A17
UART_RX_0 UART_RXD0 HDMI0_TX2P HDMI0_TX2P
R12041
TDI_0 R21 B14
UART_TX_0 HDMI0_TXCN 3
TDO_0 UART_TXD0 HDMI0_TXCN
T20 C14
UART_RX_1 UART_RXD1 HDMI0_TXCP HDMI0_TXCP
T21 IC12002
UART_TX_1 UART_TXD1 4
C12 MX25L3206EM2I-12G UART_TX_0 UART_TX_1
HDMI1_DDC_CK HDMI1_DDC_CK R12060 C12005
R12010 33 N20 A12 0.1uF
SOC_SPI0_SCLK SPI_SCLK_S HDMI1_DDC_DA HDMI1_DDC_DA 10K 5
R12011 33 P22 B12
SOC_SPI0_CS0 SPI_CS_S HDMI1_HPD CS# VCC
R12012 33 P20 C11 1 8 C12011 C12009
SOC_SPI0_MOSI SPI_MOSI_S HDMI1_REXT SPI_CS_M 0.1uF 0.1uF
R12013 33 P21 B13
SOC_SPI0_MISO SPI_MISO_S HDMI1_CEC 16V 16V
R12014 33 M22 C13 R12062 SO/SIO1 HOLD# R12073
SPI_SCLK_M
Closed to D13
1.6K 1%
SPI_SCK_M HDMI1_DDC_CEC 2 7
R12045
R12015 33 M21 SPI_MISO_M
SPI_CS_M SPI_CS_M 33 3.3K
R12016 33 N21 B9 R12054
SPI_MOSI_M SPI_MOSI_M HDMI1_TX0N HDMI1_TX0N WP# SCLK
M20 C9 0
SPI_MISO_M HDMI1_TX0P FLASH_WP 3 6 SPI_SCLK_M
SPI_MISO_M HDMI1_TX0P
B10 R12061
HDMI1_TX1N HDMI1_TX1N 10K
R12018 33 L20 C10 GND SI/SIO0
SCL_S HDMI1_TX1P HDMI1_TX1P OPT 4 5
R12019 33 L21 B11 SPI_MOSI_M
SDA_S HDMI1_TX2N HDMI1_TX2N
R12020 33 K20 A11
I2C_SCL2 SCL_M HDMI1_TX2P HDMI1_TX2P
R12021 33 K21 B8
I2C_SDA2 SDA_M HDMI1_TXCN HDMI1_TXCN
C8
HDMI1_TXCP HDMI1_TXCP
D22
D13_STPO_CLK STPI_CLK
C20 A21
D13_STPO_SOP STPI_SOP SMODE[0] SMODE[0]
D20 A20
D13_STPO_VAL STPI_VAL SMODE[1] SMODE[1]
D21
D13_STPO_ERR STPI_ERR
E21 C21
D13_STPO_DATA STPI_DATA[0] TMODE[0]
E20 B20
STPI_DATA[1] TMODE[1]
F22 B21
STPI_DATA[2] TMODE[2]
F21 B22
STPI_DATA[3] TMODE[3]
F20
STPI_DATA[4]
G21
STPI_DATA[5]
G20
STPI_DATA[6]
H22
STPI_DATA[7]
R12050
0
OPT
+3.3V_NORMAL +3.3V_NORMAL +3.3V_NORMAL
R12001 R12005 R12024
1K 1K 1K
OPT OPT
SMODE[0] SMODE[1] GPIO[5]
R12002 R12006 R12025
1K 1K 1K
OPT
SMODE[1:0]
- 00 : Normal Mode GPIO[5]
- Other : Test Mode - 1 : Serial Flash Boot
- 0 : Live Boot
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-119-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC12101 IC12103 M0_1_DDR_VREFCA_D14
M0_DDR_VREFCA_D14
H5TQ1G63EFR-PBC H5TQ1G63EFR-PBC
M0_1_DDR_VREFDQ_D14
DDR3
IC12000 N3 M8 M0_DDR_VREFDQ_D14 N3
DDR3 M8
M0_DDR_A0_D14 1Gbit M0_DDR_A0_D14
LG1512D VDDC15_D14 P7
A0 VREFCA
P7
A0 1Gbit VREFCA
M0_DDR_CKE_D14 M0_DDR_A1_D14 A1 (x16) M0_DDR_A1_D14 A1
P3 P3 (x16)
M0_DDR_A2_D14 A2 M0_DDR_A2_D14 A2
N2 H1 N2 H1
R12112 R12120 M0_DDR_A3_D14 A3 VREFDQ M0_DDR_A3_D14 A3 VREFDQ
V13 P8 P8
DDR0_A[0] M0_DDR_A0_D14 10K 10K M0_DDR_A4_D14 A4 M0_DDR_A4_D14 A4
V15 P2 VDDC15_D14 P2 VDDC15_D14
DDR0_A[1] M0_DDR_A1_D14 M0_DDR_A5_D14 A5 R12127 M0_DDR_A5_D14 A5 R12129
V11 R8 L8 R8 L8
DDR0_A[2] M0_DDR_A2_D14 M0_DDR_RESET_N_D14 M0_DDR_A6_D14 A6 ZQ M0_DDR_A6_D14 A6 ZQ
V9 R2 240 R2 240
DDR0_A[3] M0_DDR_A3_D14 M0_DDR_A7_D14 A7 1% M0_DDR_A7_D14 A7 1%
W17 T8 T8
DDR0_A[4] M0_DDR_A4_D14 M0_DDR_A8_D14 A8 M0_DDR_A8_D14 A8
W9 R3 B2 R3 B2
DDR0_A[5] M0_DDR_A5_D14 M0_DDR_A9_D14 A9 VDD_1 M0_DDR_A9_D14 A9 VDD_1
W16 L7 D9 L7 D9
DDR0_A[6] M0_DDR_A6_D14 M0_D_CLK_D14 M0_U_CLK_D14 M0_DDR_A10_D14 A10/AP VDD_2 M0_DDR_A10_D14 A10/AP VDD_2
V10 R7 G7 R7 G7
DDR0_A[7] M0_DDR_A7_D14 M0_DDR_A11_D14 A11 VDD_3 M0_DDR_A11_D14 A11 VDD_3
R12111
R12117
V17 N7 K2 N7 K2
100
100
DDR0_A[8] M0_DDR_A8_D14 M0_DDR_A12_D14 A12/BC VDD_4 M0_DDR_A12_D14 A12/BC VDD_4
V12 T3 K8 T3 K8
DDR0_A[9] M0_DDR_A9_D14 M0_DDR_A13_D14 NC_7 VDD_5 M0_DDR_A13_D14 NC_7 VDD_5
W18 N1 N1
DDR0_A[10] M0_DDR_A10_D14 VDD_6 VDD_6
W15 M0_D_CLKN_D14 M0_U_CLKN_D14 M7 N9 M7 N9
DDR0_A[11] M0_DDR_A11_D14 NC_5 VDD_7 NC_5 VDD_7
W14 R1 R1
DDR0_A[12] M0_DDR_A12_D14 VDD_8 VDD_8
W11 M2 R9 M2 R9
DDR0_A[13] M0_DDR_A13_D14 VDDC15_D14 M0_DDR_BA0_D14 BA0 VDD_9 M0_DDR_BA0_D14 BA0 VDD_9
V16 VDDC15_D14 N8 N8
DDR0_A[14] VDDC15_D14 M0_DDR_BA1_D14 BA1 M0_DDR_BA1_D14 BA1
V14 VDDC15_D14 M3 M3
DDR0_A[15] M0_1_DDR_VREFCA_D14 M0_DDR_BA2_D14 BA2 M0_DDR_BA2_D14 BA2
A1 A1
M0_DDR_VREFCA_D14 M0_1_DDR_VREFDQ_D14 VDDQ_1 VDDQ_1
R12118
W8 J7 A8 J7 A8
R12113
DDR0_BA[0] M0_DDR_BA0_D14 M0_DDR_VREFDQ_D14 M0_D_CLK_D14 CK VDDQ_2 M0_U_CLK_D14 CK VDDQ_2
1K 1%
R12124
1K 1%
V18 K7 C1 K7 C1
R12121
DDR0_BA[1] M0_DDR_BA1_D14 M0_D_CLKN_D14 CK VDDQ_3 M0_U_CLKN_D14 CK VDDQ_3
1K 1%
1K 1%
W12 K9 C9 K9 C9
DDR0_BA[2] M0_DDR_BA2_D14 M0_DDR_CKE_D14 CKE VDDQ_4 M0_DDR_CKE_D14 CKE VDDQ_4
D2 D2
VDDQ_5 VDDQ_5
Y17 L2 E9 L2 E9
0.1uF
0.1uF
DDR0_U_CK M0_U_CLK_D14 CS VDDQ_6 CS VDDQ_6
R12119
1%
AA17 K1 F1 K1 F1
R12114
1%
0.1uF
0.1uF
DDR0_U_CK_N M0_U_CLKN_D14 M0_DDR_ODT_D14 ODT VDDQ_7 M0_DDR_ODT_D14 ODT VDDQ_7
R12125
1%
Y8 J3 H2 0.1uF J3 H2 0.1uF
R12122
1%
C12105 C12110 C12114
M0_D_CLK_D14 M0_DDR_RASN_D14 M0_DDR_RASN_D14
C12103
DDR0_D_CK RAS VDDQ_8 RAS VDDQ_8
AA8 K3 H9 0.1uF K3 H9 0.1uF
OPT
1K
C12111 C12115
C12107
1K
M0_D_CLKN_D14 M0_DDR_CASN_D14 M0_DDR_CASN_D14
OPT
C12106
DDR0_D_CK_N CAS VDDQ_9 CAS VDDQ_9
W13 L3 L3
OPT
1K
1K
M0_DDR_CKE_D14 M0_DDR_WEN_D14 M0_DDR_WEN_D14
OPT
DDR0_CKE WE WE
J1 J1
NC_1 NC_1
V7 T2 J9 T2 J9
DDR0_ODT M0_DDR_ODT_D14 M0_DDR_RESET_N_D14 RESET NC_2 M0_DDR_RESET_N_D14 RESET NC_2
W6 L1 L1
DDR0_RAS_N M0_DDR_RASN_D14 NC_3 NC_3
W7 L9 L9
DDR0_CAS_N M0_DDR_CASN_D14 NC_4 NC_4
V8 F3 T7 F3 T7
DDR0_WE_N M0_DDR_WEN_D14 M0_DDR_DQS0_D14 DQSL NC_6 M0_DDR_DQS2_D14 DQSL NC_6
G3 G3
M0_DDR_DQS_N0_D14 DQSL M0_DDR_DQS_N2_D14 DQSL
W10
DDR0_RST_N M0_DDR_RESET_N_D14
C7 A9 C7 A9
M0_DDR_DQS1_D14 DQSU VSS_1 M0_DDR_DQS3_D14 DQSU VSS_1
V6 240 R12108 B7 B3 B7 B3
DDR0_ZQ_CALIB M0_DDR_DQS_N1_D14 DQSU VSS_2 M0_DDR_DQS_N3_D14 DQSU VSS_2
1% E1 E1
VSS_3 VSS_3
AA7 E7 G8 E7 G8
DDR0_DQS[0] M0_DDR_DQS0_D14 IC12000 M0_DDR_DM0_D14 DML VSS_4 M0_DDR_DM2_D14 DML VSS_4
Y7 D3 J2 D3 J2
DDR0_DQS_N[0] M0_DDR_DQS_N0_D14 LG1512D M0_DDR_DM1_D14 DMU VSS_5 M0_DDR_DM3_D14 DMU VSS_5
AA9 J8 J8
DDR0_DQS[1] M0_DDR_DQS1_D14 VSS_6 VSS_6
AB9 E3 M1 E3 M1
DDR0_DQS_N[1] M0_DDR_DQS_N1_D14 M0_DDR_DQ0_D14 DQL0 VSS_7 M0_DDR_DQ16_D14 DQL0 VSS_7
AA16 F7 M9 F7 M9
DDR0_DQS[2] M0_DDR_DQS2_D14 M0_DDR_DQ1_D14 DQL1 VSS_8 M0_DDR_DQ17_D14 DQL1 VSS_8
Y16 L5 F2 P1 F2 P1
DDR0_DQS_N[2] M0_DDR_DQS_N2_D14 DDR1_A[0] M1_DDR_A0_D14 M0_DDR_DQ2_D14 DQL2 VSS_9 M0_DDR_DQ18_D14 DQL2 VSS_9
AA18 N5 F8 P9 F8 P9
DDR0_DQS[3] M0_DDR_DQS3_D14 DDR1_A[1] M1_DDR_A1_D14 M0_DDR_DQ3_D14 DQL3 VSS_10 M0_DDR_DQ19_D14 DQL3 VSS_10
AB18 J5 H3 T1 H3 T1
DDR0_DQS_N[3] M0_DDR_DQS_N3_D14 DDR1_A[2] M1_DDR_A2_D14 M0_DDR_DQ4_D14 DQL4 VSS_11 M0_DDR_DQ20_D14 DQL4 VSS_11
G5 H8 T9 H8 T9
DDR1_A[3] M1_DDR_A3_D14 M0_DDR_DQ5_D14 DQL5 VSS_12 M0_DDR_DQ21_D14 DQL5 VSS_12
AB10 T4 G2 G2
DDR0_DM[0] M0_DDR_DM0_D14 DDR1_A[4] M1_DDR_A4_D14 M0_DDR_DQ6_D14 DQL6 M0_DDR_DQ22_D14 DQL6
AB7 H4 H7 H7
DDR0_DM[1] M0_DDR_DM1_D14 DDR1_A[5] M1_DDR_A5_D14 M0_DDR_DQ7_D14 DQL7 M0_DDR_DQ23_D14 DQL7
AB19 R4 B1 B1
DDR0_DM[2] M0_DDR_DM2_D14 DDR1_A[6] M1_DDR_A6_D14 VSSQ_1 VSSQ_1
AB16 H5 D7 B9 D7 B9
DDR0_DM[3] M0_DDR_DM3_D14 DDR1_A[7] M1_DDR_A7_D14 M0_DDR_DQ8_D14 DQU0 VSSQ_2 M0_DDR_DQ24_D14 DQU0 VSSQ_2
R5 C3 D1 C3 D1
DDR1_A[8] M1_DDR_A8_D14 M0_DDR_DQ9_D14 DQU1 VSSQ_3 M0_DDR_DQ25_D14 DQU1 VSSQ_3
AA5 M0_DDR_DQ0_D14 K5 C8 D8 C8 D8
DDR0_DQ[0] DDR1_A[9] M1_DDR_A9_D14 M0_DDR_DQ10_D14 DQU2 VSSQ_4 M0_DDR_DQ26_D14 DQU2 VSSQ_4
AA12 M0_DDR_DQ1_D14 U4 C2 E2 C2 E2
DDR0_DQ[1] DDR1_A[10] M1_DDR_A10_D14 M0_DDR_DQ11_D14 DQU3 VSSQ_5 M0_DDR_DQ27_D14 DQU3 VSSQ_5
Y4 M0_DDR_DQ2_D14 P4 A7 E8 A7 E8
DDR0_DQ[2] DDR1_A[11] M1_DDR_A11_D14 M0_DDR_DQ12_D14 DQU4 VSSQ_6 M0_DDR_DQ28_D14 DQU4 VSSQ_6
Y11 M0_DDR_DQ3_D14 N4 A2 F9 A2 F9
DDR0_DQ[3] DDR1_A[12] M1_DDR_A12_D14 M0_DDR_DQ13_D14 DQU5 VSSQ_7 M0_DDR_DQ29_D14 DQU5 VSSQ_7
AB4 M0_DDR_DQ4_D14 K4 B8 G1 B8 G1
DDR0_DQ[4] DDR1_A[13] M1_DDR_A13_D14 M0_DDR_DQ14_D14 DQU6 VSSQ_8 M0_DDR_DQ30_D14 DQU6 VSSQ_8
AB12 M0_DDR_DQ5_D14 P5 A3 G9 A3 G9
DDR0_DQ[5] DDR1_A[14] M0_DDR_DQ15_D14 DQU7 VSSQ_9 M0_DDR_DQ31_D14 DQU7 VSSQ_9
AA4 M0_DDR_DQ6_D14 M5
DDR0_DQ[6] DDR1_A[15]
Y12 M0_DDR_DQ7_D14
DDR0_DQ[7]
AA11 M0_DDR_DQ8_D14 G4
DDR0_DQ[8] DDR1_BA[0] M1_DDR_BA0_D14
AA6 M0_DDR_DQ9_D14 T5
DDR0_DQ[9] DDR1_BA[1] M1_DDR_BA1_D14
Y10 M0_DDR_DQ10_D14 L4
DDR0_DQ[10] DDR1_BA[2] M1_DDR_BA2_D14
Y5 M0_DDR_DQ11_D14
DDR0_DQ[11]
Y9 M0_DDR_DQ12_D14 T3 IC12100
DDR0_DQ[12] DDR1_U_CK M1_U_CLK_D14
H5TQ1G63EFR-PBC
M1_DDR_VREFCA_D14 IC12102 M1_1_DDR_VREFCA_D14
AB6 M0_DDR_DQ13_D14 T2
DDR0_DQ[13] DDR1_U_CK_N M1_U_CLKN_D14 H5TQ1G63EFR-PBC
AA10 M0_DDR_DQ14_D14 G3
DDR0_DQ[14] DDR1_D_CK M1_D_CLK_D14
Y6 M0_DDR_DQ15_D14 G2 M1_1_DDR_VREFDQ_D14
DDR0_DQ[15] DDR1_D_CK_N M1_D_CLKN_D14 DDR3 M1_DDR_VREFDQ_D14
AA14 M0_DDR_DQ16_D14 M4
M1_DDR_CKE_D14 M1_DDR_A0_D14
N3 M8
N3
DDR3 M8
DDR0_DQ[16]
Y20
DDR1_CKE
P7
A0 1Gbit VREFCA
M1_DDR_A0_D14 A0 1Gbit VREFCA
M0_DDR_DQ17_D14 M1_DDR_A1_D14 P7
DDR0_DQ[17] A1 (x16)
Y13 E5 P3 M1_DDR_A1_D14 A1
DDR0_DQ[18]
M0_DDR_DQ18_D14
DDR1_ODT M1_DDR_ODT_D14 M1_DDR_A2_D14 A2 P3 (x16)
AA21 M0_DDR_DQ19_D14 E4 N2 H1 M1_DDR_A2_D14 A2
DDR0_DQ[19] DDR1_RAS_N M1_DDR_RASN_D14 M1_DDR_A3_D14 A3 VREFDQ N2 H1
AB13 M0_DDR_DQ20_D14 F4 P8 M1_DDR_A3_D14 A3 VREFDQ
DDR0_DQ[20] DDR1_CAS_N M1_DDR_CASN_D14 M1_DDR_A4_D14 A4 P8
AB21 M0_DDR_DQ21_D14 F5 P2 VDDC15_D14 M1_DDR_A4_D14 A4
DDR0_DQ[21] DDR1_WE_N M1_DDR_WEN_D14 M1_DDR_A5_D14 A5 R12126 P2 VDDC15_D14
AA13 M0_DDR_DQ22_D14 R8 L8 M1_DDR_A5_D14 A5 R12128
DDR0_DQ[22] M1_DDR_A6_D14 A6 ZQ R8 L8
Y21 M0_DDR_DQ23_D14 J4 R2 240 M1_DDR_A6_D14 A6 ZQ
DDR0_DQ[23] DDR1_RST_N M1_DDR_RESET_N_D14 M1_DDR_A7_D14 A7 1% R2 240
AA20 M0_DDR_DQ24_D14 T8 M1_DDR_A7_D14 A7 1%
DDR0_DQ[24] M1_DDR_A8_D14 A8 T8
AA15 M0_DDR_DQ25_D14 U5 240 R12123 R3 B2 M1_DDR_A8_D14 A8
DDR0_DQ[25] DDR1_ZQ_CALIB M1_DDR_A9_D14 A9 VDD_1 R3 B2
Y19 M0_DDR_DQ26_D14 1% L7 D9 M1_DDR_A9_D14 A9 VDD_1
DDR0_DQ[26] M1_DDR_A10_D14 A10/AP VDD_2 L7 D9
Y14 M0_DDR_DQ27_D14 F2 R7 G7 M1_DDR_A10_D14 A10/AP VDD_2
DDR0_DQ[27] DDR1_DQS[0] M1_DDR_DQS0_D14 M1_DDR_A11_D14 A11 VDD_3 R7 G7
Y18 M0_DDR_DQ28_D14 F3 N7 K2 M1_DDR_A11_D14 A11 VDD_3
DDR0_DQ[28] DDR1_DQS_N[0] M1_DDR_DQS_N0_D14 M1_DDR_A12_D14 A12/BC VDD_4 N7 K2
AB15 M0_DDR_DQ29_D14 H2 T3 K8 M1_DDR_A12_D14 A12/BC VDD_4
DDR0_DQ[29] DDR1_DQS[1] M1_DDR_DQS1_D14 M1_DDR_A13_D14 NC_7 VDD_5 T3 K8
AA19 M0_DDR_DQ30_D14 H1 N1 M1_DDR_A13_D14 NC_7 VDD_5
DDR0_DQ[30] DDR1_DQS_N[1] M1_DDR_DQS_N1_D14 VDD_6 N1
Y15 M0_DDR_DQ31_D14 R2 M7 N9 VDD_6
DDR0_DQ[31] DDR1_DQS[2] M1_DDR_DQS2_D14 NC_5 VDD_7 M7 N9
R3 R1 NC_5 VDD_7
DDR1_DQS_N[2] M1_DDR_DQS_N2_D14 VDD_8 R1
U2 M2 R9 VDD_8
DDR1_DQS[3] M1_DDR_DQS3_D14 M1_DDR_BA0_D14 BA0 VDD_9 M2 R9
U1 N8 M1_DDR_BA0_D14 BA0 VDD_9
DDR1_DQS_N[3] M1_DDR_DQS_N3_D14 M1_DDR_BA1_D14 BA1 N8
M3 M1_DDR_BA1_D14 BA1
M1_DDR_BA2_D14 BA2 M3
J1 A1 M1_DDR_BA2_D14 BA2
DDR1_DM[0] M1_DDR_DM0_D14 VDDQ_1 A1
F1 J7 A8 VDDQ_1
DDR1_DM[1] M1_DDR_DM1_D14 M1_D_CLK_D14 CK VDDQ_2 J7 A8
V1 K7 C1 M1_U_CLK_D14 CK VDDQ_2
DDR1_DM[2] M1_DDR_DM2_D14 M1_D_CLKN_D14 CK VDDQ_3 K7 C1
R1 K9 C9 M1_U_CLKN_D14 CK VDDQ_3
DDR1_DM[3] M1_DDR_DM3_D14 M1_DDR_CKE_D14 CKE VDDQ_4 K9 C9
D2 M1_DDR_CKE_D14 CKE VDDQ_4
VDDC15_D14 VDDQ_5 D2
M1_DDR_CKE_D14 D2 M1_DDR_DQ0_D14 L2 E9 VDDQ_5
DDR1_DQ[0] CS VDDQ_6 L2 E9
L2 M1_DDR_DQ1_D14 K1 F1 CS VDDQ_6
DDR1_DQ[1] M1_DDR_ODT_D14 ODT VDDQ_7 K1 F1
R12101 R12107 C3 M1_DDR_DQ2_D14 J3 H2 C12108 0.1uF M1_DDR_ODT_D14 ODT VDDQ_7
DDR1_DQ[2] M1_DDR_RASN_D14 RAS VDDQ_8 J3 H2 C12112 0.1uF
10K 10K K3 M1_DDR_DQ3_D14 K3 H9 C12109 0.1uF M1_DDR_RASN_D14 RAS VDDQ_8
DDR1_DQ[3] M1_DDR_CASN_D14 CAS VDDQ_9 K3 H9 C12113 0.1uF
C1 M1_DDR_DQ4_D14 L3 M1_DDR_CASN_D14 CAS VDDQ_9
DDR1_DQ[4] M1_DDR_WEN_D14 WE L3
M1_DDR_RESET_N_D14 L1 M1_DDR_DQ5_D14 J1 M1_DDR_WEN_D14 WE
DDR1_DQ[5] NC_1 J1
C2 M1_DDR_DQ6_D14 T2 J9 NC_1
DDR1_DQ[6] M1_DDR_RESET_N_D14 RESET NC_2 T2 J9
L3 M1_DDR_DQ7_D14 L1 M1_DDR_RESET_N_D14 RESET NC_2
DDR1_DQ[7] NC_3 L1
K2 M1_DDR_DQ8_D14 L9 NC_3
DDR1_DQ[8] NC_4 L9
M1_D_CLK_D14 M1_U_CLK_D14 E2 M1_DDR_DQ9_D14 F3 T7 NC_4
DDR1_DQ[9] M1_DDR_DQS0_D14 DQSL NC_6 F3 T7
J3 G3 M1_DDR_DQS2_D14 DQSL NC_6
R12100
R12104
M1_DDR_DQ10_D14 M1_DDR_DQS_N0_D14 G3
100
100
DDR1_DQ[10] DQSL
D3 M1_DDR_DQ11_D14 M1_DDR_DQS_N2_D14 DQSL
DDR1_DQ[11]
H3 M1_DDR_DQ12_D14 C7 A9
DDR1_DQ[12] M1_DDR_DQS1_D14 DQSU VSS_1 C7 A9
E1 M1_DDR_DQ13_D14 B7 B3 M1_DDR_DQS3_D14 DQSU VSS_1
M1_D_CLKN_D14 M1_U_CLKN_D14 DDR1_DQ[13] M1_DDR_DQS_N1_D14 DQSU VSS_2 B7 B3
J2 M1_DDR_DQ14_D14 E1 M1_DDR_DQS_N3_D14 DQSU VSS_2
DDR1_DQ[14] VSS_3 E1
E3 M1_DDR_DQ15_D14 E7 G8 VSS_3
DDR1_DQ[15] M1_DDR_DM0_D14 DML VSS_4 E7 G8
VDDC15_D14 N2 M1_DDR_DQ16_D14 D3 J2 M1_DDR_DM2_D14 DML VSS_4
VDDC15_D14 DDR1_DQ[16] M1_DDR_DM1_D14 DMU VSS_5 D3 J2
VDDC15_D14 W3 J8 M1_DDR_DM3_D14 DMU VSS_5
VDDC15_D14 M1_DDR_DQ17_D14 J8
DDR1_DQ[17] VSS_6
M1_1_DDR_VREFCA_D14 M3 M1_DDR_DQ18_D14 E3 M1 VSS_6
M1_1_DDR_VREFDQ_D14 DDR1_DQ[18] M1_DDR_DQ0_D14 DQL0 VSS_7 E3 M1
M1_DDR_VREFCA_D14 Y2 F7 M9 M1_DDR_DQ16_D14 DQL0 VSS_7
R12105
M1_DDR_VREFDQ_D14 M1_DDR_DQ19_D14 M1_DDR_DQ1_D14 F7 M9
DDR1_DQ[19] DQL1 VSS_8
R12102
R12115
M1 F2 P1 M1_DDR_DQ17_D14
1K 1%
DQL1 VSS_8
R12109
M1_DDR_DQ20_D14 M1_DDR_DQ2_D14 F2 P1
1K 1%
DDR1_DQ[20] DQL2 VSS_9
1K 1%
Y1 F8 P9 M1_DDR_DQ18_D14
1K 1%
M1_DDR_DQ21_D14 DQL2 VSS_9
DDR1_DQ[21] M1_DDR_DQ3_D14 DQL3 VSS_10 F8 P9
M2 M1_DDR_DQ22_D14 H3 T1 M1_DDR_DQ19_D14 DQL3 VSS_10
DDR1_DQ[22] M1_DDR_DQ4_D14 DQL4 VSS_11 H3 T1
Y3 M1_DDR_DQ23_D14 H8 T9 M1_DDR_DQ20_D14 DQL4 VSS_11
DDR1_DQ[23] M1_DDR_DQ5_D14 DQL5 VSS_12 H8 T9
0.1uF
W2 G2 M1_DDR_DQ21_D14 DQL5 VSS_12
0.1uF
R12106
1%
OPT 0.1uF
M1_DDR_DQ24_D14 M1_DDR_DQ6_D14 G2
DDR1_DQ[24] DQL6
0.1uF
R12130
1%
R12116
1%
P2 H7 M1_DDR_DQ22_D14 DQL6
R12110
1%
M1_DDR_DQ25_D14 M1_DDR_DQ7_D14 H7
DDR1_DQ[25] DQL7
C12101
V3 B1 M1_DDR_DQ23_D14 DQL7
C12100
M1_DDR_DQ26_D14
C12104
B1
1K
DDR1_DQ[26] VSSQ_1
C12102
N3 D7 B9
OPT
1K
VSSQ_1
1K
M1_DDR_DQ27_D14 M1_DDR_DQ8_D14 D7 B9
OPT
OPT
1K
DDR1_DQ[27] DQU0 VSSQ_2
U3 M1_DDR_DQ28_D14 C3 D1 M1_DDR_DQ24_D14 DQU0 VSSQ_2
DDR1_DQ[28] M1_DDR_DQ9_D14 DQU1 VSSQ_3 C3 D1
P1 M1_DDR_DQ29_D14 C8 D8 M1_DDR_DQ25_D14 DQU1 VSSQ_3
DDR1_DQ[29] M1_DDR_DQ10_D14 DQU2 VSSQ_4 C8 D8
V2 M1_DDR_DQ30_D14 C2 E2 M1_DDR_DQ26_D14 DQU2 VSSQ_4
DDR1_DQ[30] M1_DDR_DQ11_D14 DQU3 VSSQ_5 C2 E2
P3 M1_DDR_DQ31_D14 A7 E8 M1_DDR_DQ27_D14 DQU3 VSSQ_5
DDR1_DQ[31] M1_DDR_DQ12_D14 DQU4 VSSQ_6 A7 E8
A2 F9 M1_DDR_DQ28_D14 DQU4 VSSQ_6
M1_DDR_DQ13_D14 DQU5 VSSQ_7 A2 F9
B8 G1 M1_DDR_DQ29_D14 DQU5 VSSQ_7
M1_DDR_DQ14_D14 DQU6 VSSQ_8 B8 G1
A3 G9 M1_DDR_DQ30_D14 DQU6 VSSQ_8
M1_DDR_DQ15_D14 DQU7 VSSQ_9 A3 G9
M1_DDR_DQ31_D14 DQU7 VSSQ_9
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-121-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. D14_DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+1.1V_VDD
R12204
10K
R12207
R12216
4.99K
1/16W
39K
R1
1%
1/16W
5%
1%
1/16W
91K
R12206
C12214
R12217
[EP]
GND2
GND1
NC_3
TRIP
1/16W
1000pF +12V
5.1K
VO
50V R2
1%
1/16W
27K
R12205
1%
R12222
1%
1/16W
20K
28
27
26
25
24
RF 1 23 FB
THERMAL
PGOOD 2 29 22 GND L12201
+1.1V_Bypass Cap +1.5V_Bypass Cap
R12201 1K EN 3 21 MODE IC12000
POWER_ON/OFF2_4 16V +1.1V_VDD_D14
0.1uF IC12200 LG1512D
VBST 4 20 VREG
TPS53513RVER
R12203
C12217 NC_1 +1.1V_VDD_D14 VDDC15_D14
5 19 VDD VDDC15_D14
4.7
C12213 R12200
2K J13 E10
SW_1 6 18 NC_2 AVDD11_HDMI0_1 VSS_26
J14 E11
0.1uF 1/16W C12221 C12223 AVDD11_HDMI0_2 VSS_27
16V SW_2 7 17 VIN_3 C12222 J11 E12
5% 1uF 10uF
10uF AVDD11_HDMI1_1 VSS_28
+1.1V_VDD_D14 10V 16V J12 E13
L12200 SW_3 8 16 VIN_2 16V AVDD11_HDMI1_2 VSS_29
8A
C12209 4.7uF
H9 E14
C12210 0.1uF
C12236 0.1uF
C12239 0.1uF
C12200 0.1uF
1uH
C12211 10uF
C12207 10uF
DVDD11_1 VSS_30
C12226 22uF
C12227 22uF
C12230 10uF
SW_4 VIN_1
C12267 0.1uF
C12268 0.1uF
J9 E15
C12233 1uF
9 15
C12202 10uF
C12255 0.1uF
C12258 0.1uF
22uF
C12201 10uF
22uF
DVDD11_2 VSS_31
J15 E16
R12202
10
11
12
13
14
DVDD11_3
1/10W
VSS_32
K9 E17
ZD12200
D12200
3.3
C12203 C12205 C12212 DVDD11_4 VSS_33
5%
C12220 K15 E18
2.5V
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
OPT
C12264
30V
DVDD11_5 VSS_34
C12250
22uF 22uF 22uF 2200pF L9 E19
50V DVDD11_6 VSS_35
L15 F6
C12215 DVDD11_7 VSS_36
M9 F7
470pF 4th layer DVDD11_8 VSS_37
50V 4th layer 4th layer M15 F9
VDDC11_XTAL_D14 DVDD11_9 VSS_38
N15 F10
DVDD11_10 VSS_39
VREF_M0_0_D14 VREF_M1_0_D14 P9 F11
L12203 DVDD11_11 VSS_40
BLM18PG121SN1D P10 F14
DVDD11_12 VSS_41
P11 F15
1uF
DVDD11_13 VSS_42
R12208 R12210 R12212 R12214 P12 F16
VDDC11_XTAL_D14 DVDD11_14 VSS_43
1K 1% 1K 1% P13 F17
1K 1% 1K 1% DVDD11_15 VSS_44
P15 F18
C12216
DVDD11_16 VSS_45
C12251 C12265 B4 F19
0.1uF 0.1uF DVDD11_PLL VSS_46
A4 G6
OPT OPT VDDC15_D14 DVDD11_XTAL VSS_47
G18
VSS_48
T9 G19
DVDD15_DDR0_1 VSS_49
T10 H6
DVDD15_DDR0_2 VSS_50
T11 H18
+12V DVDD15_DDR0_3 VSS_51
VREF_M0_1_D14 VREF_M1_1_D14 T12 H19
DVDD15_DDR0_4
+1.5V VDDC15_D14
R12211
T13
T14
DVDD15_DDR0_5
DVDD15_DDR0_6
VSS_52
VSS_53
VSS_54
J6
J10
L12213 R12209 R12213 R12215 T15 J18
POWER_ON/OFF2_3 DCDC_TI VDDC15_D14 DVDD15_DDR0_7 VSS_55
BLM18PG121SN1D IC12201-*1 1K 1% 1K 1% T16 J19
1K 1% 1K 1% DVDD15_DDR0_8 VSS_56
TPS54327DDAR [EP]GND
T17 K6
DVDD15_DDR0_9 VSS_57
EN
1 8
VIN
C12252 C12266 G7 K10
0.1uF 0.1uF DVDD15_DDR1_1 VSS_58
THERMAL
VFB VBST
H7 K11
9
2 7 OPT OPT DVDD15_DDR1_2 VSS_59
C12277
10uF
C12204
0.1uF VREG5
3 6
SW
+3.3V_Bypass Cap J7
DVDD15_DDR1_3 VSS_60
K12
DCDC_ROHM K7 K13
16V DVDD15_DDR1_4 VSS_61
IC12201 SS
4 5
GND
L7 K14
R12221 DVDD15_DDR1_5 VSS_62
BD9D320EFJ [EP]FIN M7 K18
10K DVDD15_DDR1_6 VSS_63
N7 L6
DVDD15_DDR1_7 VSS_64
P7 L10
EN VIN DVDD15_DDR1_8 VSS_65
1 8 +3.3V_NORMAL VDD33_D14 R7 L11
16V DVDD15_DDR1_9 VSS_66
THERMAL
0.1uF VDD25_D14 L12
R12218 R12219 FB BOOT C12281 VSS_67
H13 L13
9
2 7 L12205 AVDD25_HDMI0_1 VSS_68
H14 L14
R1 18K 3.6K L12214 BLM18PG121SN1D
AVDD25_HDMI0_2 VSS_69
1% 1% 2.2uH H11 L18
+2.5V_Bypass Cap
C12228 0.1uF
VREG SW AVDD25_HDMI1_1 VSS_70
C12224 10uF
C12206 10uF
3 6 H12 M6
22uF
C12278 AVDD25_HDMI1_2 VSS_71
100pF NR5040T2R2N VDD25_XTAL_D14 H15 M10
50V DVDD25_OTP VSS_72
SS GND B5 M11
1.0V_DCDC_TI 4
3A 5 C12282 C12283 ZD12201 DVDD25_PLL VSS_73
C12218
22uF 22uF VDD33_D14 M12
10V 2.5V +2.5V_Normal
C12280-*1 R12220 10V VSS_74
OPT F8 M13
3300pF C12279 C12280 VDD25_D14 DVDD33_1 VSS_75
22K F12 M14
50V 1uF 2200pF
1% DVDD33_2 VSS_76
10V 50V F13 M18
1.0V_DCDC_ROHM DVDD33_3 VSS_77
H10 N6
R2 VDD33_XTAL_D14 4th layer L12210 DVDD33_4 VSS_78
H16 N9
BLM18PG121SN1D DVDD33_5 VSS_79
J16 N10
Vout=0.765*(1+R1/R2)=1.516V L12206 DVDD33_6 VSS_80
22uF
C12259 0.1uF
K16 N11
C12208 10uF
BLM18PG121SN1D
C12256 10uF
DVDD33_7 VSS_81
L16 N12
C12225 0.1uF
C12219 4.7uF
DVDD33_8 VSS_82
M16 N13
C12253
DVDD33_9 VSS_83
VDD33_XTAL_D14 N16 N14
DVDD33_10 VSS_84
P16 N18
DVDD33_11 VSS_85
VREF_M0_0_D14 T8 P6
DVDD33_12 VSS_86
A5 P14
VREF_M0_1_D14 DVDD33_XTAL VSS_87
P18
VREF_M1_0_D14 VSS_88
VDD25_XTAL_D14 4th layer AB3 R6
VREF_M1_1_D14 VREF0_DDR0 VSS_89
AA22 R18
L12209 VREF1_DDR0 VSS_90
B1 R19
BLM18PG121SN1D VREF0_DDR1 VSS_91
AA1 R20
VREF1_DDR1 VSS_92
C12257 0.1uF
4.7uF
T6
VSS_93
T7
VSS_94
A2 T18
VSS_1 VSS_95
A14 T19
C12254
VSS_2 VSS_96
B2 U6
VSS_3 VSS_97
C4 U7
VSS_4 VSS_98
C5 U8
VSS_5 VSS_99
D4 U9
VSS_6 VSS_100
D5 U10
VSS_7 VSS_101
D6 U11
VSS_8 VSS_102
D7 U12
VSS_9 VSS_103
D8 U13
VSS_10 VSS_104
D9 U14
VSS_11 VSS_105
D10 U15
VSS_12 VSS_106
D11 U16
VSS_13 VSS_107
D12 U17
VSS_14 VSS_108
D13 U18
VSS_15 VSS_109
D14 U19
VSS_16 VSS_110
D15 V4
VSS_17 VSS_111
D16 V5
VSS_18 VSS_112
D17 V19
VSS_19 VSS_113
D18 W4
VSS_20 VSS_114
D19 W5
VSS_21 VSS_115
E6 W19
VSS_22 VSS_116
E7 AA2
VSS_23 VSS_117
E8 AA3
VSS_24 VSS_118
E9 AB2
VSS_25 VSS_119
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-122-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
UB85/95/UC89 only +3.3V_NORMAL
L2100
BLM18PG121SN1D
VDDP
4st Layer
C2106 C2111 C2120 C2128 C2134 C2139 C2143 C2145 C13314 C13315
10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF
10V 10V 10V 10V 16V 16V 16V 16V 16V 10V
AVDD_PLL 4st Layer
Close to Chip side
L2101
BLM18PG121SN1D
C2105 C2109 C13302 C2151
10uF 0.1uF 0.1uF 10uF
10V 16V 16V 10V
IC2500
LGE7411(URSA9)
IC2500 Close to Chip side
AG2 LGE7411(URSA9) AVDD_MOD
TXB0N/TX5N
AG1
RB0N 4th Layer
TXB0P/TX5P RB0P L2102
AH3
TXB1N/TX4N RB1N BLM18PG121SN1D
AH1
TXB1P/TX4P RB1P
AH2
TXB2N/TX3N RB2N
AJ3
TXB2P/TX3P RB2P C2104 C2110 C2119 C2127 C2133 C2138 C2142 C13306
AJ2
TXBCLKN/TX2N
AK2
RBCKN 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
TXBCLKP/TX2P
AK1
RBCKP
AM17 10V 10V 10V 16V 16V 16V 16V 16V
TXB3N/TX1N RB3N VX1_0-
AL1 AK17
TXB3P/TX1P RB3P VX1_0+
AM2 AL18
TXB4N/TX0N
AL2
RB4N VX1_1-
AK18 D1
TXB4P/TX0P RB4P VX1_1+
AM19
HDMI_CLK+_URSA9_0 HDMI_RXCP_0
VX1_2-
D3
AL19 HDMI_CLK-_URSA9_0 HDMI_RXCN_0
TXA0N/TX11N
AK3
RC0N
VX1_2+
VX1_3-
AL20
HDMI_RX0+_URSA9_0
E3
HDMI_RX0P_0
Close to Chip side
AL3 AM20 D2
TXA0P/TX11P RC0P VX1_3+
AK4 AK22 0.1uF C13008 TXDBN7_L HDMI_RX0-_URSA9_0 HDMI_RX0N_0
TXA1N/TX10N AL4
RC1N VX1_4-
AL21 F3
0.1uF C13009 TXDBP7_L
TXA1P/TX10P AM4
RC1P VX1_4+
AK23
HDMI_RX1+_URSA9_0 HDMI_RX1P_0 VDDC VDDC 4th Layer
TXA2N/TX9N RC2N VX1_5-
0.1uF C13010 TXDBN6_L E2
AK5 AM22 0.1uF C13011 TXDBP6_L HDMI_RX1-_URSA9_0 HDMI_RX1N_0
TXA2P/TX9P AM5
RC2P VX1_5+
AK24 F1
0.1uF C13012 TXDBN5_L
TXACLKN/TX8N AL5
RCCKN VX1_6-
AL23
HDMI_RX2+_URSA9_0 HDMI_RX2P_0
TXACLKP/TX8P RCCKP VX1_6+
0.1uF C13013 TXDBP5_L F2
TXA3N/TX7N
AK6
RC3N VX1_7-
AL25 0.1uF C13014 TXDBN4_L HDMI_RX2-_URSA9_0 HDMI_RX2N_0
AL6 AK25 0.1uF C13015 TXDBP4_L
TXA3P/TX7P
AK7
RC3P VX1_7+
AM26 C2100 C2101 C2114 C2122 C2132 C2137 C2144 C2146 C2147 C2148 C2149 C13307 C2150 C2107
0.1uF C13016 TXDBN3_L
TXA4N/TX6N AL7
RC4N VX1_8-
AK26 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
0.1uF C13017 TXDBP3_L
TXA4P/TX6P RC4P VX1_8+ 10V
AL27 0.1uF C13018 TXDBN2_L 10V 10V 10V 10V 10V 10V 16V 16V 16V 16V 16V 16V 10V
VX1_9-
AK27 0.1uF C13019 TXDBP2_L
VX1_9+
AM7 AM28 0.1uF C13020 TXDBN1_L
TXD0N/TX17N RD0N VX1_10-
AK8 AL28 0.1uF C13021 TXDBP1_L
TXD0P/TX17P RD0P VX1_10+
AM8 AL29 0.1uF C13022 TXDBN0_L AVDDL_MOD
TXD1N/TX16N RD1N VX1_11-
AL8 AM29 0.1uF C13023 TXDBP0_L
TXD1P/TX16P
TXD2N/TX15N
AK9
AL9
RD1P
RD2N
VX1_11+
VX1_12-
AM31
AL30
0.1uF
0.1uF
C13024
C13025
TXDAN7_L
L2104
4th Layer
Close to Chip side
TXDAP7_L BLM18PG121SN1D
TXD2P/TX15P RD2P VX1_12+
AK10 AL32 0.1uF C13026 TXDAN6_L
TXDCLKN/TX14N
AL10
RDCKN VX1_13-
AL31 G1
0.1uF C13027 TXDAP6_L
TXDCLKP/TX14P
AM10
RDCKP VX1_13+
AK31
HDMI_CLK+_URSA9_1 HDMI_RXCP_1
TXD3N/TX13N RD3N VX1_14-
0.1uF C13028 TXDAN5_L G3 C2115 C2123 C13311 C13305 C2154
AK11 AK32 0.1uF C13029 TXDAP5_L HDMI_CLK-_URSA9_1 HDMI_RXCN_1 0.1uF 0.1uF 10uF 10uF
TXD3P/TX13P
AM11
RD3P VX1_14+
AJ30 H3 0.1uF
0.1uF C13030 TXDAN4_L 16V
TXD4N/TX12N
AL11
RD4N VX1_15-
AJ31
HDMI_RX0+_URSA9_1 HDMI_RX0P_1 16V 10V 16V 10V
TXD4P/TX12P RD4P VX1_15+
0.1uF C13031 TXDAP4_L G2
AH30 0.1uF C13064 TXDAN3_L HDMI_RX0-_URSA9_1 HDMI_RX0N_1
VX1_16-
AH32 J3
0.1uF C13065 TXDAP3_L
AK12
VX1_16+
AG30
HDMI_RX1+_URSA9_1 HDMI_RX1P_1
TXC0N/TX23N RE0N VX1_17-
0.1uF C13066 TXDAN2_L H2
TXC0P/TX23P
AL12
AK13
RE0P VX1_17+
AG31
AE31
0.1uF
0.1uF
C13067
C13068
TXDAP2_L
TXDAN1_L
HDMI_RX1-_URSA9_1
J1
HDMI_RX1N_1
AVDDL_DRV
Close to Chip side
TXC1N/TX22N
AL13
RE1N VX1_18-
AF30
HDMI_RX2+_URSA9_1 HDMI_RX2P_1
TXC1P/TX22P RE1P VX1_18+
0.1uF C13069 TXDAP1_L J2 4th Layer
AM13
RE2N VX1_19-
AD32 0.1uF C13070 TXDAN0_L HDMI_RX2-_URSA9_1 HDMI_RX2N_1
TXC2N/TX21N L2105
AK14 AE30 0.1uF C13071 TXDAP0_L BLM18PG121SN1D
TXC2P/TX21P RE2P VX1_19+
AM14
TXCCLKN/TX20N RECKN
AL14
TXCCLKP/TX20P RECKP
AK15 AH29 C2116 C2124 C13310 C13304 C2153
TXC3N/TX19N RE3N VX1_HTDPN HTPDAn
AL15
RE3P VX1_LOCKN
AG29 0.1uF 0.1uF 10uF 0.1uF 10uF
TXC3P/TX19P
AK16 16V
TXC4N/TX18N RE4N R1938
16V 10V 16V 10V
AL16 10K
TXC4P/TX18P RE4P
URSA_TX_HTPD_pulldown
AE2
VBY1_RXM[0]
HDMI_TX_DDC_CLK
DVDD_DDR Close to Chip side
AE1 HDMI_TX_DDC_SDA 4th Layer
VBY1_RXP[0]
AD2
VBY1_RXM[1] LOCKAn L2106
AE3 BLM18PG121SN1D
VBY1_RXP[1] R1996 22 N4
AC2
VBY1_RXM[2] HDMI_TX_DDC_CLK HDMITX_SCL
AD3 R1997 22 M4
VBY1_RXP[2] HDMI_TX_DDC_SDA C2117 C2125 C13312 C2152 C13303 C13313
AC3 HDMITX_SDA
AC1
VBY1_RXM[3] +3.3V_NORMAL N1 0.1uF 0.1uF 4.7uF 10uF 0.1uF 4.7uF
HDMI OUTPUT to H13
VBY1_RXP[3] HDMI_CLK+ HDMI_TXCP 16V 10V 10V 16V 10V
P1 16V
AB2 HDMI_CLK- HDMI_TXCN
AB1
VBY1_RXM[4] N3
AA2
VBY1_RXP[4] HDMI_RX0+ HDMI_TX0P
VBY1_RXM[5]
N2
AB3 HDMI_RX0- HDMI_TX0N
R1952
Y2
VBY1_RXP[5] M3
Close to Chip side
22
AA3
VBY1_RXM[6] HDMI_RX1+ HDMI_TX1P
VBY1_RXP[6]
M2
Y3 HDMI_RX1- HDMI_TX1N AVDDL_HDMI_TX_RX
Y1
VBY1_RXM[7] L1
HDMI_RX2+ HDMI_TX2P
SML-512UW
VBY1_RXP[7]
LD1900
L2 L2107
W2
VBY1_RXM[8]
HDMI_RX2- HDMI_TX2N BLM18PG121SN1D
W1 R1939
VBY1_RXP[8] 10K
V2
W3
VBY1_RXM[9] C2118 C2126 C2131 C13309
R1943
VBY1_RXP[9] 0.1uF 0.1uF
U2 0.1uF 10uF
220
VBY1_RXM[10]
V3 16V 16V 16V 10V
VBY1_RXP[10]
U3
VBY1_RXM[11]
U1
VBY1_RXP[11] E Q1901
MMBT3906(NXP)
GND Connection at Vx1 41pin wafer
B
AVDDL_LVDSRX
C R12900 0
GND_Vx1_2
Non_LGD_Module L13300
(pin 8) BLM18PG121SN1D
C13300 C13301 C13308
0.1uF 0.1uF 10uF
R12901 0 16V 16V 10V
GND_Vx1
(pin 5,11,14) Non_UB95
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-128-02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_LVDS INPUT
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+1.8V
+3.3V_NORMAL
+1.8V Vx1 LOCKAn/HTPDn
[51P Vx1 IC13000
AZ1117EH-ADJTRG1
output wafer]
R1505
R1504
4.7K
1.5K
IN OUT
R13035
ADJ/GND
1
75
R13036
51pin_Wafer
P13000 Q1404 [41P Vx1
G
FI-RE51S-HF-J-R1500 AO3438
output wafer] C13034 C13035
33
R13042
LOCKAn 10uF 10uF
S
D
LOCKn_IN 10V 10V
1
41pin_Wafer
2 TXDAP7_L +1.8V P13001
3 FI-RE41S-HF-J-R1500
TXDAN7_L
4
URSA_TX_HTPD_Pullup
URSA_TX_HTPD_Pullup
+3.3V_NORMAL
5 TXDAP6_L 1
6 TXDAN6_L 2 D9_I2C_SCL
R209 R211 R222
7 4.7K 1.5K 10K
3 D9_I2C_SDA
URSA_TX_HTPD_Pullup
8 TXDAP5_L 4 Not Used Net (UB85/95/UC89)
9
G
TXDAN5_L 5 GND_Vx1 TXDBP11_L
10
HTPDAn 6 TXDBP11_L TXDBN11_L
S
D
11 HTPDn_IN R221
TXDAP4_L 0 Q203 7
URSA_TX_HTPD_Pullup AO3438 TXDBN11_L
12 URSA_TX_HTPD_Pullup TXDBP10_L
TXDAN4_L 8 GND_Vx1_2
13 TXDBN10_L
9 TXDBP10_L
14 TXDAP3_L R220 TXDBP9_L
0 10 TXDBN10_L
15 OPT
TXDAN3_L 11 TXDBN9_L
16
12 TXDBP9_L TXDBP8_L
17 TXDAP2_L 13 TXDBN9_L TXDBN8_L
18 TXDAN2_L +3.3V_NORMAL 14
L/D_EN(Pin30) GND_Vx1
19 - T-Con L/D Function
R13034 15 TXDBP8_L
10K HIGH : Enable GND_Vx1_2
20 TXDAP1_L LOW or NC : Disable
OPT 16 TXDBN8_L
+3.3V_NORMAL *LGD_120Hz: T240 module (UB98/95,D9)
21 R13037 0
TXDAN1_L L_DIM_EN 17
Non_AUO_Module
22 R13003 18 TXDBP7_L
10K R13007
23 D9_I2C_SCL
TXDAP0_L OPT 10K 19 TXDBN7_L
Non_AUO_Module
D9_I2C
+3.3V_NORMAL
24
R13014 0
TXDAN0_L 20
TCON_I2C_EN
25
R13004 R13018 21 TXDBP6_L
G
10K 4.7K
26 LOCKn_IN LGD_Module
22 TXDBN6_L
R13013 0 R13061 0
27 HTPDn_IN I2C_SCL1
S
23
D
R13011 10K NON_D9_I2C Non_AUO_Module
28 EL_VDD_DETECT_22V Q13004
2N7002A 24 TXDBP5_L
Non_INX_Module
29 R13055
25 TXDBN5_L
30 L13001 33 OPT
BLM18PG121SN1D 26
OPT *Pin31(BIT_SEL) +3.3V_NORMAL
31 HIGH or NC : 10Bit OLED D9_I2C_SDA
0
27 TXDBP4_L
D9_I2C
R13033 10K LOW : 8Bit
32 TCON_I2C_EN
R13017
R13019 28 TXDBN4_L
G
33 4.7K
29
R13012 0 R13062 0
34 I2C_SDA1
S
30
D
R13006 0 *Pin35(PCID) NON_D9_I2C Non_AUO_Module TXDBP3_L
35 3D_EN High:PCID enable Q13005
2N7002A 31 TXDBN3_L
3D_EN_LGD_120Hz Low or NC : PCID diable
36
R13059 32
37
33 OPT 33 TXDBP2_L
R13005 0 +3.3V_NORMAL
38 *Pin38
Non_LGD_60Hz: T120 module(UB85) 34 TXDBN2_L
Non_LGD_60Hz
39
35
R13044
40 10K
OPT 36 TXDBP1_L
R13001 0
41 INV_CTL R13016 0 37 TXDBN1_L
OLED R13002 0 Data_Format_1
42 Compensation_Done 38
Non_OLED & Non_AUO_Module
LGD_Module
Non_OLED & Non_AUO_Module
OLED
43
R13009 R13010 39
0 0 TXDBP0_L
44 R13045 40 TXDBN0_L
10K Data Input Format[1:0]
45 LGD_Module 41
*Mode 3 (4 Division)
46 - Data Format 0(Pin37) = Low
Data Format 1(Pin36) = High 42
47 +3.3V_NORMAL
*Mode 2 (2 Division)
48 - Data Format 0(Pin37) = High
Data Format 1(Pin36) = Low
49 R13040
10K
50 OPT
PANEL_VCC
51 R13015 0
Data_Format_0
L13000 LGD_Module
52 MLB-201209-0120P-N2
51pin_12V
C13032 C13033 R13041
10K
10uF 10uF LGD_Module
25V 25V
51pin_12V 51pin_12V
EL_VDD_DETECT_22V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-130-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Output_wafer
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
LGE7411(URSA9)
F14 H27 B_DDR3_A[0]
B_DDR3_A[0-15] DDR PHY VREF
A_DDR3_A[0] A_DDR3_A0 B_DDR3_A0
B13 G31 B_DDR3_A[1] +1.5V_U_DDR +1.5V_U_DDR
A_DDR3_A[1] A_DDR3_A1 B_DDR3_A1 U_MVREFCA_A0 U_MVREFCA_A1
E13 G28 B_DDR3_A[2]
A_DDR3_A[2] A_DDR3_A2 B_DDR3_A2
D13 G29 B_DDR3_A[3]
A_DDR3_A[3] A_DDR3_A3 B_DDR3_A3 DDR_VTT_URSA_1
C14 H30 B_DDR3_A[4]
A_DDR3_A[4] A_DDR3_A4 B_DDR3_A4 R13110 R13120
F13 G27 B_DDR3_A[5] 1K
A_DDR3_A[5] A_DDR3_A5 B_DDR3_A5 1%
1K IC2600
A_DDR3_A[6]
C13 G30 B_DDR3_A[6] 1%
H5TQ1G63EFR-RDC AR13100 AR13102 AR13104 AR13106 AR13108 AR13110 AR13112
IC2700
A_DDR3_A6 B_DDR3_A6
B10 D31 B_DDR3_A[7] U_MVREFCA_A0 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
A_DDR3_A[7] A_DDR3_A7 B_DDR3_A7 U_MVREFCA_A1
A12 F32 B_DDR3_A[8]
A_DDR3_A[8] A_DDR3_A8 B_DDR3_A8 R13111 C13202 C13210 R13121 C13222 C13230
C10 D30 B_DDR3_A[9]
1K
A_DDR3_A[9] A_DDR3_A9 B_DDR3_A9 0.1uF 1000pF 1K 0.1uF 1000pF N3 M8
A14 H32 B_DDR3_A[10] 1% 1% A_DDR3_A[0] A0 VREFCA N3 M8
A_DDR3_A[10] A_DDR3_A10 B_DDR3_A10 P7 A_DDR3_A[0] A0 VREFCA
B12 F31 B_DDR3_A[11] A_DDR3_A[1] A1 P7
A_DDR3_A[11] A_DDR3_A11 B_DDR3_A11 P3 A_DDR3_A[1] A1
F15 J27 B_DDR3_A[12] A_DDR3_A[2] A2 P3
A_DDR3_A[12] A_DDR3_A12 B_DDR3_A12 N2 H1 A_DDR3_A[2] A2
C11 E30 B_DDR3_A[13] A_DDR3_A[3] A3 VREFDQ N2 H1
A_DDR3_A[13] A_DDR3_A13 B_DDR3_A13 P8 A_DDR3_A[3] A3 VREFDQ
C12 F30 B_DDR3_A[14] A_DDR3_A[4] A4 P8
A_DDR3_A[14] A_DDR3_A14 B_DDR3_A14 P2 A_DDR3_A[4] A4
D17 L29 B_DDR3_A[15] A_DDR3_A[5] A5 P2
A_DDR3_A[15] A_DDR3_A15 B_DDR3_A15 R8 L8 R13126 240
A_DDR3_A[5] A5
E14 H28 A_DDR3_A[6] A6 ZQ R8 L8 R13134 240
A_DDR3_BA[0] A_DDR3_BA0 B_DDR3_BA0 B_DDR3_BA[0] R2 1%
A_DDR3_A[6] A6 ZQ
B14 H31 A_DDR3_A[7] A7 R2 1% +1.5V_U_DDR
A_DDR3_BA1 T8 +1.5V_U_DDR A_DDR3_A[7]
A_DDR3_BA[1] B_DDR3_BA1 B_DDR3_BA[1] A_DDR3_A[8] A7
E15 J28 A8 T8
A_DDR3_BA[2] A_DDR3_BA2 B_DDR3_BA2 B_DDR3_BA[2] R3 B2 A_DDR3_A[8] A8
A_DDR3_A[9] A9 VDD_1 R3 B2
L7 D9 A_DDR3_A[9] A9 VDD_1
E17 L28 A_DDR3_A[10] A10/AP VDD_2 L7 D9
A_DDR3_RASZ A_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ R7 G7 A_DDR3_A[10] A10/AP VDD_2
C17 L30 A_DDR3_A[11] A11 VDD_3 R7 G7
A_DDR3_CASZ A_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ N7 K2 A_DDR3_A[11] A11 VDD_3
C16 K30 A_DDR3_A[12] A12/BC VDD_4 N7 K2
A_DDR3_WEZ A_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ T3 K8 A_DDR3_A[12] A12/BC VDD_4
F17 L27 A_DDR3_A[13] NC_7 VDD_5 T3 K8
A_DDR3_ODT A_DDR3_ODT B_DDR3_ODT B_DDR3_ODT N1 A_DDR3_A[13] NC_7 VDD_5
C15 J30 VDD_6 N1
A_DDR3_CKE A_DDR3_CKE B_DDR3_CKE B_DDR3_CKE M7 N9 A_DDR3_A[14] VDD_6
B11 E31 A_DDR3_A[15] NC_5 VDD_7 M7 N9
A_DDR3_RESET A_DDR3_RESETB B_DDR3_RESETB B_DDR3_RESET R1 A_DDR3_A[15] NC_5 VDD_7
B16 K31 VDD_8 R1
A_DDR3_MCLK A_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK +1.5V_U_DDR M2 R9 VDD_8
A16 K32 A_DDR3_BA[0] BA0 VDD_9 M2 R9
A_DDR3_MCLKZ B_DDR3_MCLKZ +1.5V_U_DDR N8
A_DDR3_MCLKZ B_DDR3_MCLKZ U_MVREFCA_B0 U_MVREFCA_B1 A_DDR3_BA[0] BA0 VDD_9
C9 C30 A_DDR3_BA[1] BA1 +1.5V_U_DDR N8
M3 +1.5V_U_DDR
R13123R13122
A_DDR3_CSB1 A_DDR3_CSB1 B_DDR3_CSB1 B_DDR3_CSB1 A_DDR3_MCLK A_DDR3_BA[1] BA1
A9 C32 A_DDR3_BA[2] BA2 M3
56
A_DDR3_CSB2 A_DDR3_CSB2 B_DDR3_CSB2 B_DDR3_CSB2 C13233 A1 A_DDR3_BA[2] BA2
VDDQ_1 A1
A_DDR3_DQ[0-15] B_DDR3_DQ[0-15] R13108 0.01uF J7 A8 VDDQ_1
R13118
56
A_DDR3_DQ[0] D23 U29 B_DDR3_DQ[0] CK VDDQ_2 J7 A8
1K 1K K7 C1
A_DDR3_DQ0 B_DDR3_DQ0 A_DDR3_MCLK CK VDDQ_2
A_DDR3_DQ[1] A19 N32 B_DDR3_DQ[1] 1% 1% A_DDR3_MCLKZ CK VDDQ_3 K7 C1
A_DDR3_DQ1 B_DDR3_DQ1 K9 C9 A_DDR3_MCLKZ CK VDDQ_3
A_DDR3_DQ[2] E22 T28 B_DDR3_DQ[2] A_DDR3_CKE CKE VDDQ_4 K9 C9
A_DDR3_DQ2 B_DDR3_DQ2 D2 A_DDR3_CKE CKE VDDQ_4
A_DDR3_DQ[3] B18 M31 B_DDR3_DQ[3] VDDQ_5 D2
A_DDR3_DQ3 B_DDR3_DQ3 L2 E9 VDDQ_5
A_DDR3_DQ[4] C23 U30 B_DDR3_DQ[4] R13109 C13201 C13209 R13119 C13221 C13229 A_DDR3_CSB1 CS VDDQ_6 L2 E9
A_DDR3_DQ4 B_DDR3_DQ4 1K 0.1uF 1000pF 1K K1 F1 A_DDR3_CSB2 CS VDDQ_6
A_DDR3_DQ[5] C18 M30 B_DDR3_DQ[5] 0.1uF 1000pF A_DDR3_ODT ODT VDDQ_7 K1 F1
1% 1% J3 H2
A_DDR3_DQ5 B_DDR3_DQ5 A_DDR3_ODT ODT VDDQ_7
A_DDR3_DQ[6] B22 T31 B_DDR3_DQ[6] A_DDR3_RASZ RAS VDDQ_8 J3 H2
A_DDR3_DQ6 B_DDR3_DQ6 K3 H9 A_DDR3_RASZ RAS VDDQ_8
A_DDR3_DQ[7] A18 M32 B_DDR3_DQ[7] A_DDR3_CASZ CAS VDDQ_9 K3 H9
A_DDR3_DQ7 B_DDR3_DQ7 L3 A_DDR3_CASZ CAS VDDQ_9
A_DDR3_DQ[8] E19 N28 B_DDR3_DQ[8] A_DDR3_WEZ WE L3
A_DDR3_DQ8 B_DDR3_DQ8 J1 A_DDR3_WEZ WE
A_DDR3_DQ[9] B21 R31 B_DDR3_DQ[9] NC_1 J1
A_DDR3_DQ9 B_DDR3_DQ9 T2 J9 NC_1
A_DDR3_DQ[10] F18 M27 B_DDR3_DQ[10] A_DDR3_RESET RESET NC_2 T2 J9
A_DDR3_DQ10 B_DDR3_DQ10 L1 A_DDR3_RESET RESET NC_2
A_DDR3_DQ[11] C22 T30 B_DDR3_DQ[11] NC_3 L1
A_DDR3_DQ11 B_DDR3_DQ11 L9 NC_3
A_DDR3_DQ[12] D20 P29 B_DDR3_DQ[12] NC_4 L9
A_DDR3_DQ12 B_DDR3_DQ12 F3 T7 NC_4
A_DDR3_DQ[13] F22 T27 B_DDR3_DQ[13] A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14] F3 T7
A_DDR3_DQ13 B_DDR3_DQ13 G3 A_DDR3_DQS2 DQSL NC_6 A_DDR3_A[14]
A_DDR3_DQ[14] E18 M28 B_DDR3_DQ[14] A_DDR3_DQS0B DQSL G3
A_DDR3_DQ14 B_DDR3_DQ14 A_DDR3_DQS2B DQSL
A_DDR3_DQ[15] D22 T29 B_DDR3_DQ[15]
A_DDR3_DQ15 B_DDR3_DQ15 C7 A9
B19 N31 A_DDR3_DQS1 DQSU VSS_1 C7 A9
A_DDR3_DM0 A_DDR3_DM0 B_DDR3_DM0 B_DDR3_DM0 B7 B3 A_DDR3_DQS3 DQSU VSS_1
E21 R28 A_DDR3_DQS1B DQSU VSS_2 B7 B3
A_DDR3_DM1 A_DDR3_DM1 B_DDR3_DM1 B_DDR3_DM1 E1 A_DDR3_DQS3B DQSU VSS_2
VSS_3 E1
E7 G8 VSS_3
A21 R32 A_DDR3_DM0 DML VSS_4 E7 G8
A_DDR3_DQS0 A_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_DQS0 D3 J2 A_DDR3_DM2 DML VSS_4
B20 P31 A_DDR3_DM1 DMU VSS_5 D3 J2
A_DDR3_DQS0B A_DDR3_DQS0B B_DDR3_DQS0B B_DDR3_DQS0B J8 A_DDR3_DM3 DMU VSS_5
C20 P30 A_DDR3_DQ[0-15] VSS_6 J8
A_DDR3_DQS1 A_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_DQS1
A_DDR3_DQ[0] E3 M1 A_DDR3_DQ[16-31] VSS_6
C19 N30 DQL0 VSS_7 A_DDR3_DQ[16] E3 M1
A_DDR3_DQS1B A_DDR3_DQS1B B_DDR3_DQS1B B_DDR3_DQS1B
A_DDR3_DQ[1] F7 M9 DQL0 VSS_7
DQL1 VSS_8 A_DDR3_DQ[17] F7 M9
A_DDR3_DQ[16-31] B_DDR3_DQ[16-31]
A_DDR3_DQ[2] F2 P1 DQL1 VSS_8
A_DDR3_DQ[16] B27 AA31 B_DDR3_DQ[16] DQL2 VSS_9 A_DDR3_DQ[18] F2 P1
A_DDR3_DQ16 B_DDR3_DQ16
A_DDR3_DQ[3] F8 P9 DQL2 VSS_9
A_DDR3_DQ[17] A24 V32 B_DDR3_DQ[17] DQL3 VSS_10 A_DDR3_DQ[19] F8 P9
A_DDR3_DQ17 B_DDR3_DQ17
A_DDR3_DQ[4] H3 T1 DQL3 VSS_10
A_DDR3_DQ[18] C27 AA30 B_DDR3_DQ[18] DQL4 VSS_11 A_DDR3_DQ[20] H3 T1
A_DDR3_DQ18 B_DDR3_DQ18
A_DDR3_DQ[5] H8 T9 DQL4 VSS_11
A_DDR3_DQ[19] C24 V30 B_DDR3_DQ[19] DQL5 VSS_12 A_DDR3_DQ[21] H8 T9
A_DDR3_DQ19 B_DDR3_DQ19
A_DDR3_DQ[6] G2 DQL5 VSS_12
A_DDR3_DQ[20] A28 AB32 B_DDR3_DQ[20] DQL6 A_DDR3_DQ[22] G2
A_DDR3_DQ20 B_DDR3_DQ20
A_DDR3_DQ[7] H7 DQL6
A_DDR3_DQ[21] E24 V28 B_DDR3_DQ[21] DQL7 A_DDR3_DQ[23] H7
A_DDR3_DQ21 B_DDR3_DQ21 +1.5V_U_DDR A_DDR3_CKE B1 DQL7
A_DDR3_DQ[22] B28 AB31 B_DDR3_DQ[22] VSSQ_1 B1
A_DDR3_DQ22 B_DDR3_DQ22
A_DDR3_DQ[8] D7 B9 VSSQ_1
A_DDR3_DQ[23] B23 U31 B_DDR3_DQ[23] R13112 DQU0 VSSQ_2 A_DDR3_DQ[24] D7 B9
A_DDR3_DQ23 B_DDR3_DQ23
R13102
1K
A_DDR3_DQ[9] C3 D1 DQU0 VSSQ_2
1K DQU1 VSSQ_3
A_DDR3_DQ[24] D25 W29 B_DDR3_DQ[24] A_DDR3_DQ[25] C3 D1
A_DDR3_DQ24 B_DDR3_DQ24
A_DDR3_DQ[10] C8 D8 DQU1 VSSQ_3
A_DDR3_DQ[25] E27 AA28 B_DDR3_DQ[25] A_DDR3_RESET DQU2 VSSQ_4 A_DDR3_DQ[26] C8 D8
A_DDR3_DQ25 B_DDR3_DQ25
A_DDR3_DQ[11] C2 E2 DQU2 VSSQ_4
A_DDR3_DQ[26] C25 W30 B_DDR3_DQ[26] DQU3 VSSQ_5 A_DDR3_DQ[27] C2 E2
A_DDR3_DQ26 B_DDR3_DQ26
A_DDR3_DQ[12] A7 E8 DQU3 VSSQ_5
A_DDR3_DQ[27] D28 AB29 B_DDR3_DQ[27] DQU4 VSSQ_6 A_DDR3_DQ[28] A7 E8
A_DDR3_DQ27 B_DDR3_DQ27
A_DDR3_DQ[13] A2 F9 DQU4 VSSQ_6
A_DDR3_DQ[28] E26 Y28 B_DDR3_DQ[28] DQU5 VSSQ_7 A_DDR3_DQ[29] A2 F9
A_DDR3_DQ28 B_DDR3_DQ28
A_DDR3_DQ[14] B8 G1 DQU5 VSSQ_7
A_DDR3_DQ[29] E28 AB28 B_DDR3_DQ[29] DQU6 VSSQ_8 A_DDR3_DQ[30] B8 G1
A_DDR3_DQ29 B_DDR3_DQ29
A_DDR3_DQ[15] A3 G9 DQU6 VSSQ_8
A_DDR3_DQ[30] E25 W28 B_DDR3_DQ[30] DQU7 VSSQ_9 A_DDR3_DQ[31] A3 G9
A_DDR3_DQ30 B_DDR3_DQ30 DQU7 VSSQ_9
A_DDR3_DQ[31] C28 AB30 B_DDR3_DQ[31]
A_DDR3_DQ31 B_DDR3_DQ31 +1.5V_U_DDR B_DDR3_CKE
B24 V31
A_DDR3_DM2 A_DDR3_DM2 B_DDR3_DM2 B_DDR3_DM2
B26 Y31
A_DDR3_DM3 A_DDR3_DM3 B_DDR3_DM3 B_DDR3_DM3 R13113
R13103 1K
1K
B25 W31
A_DDR3_DQS2 A_DDR3_DQS2 B_DDR3_DQS2 B_DDR3_DQS2
A25 W32 B_DDR3_RESET
A_DDR3_DQS2B A_DDR3_DQS2B B_DDR3_DQS2B B_DDR3_DQS2B
D26 Y29
A_DDR3_DQS3 A_DDR3_DQS3 B_DDR3_DQS3 B_DDR3_DQS3
C26 Y30
A_DDR3_DQS3B A_DDR3_DQS3B B_DDR3_DQS3B B_DDR3_DQS3B
* DDR_VTT
DDR_VTT_URSA_0
+1.5V_U_DDR
+3.3V_NORMAL
R13100
10K 1%
IC13100
TPS51200DRCR [EP] L13101
C13199
AR13101 AR13103 AR13105 AR13107 AR13109 AR13111 AR13113
IC2900
10uF
R13101 C13122
CIS21J121 10V 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
10K 1000pF IC2800 U_MVREFCA_B1
REFIN VIN
1% 1 10
H5TQ1G63EFR-RDC
THERMAL
U_MVREFCA_B0
11
VLDOIN PGOOD C13150
2 9 4700pF N3 M8
B_DDR3_A[0] A0 VREFCA
DDR_VTT_URSA VO GND
P7
C13123 B_DDR3_A[1] A1
3 8
22uF N3 M8 P3
10V B_DDR3_A[0] A0 VREFCA B_DDR3_A[2] A2
L13100 PGND EN P7 N2 H1
CIS21J121
4 7 B_DDR3_A[1] A1 B_DDR3_A[3] A3 VREFDQ
P3 P8
VOSNS REFOUT
B_DDR3_A[2] A2 B_DDR3_A[4] A4
5 6 N2 H1 P2
B_DDR3_A[3] A3 VREFDQ B_DDR3_A[5] A5
C13110 C13111 C13113 C13147 P8 R8 L8 R13135 240
10uF 10uF 10uF 0.1uF B_DDR3_A[4] A4 B_DDR3_A[6] A6 ZQ
P2 R2 1%
B_DDR3_A[5] A5 B_DDR3_A[7] A7 +1.5V_U_DDR
Close to REFOUT pin
R8 L8 R13127 240
T8
B_DDR3_A[6] A6 ZQ B_DDR3_A[8] A8
R2 1%
R3 B2
B_DDR3_A[7] A7 +1.5V_U_DDR B_DDR3_A[9] A9 VDD_1
T8 L7 D9
B_DDR3_A[8] A8 B_DDR3_A[10] A10/AP VDD_2
R3 B2 R7 G7
B_DDR3_A[9] A9 VDD_1 B_DDR3_A[11] A11 VDD_3
L7 D9 N7 K2
B_DDR3_A[10] A10/AP VDD_2 B_DDR3_A[12] A12/BC VDD_4
R7 G7 T3 K8
B_DDR3_A[11] A11 VDD_3 B_DDR3_A[13] NC_7 VDD_5
N7 K2 N1
B_DDR3_A[12] A12/BC VDD_4 B_DDR3_A[14] VDD_6
T3 K8 M7 N9
B_DDR3_A[13] NC_7 VDD_5 B_DDR3_A[15] NC_5 VDD_7
DDR_VTT_URSA N1
DDR_VTT_URSA_0 R1
L13102 VDD_6 VDD_8
BLM18PG121SN1D M7 N9 M2 R9
B_DDR3_A[15] NC_5 VDD_7 B_DDR3_BA[0] BA0 VDD_9
R1 N8 +1.5V_U_DDR
C13181 C13179 C13189 C13151
VDD_8 B_DDR3_BA[1] BA1
C13105 M2 R9 M3
1uF 0.1uF 0.1uF 0.1uF
25V 16V 16V 16V
0.1uF B_DDR3_BA[0] BA0 VDD_9 B_DDR3_BA[2] BA2
16V N8 A1
B_DDR3_BA[1] BA1 VDDQ_1
M3 +1.5V_U_DDR
R13125R13124
B_DDR3_MCLK J7 A8
B_DDR3_BA[2] BA2 B_DDR3_MCLK CK VDDQ_2
56
C13234 A1 K7 C1
VDDQ_1 B_DDR3_MCLKZ CK VDDQ_3
0.01uF J7 A8 K9 C9
56
DDR_VTT_URSA DDR_VTT_URSA_1 CK VDDQ_2 B_DDR3_CKE CKE VDDQ_4
L13103 K7 C1 D2
BLM18PG121SN1D B_DDR3_MCLKZ CK VDDQ_3 VDDQ_5
K9 C9 L2 E9
B_DDR3_CKE CKE VDDQ_4 B_DDR3_CSB2 CS VDDQ_6
D2 K1 F1
C13112 C13132 C13158 C13174 C13106 VDDQ_5 B_DDR3_ODT ODT VDDQ_7
1uF 0.1uF 0.1uF 0.1uF 0.1uF L2 E9 J3 H2
25V 16V 16V 16V 16V B_DDR3_CSB1 CS VDDQ_6 B_DDR3_RASZ RAS VDDQ_8
K1 F1 K3 H9
B_DDR3_ODT ODT VDDQ_7 B_DDR3_CASZ CAS VDDQ_9
J3 H2 L3
B_DDR3_RASZ RAS VDDQ_8 B_DDR3_WEZ WE
K3 H9 J1
B_DDR3_CASZ CAS VDDQ_9 NC_1
L3 T2 J9
B_DDR3_WEZ WE B_DDR3_RESET RESET NC_2
J1 L1
NC_1 NC_3
T2 J9 L9
B_DDR3_RESET RESET NC_2 NC_4
L1 F3 T7
NC_3 B_DDR3_DQS2 DQSL NC_6 B_DDR3_A[14]
L9 G3
NC_4 B_DDR3_DQS2B DQSL
F3 T7
Decap removed B_DDR3_DQS0
G3
DQSL NC_6 B_DDR3_A[14]
C7 A9
B_DDR3_DQS0B DQSL B_DDR3_DQS3 DQSU VSS_1
B7 B3
C7 A9 B_DDR3_DQS3B DQSU VSS_2
E1
B_DDR3_DQS1 DQSU VSS_1 VSS_3
B7 B3 E7 G8
B_DDR3_DQS1B DQSU VSS_2 B_DDR3_DM2 DML VSS_4
E1 D3 J2
VSS_3 B_DDR3_DM3 DMU VSS_5
E7 G8 J8
B_DDR3_DM0 DML VSS_4 B_DDR3_DQ[16-31] VSS_6
D3 J2 B_DDR3_DQ[16] E3 M1
B_DDR3_DM1 DMU VSS_5 DQL0 VSS_7
J8 B_DDR3_DQ[17] F7 M9
B_DDR3_DQ[0-15] VSS_6 DQL1 VSS_8
B_DDR3_DQ[0] E3 M1 B_DDR3_DQ[18] F2 P1
DQL0 VSS_7 DQL2 VSS_9
B_DDR3_DQ[1] F7 M9 B_DDR3_DQ[19] F8 P9
DQL1 VSS_8 DQL3 VSS_10
B_DDR3_DQ[2] F2 P1 B_DDR3_DQ[20] H3 T1
DQL2 VSS_9 DQL4 VSS_11
+1.5V_U_DDR B_DDR3_DQ[3] F8 P9 B_DDR3_DQ[21] H8 T9
DQL3 VSS_10 DQL5 VSS_12
Close to DDR Power pin B_DDR3_DQ[4] H3 T1 B_DDR3_DQ[22] G2
DQL4 VSS_11 DQL6
B_DDR3_DQ[5] H8 T9 B_DDR3_DQ[23] H7
DQL5 VSS_12 DQL7
B_DDR3_DQ[6] G2 B1
DQL6 VSSQ_1
B_DDR3_DQ[7] H7 B_DDR3_DQ[24] D7 B9
C13104 C13109 C13117 C13128 C13137 C13146 C13156 C13164 C13172 C13178 C13186 C13194 C13198 C13206 C13214 C13218 C13226 DQL7
B1 DQU0 VSSQ_2
B_DDR3_DQ[25] C3 D1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF B_DDR3_DQ[8] D7
VSSQ_1
B9 DQU1 VSSQ_3
B_DDR3_DQ[26] C8 D8
16V 16V 16V 16V 16V 16V 16V 16V 25V 16V 16V 10V 16V 16V 16V 16V 25V B_DDR3_DQ[9] C3
DQU0 VSSQ_2
D1 DQU2 VSSQ_4
B_DDR3_DQ[27] C2 E2
DQU1 VSSQ_3 DQU3 VSSQ_5
B_DDR3_DQ[10] C8 D8 B_DDR3_DQ[28] A7 E8
DQU2 VSSQ_4 DQU4 VSSQ_6
B_DDR3_DQ[11] C2 E2 B_DDR3_DQ[29] A2 F9
DQU3 VSSQ_5 DQU5 VSSQ_7
B_DDR3_DQ[12] A7 E8 B_DDR3_DQ[30] B8 G1
DQU4 VSSQ_6 DQU6 VSSQ_8
B_DDR3_DQ[13] A2 F9 B_DDR3_DQ[31] A3 G9
DQU5 VSSQ_7 DQU7 VSSQ_9
B_DDR3_DQ[14] B8 G1
DQU6 VSSQ_8
B_DDR3_DQ[15] A3 G9
+1.5V_U_DDR DQU7 VSSQ_9
Close to DDR Power pin
C13102 C13107 C13115 C13126 C13135 C13144 C13154 C13162 C13170 C13176 C13184 C13192 C13196 C13204 C13212 C13216 C13224 C13232 C13100 C13101
0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
16V 16V 25V 16V 16V 16V 16V 10V 16V 16V 16V 16V 16V 16V 25V 16V 16V 16V 10V 10V
4th layer
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13103 C13108 C13116
0.1uF 0.1uF 0.1uF
16V 16V 16V
BSD-14Y-UD-131-HD
+1.5V_U_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
Close to DDR Power pin SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
Decap removed FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
C13195 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
0.1uF THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
16V
2013.12.17
4th layer
URSA7_DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
URSA Option
Clock for URSA9 +3.3V_NORMAL URSA Reset
URSA_RX_LVDS
URSA_BIT0_1
LGD_Module
URSA_BIT1_1
URSA_BIT2_1
R1911 10K
R1913 10K
R1915 10K
R1917 10K
R1909 10K
Option Name
C1903
UB98/UC9_URSA9_crystalcap SW1901
JTP-1127WEM
5pF
50V
1 2 OPT URSA_OPT_0
X-TAL_1
Rx Interface
XIN_URSA C1902 URSA_OPT_1
GND_1
22uF Module Type
3 4 URSA_BIT0
10V
URSA_BIT1
Tx Lane
R1925
URSA_RESET
2
1
URSA_BIT2
24MHz
X1900
0
1N4148W
1M
R1924
D1900
BIT [2/1/0] Tx Lane
C1904
R1923
100V
URSA_RESET_SoC
3
4
5pF
50V
10K
URSA_BIT1_0
URSA_BIT2_0
0 0/0/0 4K@120 (16lane)
URSA_BIT0_0
URSA_RX_VX1
10K
10K
10K
10K
10K
OS_Module
X-TAL_2
GND_2
R1930 0/0/1 4k@60 (8lane)
XO_URSA 0/1/0 5k@120 (20lane)
R1916
R1910
R1918
R1912
R1914
0/1/1 OLED ULTRA HD
1/0/0 FHD@120 (4lane)
1/0/1 FHD@60 (2lane)
1/1/0 Reserved
1/1/1 Reserved
Option Name
UB85/95/UC97_URSA9_crystalcap
C1904-*1 C1903-*1 IC2500
8pF 8pF LGE7411(URSA9)
50V 50V
AF29 AG25
URSA_RESET RESET I2C_HSC_SDA/VSYNC_LIKE2
AH25
I2C_HSC_SCL/VSYNC_LIKE3
R3
IC1901-*1 XIN_URSA XTALO
W25Q32BVSSIG R4 AH28
SPI Flash XO_URSA XTALI SPI1_CK/PWM2/GPIO58
AJ27
OPT
R13202 33
URSA_OPT_0
/CS VCC SPI1_DI/PWM3/GPIO59
1 8 AJ24 AJ29
I2CS_SDA SPI2_CK/PWM0/GPIO56 +3.3V_NORMAL
I2CS_SDA AR13201 AH24 AF27
DO[IO1] /HOLD[IO3] I2CS_SCL 33 I2CS_SCL SPI2_DI/PWM1/GPIO57
2 7
AG28 OPT
SPI3_CK/DIM10/GPIO54 R1936
AH26 AH27 10K
/WP[IO2] CLK
3 6 I2CM_SDA SPI3_DI/DIM11/GPIO55
AG24 AG27 R1935 33
+3.3V_NORMAL I2CM_SCL/VSYNC_LIKE1 SPI4_CK/DIM8/GPIO52 3D_EN
GND
4 5
DI[IO0]
AG26 R1934 33
R1937
IC1901 B4
SPI4_DI/DIM9/GPIO53 L_DIM_EN
10K
MX25L3206EM2I-12G A4
GPIO[0][UART2_TX]
AF28
OPT
R13203 33
SPI_4MB_Winbond GPIO[1][UART2_RX] VSYNC_LIKE/PWM5/GPIO40
CS# VCC C1901 B5
1 8 0.1uF GPIO[2][UART1_TX]
SPI_CZ SPI_4MB_MACRONIX 16V A5 AG23 +3.3V_NORMAL
GPIO[3][UART1_RX] DIM0/GPIO[32] DIM0
Change pin from A5 to C4
AG20
R1904 SO/SIO1 HOLD# DIM1/GPIO[33] DIM1 OPT
33 2 7 AH23 R13204
SPI_DO DIM2/GPIO[34] DIM2 10K
10K R1903 +3.3V_NORMAL AD28 AH20
SPI_CZ SPI_CZ DIM3/GPIO[35]
1K WP# SCLK AD30 AG21
R1905 3 6 SPI_CK SPI_CK DIM4/GPIO[36] URSA_OPT_1
FLASH_WP_URSA 1K SPI_CK AR13200 AC31 AH22 R13205
URSA_BIT0 10K
U_SPI_WP_f_URSA SPI_DI 33 SPI_DI DIM5/GPIO[37]
OPT AD29 AG22
GND SI/SIO0 R1954 SPI_DO SPI_DO DIM6/GPIO[38] URSA_BIT1
R1932 1K 4 5 SPI_DI AH21
URSA_BIT2
FRC_FLASH_WP DIM7/GPIO[39]
33 R1981 AE28
U_SPI_WP_f_SoC TCON_I2C_EN INT_R21/GPIO[41]
OPT 33 R1933 AE27
10K INT_R20/GPIO[42]
A3
R1955 GPIO43/TCON0
B3
GPIO44/TCON1
A2
GPIO45/TCON2
C4 C3 Not Used Net (UB98/D9)
IRE GPIO46/TCON3
B2
GPIO47/TCON4 RXASCL_URSA9
URSA9 UART1_RX B1 RXASDA_URSA9
GPIO48/TCON5
C2 RXBSCL_URSA9
GPIO49/TCON6 RXBSDA_URSA9
AC27 C1
GND_1 GPIO50/TCON7
AD27
GND_2
AG4
GPIO[18]/TCON8
A7 AG5 HDMI OUTPUT_1 DDC to URSA9
NC_1 GPIO[19]/TCON9
B6 AH4
Chip Config NC_2 GPIO[20]/TCON10 RXASCL_URSA9
Debugging for URSA9 B7
C5
NC_3 GPIO[21]/TCON11
AH5
AH6
RXASDA_URSA9
Debug/ISP ADDR NC_4 GPIO[22]/TCON12
Slave (Debug Port:0XB4,ISP:0X98) C6 AJ4
NC_5 GPIO[23]/TCON13
CHIP_CONF:{DIM2,DIM1,DIM0} C7 AJ5
CHIP_CONF=3’d7:111:boot from SPI Flash I2C_S Port NC_6 GPIO24/TCON14
D4 AJ6
NC_7 GPIO25/TCON15
P1905 D5
12507WS-04L NC_8
D6 AH16
WAFER-STRAIGHT Data_Format_1
NC_9 GPIO[4]
D7 AG16
+3.3V_NORMAL DIM0 1 SW1902 NC_10 GPIO[5] Data_Format_0 HDMI OUTPUT_0 DDC to URSA9
JS2235S E4 Y5
NC_11 GPIO[6] RXBSCL_URSA9
OPT 10K E5 Y4
2 RXBSDA_URSA9
NC_12 GPIO[7]
10K R1908 I2C_SCL1 1 6 I2C_SDA1 E6 AB4
DIM1 R1922 R1958 R1959 NC_13 GPIO[8]
R1902 3 33
SCL2_+3.3V_DB 0 0 E7 AB5 For DFT JIG
URSA_MP URSA_MP
OPT 10K URSA_DEBUG
I2CS_SCL 2 5 I2CS_SDA NC_14 GPIO[9] OPT
R1960 URSA_DEBUG R1961
F4 AG17 R13207 33
R13206 R13209
R1921 33 0 0 NC_15 GPIO[10]/PWM_DIM_IN[0] OPT 100K 100K
4 SDA2_+3.3V_DB
10K R1907 URSA_DEBUG
OPT
3 4
OPT F5 AH17 R13208 33
SCL2_+3.3V_DB SDA2_+3.3V_DB NC_16 GPIO[11]/PWM_DIM_IN[1]
R1901 DIM2 5 M5 AG18 10K R13201
NC_17 GPIO[12] URSA_RX_Vx1_HTPDn
OPT 10K M6 AJ20 10K R13200
NC_18 GPIO[13] URSA_RX_Vx1_HTPDn
M7 AH18 URSA9_Vx1_RX_HTPD_GPIO
10K R1906 NC_19 GPIO[14] URSA9_CONNECT
R1900 N5 AG19
NC_20 GPIO[15] URSA_LOCK_O
R7 AH19
NC_21 GPIO[16] URSA_LOCK_V
P7 AJ21 Not Used Net (UB85/95/UC89)
NC_22 GPIO[17] FLASH_WP_URSA
N7 URSA9_CONNECT
NC_23 URSA_LOCK_O
N6
NC_24 URSA_LOCK_V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-132-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
IC2500 LGE7411(URSA9)
LGE7411(URSA9)
D18 D24
A8 T13 VSS_285 VSS_389
VSS_81 VSS_186 G18 F24
B8 R13 VSS_286 VSS_390
VSS_82 VSS_187 H18 G24
C8 P13 VSS_287 VSS_391
VSS_83 VSS_188 J18 H24
D8 N13 VSS_288 VSS_392
VSS_84 VSS_189 L18 J24
E8 M13 VSS_289 VSS_393
VSS_85 VSS_190 N18 K24
F8 U13 VSS_290 VSS_394
VSS_86 VSS_191 P18 L24
G8 V13 VSS_291 VSS_395
VSS_87 VSS_192 R18 M24
H8 W13 VSS_292 VSS_396
VSS_88 VSS_193 T18 N24
J8 Y13 VSS_293 VSS_397
VSS_89 VSS_194 U18 P24
K8 AA13 VSS_294 VSS_398
IC2500 VSS_90 VSS_195 V18 R24
L8 AB13 VSS_295 VSS_399
LGE7411(URSA9) VSS_91 VSS_196 W18 T24
M8 AD13 VSS_296 VSS_400
VSS_92 VSS_197 Y18 U24
VDDC N8 AE13 VSS_297 VSS_401
VSS_93 VSS_198 AA18 V24
P8 AF13 VSS_298 VSS_402
VSS_94 VSS_199 AB18 W24
A6 K1 R8 AG13 VSS_299 VSS_403
VDDC_1 VSS_1 VSS_95 VSS_200 AE18 Y24
M9 T1 T8 AH13 VSS_300 VSS_404
VDDC_2 VSS_2 VSS_96 VSS_201 AF18 AA24
M10 K2 U8 AJ13 VSS_301 VSS_405
VDDC_3 VSS_3 VSS_97 VSS_202 AJ18 AB24
M11 P2 V8 G14 VSS_302 VSS_406
VDDC_4 VSS_4 VSS_98 VSS_203 F19 AC24
N9 T2 W8 H14 VSS_303 VSS_407
VDDC_5 VSS_5 VSS_99 VSS_204 G19 AD24
N10 AF2 Y8 J14 VSS_304 VSS_408
VDDC_6 VSS_6 VSS_100 VSS_205 H19 AE24
N11 K3 AA8 K14 VSS_305 VSS_409
VDDC_7 VSS_7 VSS_101 VSS_206 J19 AF24
P9 T3 L14 VSS_306 VSS_410
VDDC_8 VSS_8 VSS_207 K19
P10 AF3 AC8 P14 VSS_307
VDDC_9 VSS_9 VSS_102 VSS_208 L19 AL24
P11 AG3 AD8 R14 VSS_308 VSS_411
VDDC_10 VSS_10 VSS_103 VSS_209 N19 F25
R9 G4 AE8 T14 VSS_309 VSS_412
VDDC_11 VSS_11 VSS_104 VSS_210 P19 G25
R10 H4 AF8 U14 VSS_310 VSS_413
VDDC_12 VSS_12 VSS_105 VSS_211 R19 H25
R11 J4 AG8 V14 VSS_311 VSS_414
VDDC_13 VSS_13 VSS_106 VSS_212 T19 J25
T9 K4 AH8 W14 VSS_312 VSS_415
VDDC_14 VSS_14 VSS_107 VSS_213 U19 K25
T10 P4 AJ8 Y14 VSS_313 VSS_416
VDDC_15 VSS_15 VSS_108 VSS_214 V19 L25
T11 T4 B9 AA14 VSS_314 VSS_417
VDDC_16 VSS_16 VSS_109 VSS_215 W19 M25
U9 U4 D9 AB14 VSS_315 VSS_418
VDDC_17 VSS_17 VSS_110 VSS_216 Y19 N25
U10 V4 E9 AE14 VSS_316 VSS_419
VDDC_18 VSS_18 VSS_111 VSS_217 AB19 P25
U11 W4 F9 AF14 VSS_317 VSS_420
VDDC_19 VSS_19 VSS_112 VSS_218 AC19 R25
V9 AA4 G9 AG14 VSS_318 VSS_421
VDDC_20 VSS_20 VSS_113 VSS_219 AD19 T25
V10 AC4 H9 AH14 VSS_319 VSS_422
VDDC_21 VSS_21 VSS_114 VSS_220 AE19 U25
V11 AD4 J9 AJ14 VSS_320 VSS_423
VDDC_22 VSS_22 VSS_115 VSS_221 AF19 V25
W9 AE4 K9 A15 VSS_321 VSS_424
VDDC_23 VSS_23 VSS_116 VSS_222 AK19 W25
W10 AF4 L9 B15 VSS_322 VSS_425
VDDC_24 VSS_24 VSS_117 VSS_223 A20 Y25
W11 G5 D15 VSS_323 VSS_426
VDDC_25 VSS_25 VSS_224 E20 AA25
Y9 H5 VSS_324 VSS_427
VDDC_26 VSS_26 F20 AB25
J5 AD9 G15 VSS_325 VSS_428
VSS_27 VSS_118 VSS_225 G20 AC25
K5 AE9 H15 VSS_326 VSS_429
AVDDL_HDMI_TX_RX VSS_28 VSS_119 VSS_226 H20 AD25
L5 AF9 J15 VSS_327 VSS_430
VSS_29 VSS_120 VSS_227 J20 AE25
AG9 K15 VSS_328 VSS_431
VSS_121 VSS_228 L20 AF25
L3 P5 AH9 L15 VSS_329 VSS_432
AVDDL_HDMITX_1 VSS_30 VSS_122 VSS_229 N20 AM25
AVDDL_LVDSRX L4 R5 AJ9 M15 VSS_330 VSS_433
AVDDL_HDMITX_2 VSS_31 VSS_123 VSS_230 P20 A26
AA9 T5 N15 VSS_331 VSS_434
AVDDL_RX_1 VSS_32 VSS_231 R20 F26
AA10 U5 D10 P15 VSS_332 VSS_435
AVDDL_RX_2 VSS_33 VSS_124 VSS_232 T20 G26
AB9 V5 E10 R15 VSS_333 VSS_436
AVDDL_RX_3 VSS_34 VSS_125 VSS_233 U20 H26
F10 T15 VSS_334 VSS_437
VSS_126 VSS_234 V20 J26
Y10 W5 G10 U15 VSS_335 VSS_438
AVDDL_DVI_1 VSS_35 VSS_127 VSS_235 W20 K26
Y11 AA5 H10 V15 VSS_336 VSS_439
AVDDL_DVI_2 VSS_36 VSS_128 VSS_236 AE20 L26
DVDD_DDR AC5 J10 W15 VSS_337 VSS_440
VSS_37 VSS_129 VSS_237 AF20 M26
M14 AD5 K10 Y15 VSS_338 VSS_441
DVDD_DDR_1 VSS_38 VSS_130 VSS_238 AK20 N26
N14 AE5 L10 AA15 VSS_339 VSS_442
AVDDL_MOD DVDD_DDR_2 VSS_39 VSS_131 VSS_239 P26
AF5 AB10 AE15 VSS_443
VSS_40 VSS_132 VSS_240 D21 R26
Y20 F6 AC10 AF15 VSS_340 VSS_444
AVDDL_MOD_1 VSS_41 VSS_133 VSS_241 F21 T26
Y21 G6 AD10 AG15 VSS_341 VSS_445
AVDDL_MOD_2 VSS_42 VSS_134 VSS_242 G21 U26
Y22 H6 AE10 AH15 VSS_342 VSS_446
AVDDL_MOD_3 VSS_43 VSS_135 VSS_243 H21 V26
AA19 J6 AF10 AJ15 VSS_343 VSS_447
AVDDL_MOD_4 VSS_44 VSS_136 VSS_244 J21 W26
AA20 K6 AG10 E16 VSS_344 VSS_448
AVDDL_DRV AVDDL_MOD_5 VSS_45 VSS_137 VSS_245 K21 Y26
AA21 L6 AH10 F16 VSS_345 VSS_449
AVDDL_DRV_1 VSS_46 VSS_138 VSS_246 L21 AA26
AA22 AJ10 G16 VSS_346 VSS_450
AVDDL_DRV_2 VSS_139 VSS_247 T21 AB26
AB20 P6 A11 H16 VSS_347 VSS_451
AVDDL_DRV_3 VSS_47 VSS_140 VSS_248 U21 AC26
AB21 R6 D11 J16 VSS_348 VSS_452
AVDDL_DRV_4 VSS_48 VSS_141 VSS_249 V21 AD26
AB22 T6 E11 VSS_349 VSS_453
AVDDL_DRV_5 VSS_49 VSS_142 W21 AE26
U6 F11 L16 VSS_350 VSS_454
AVDD_MOD VSS_50 VSS_143 VSS_250 AE21 AF26
AC20 V6 G11 N16 VSS_351 VSS_455
AVDD_MOD_1 VSS_51 VSS_144 VSS_251 AF21 AJ26
AC21 W6 H11 P16 VSS_352 VSS_456
AVDD_MOD_2 VSS_52 VSS_145 VSS_252 AK21 AL26
AD21 Y6 J11 R16 VSS_353 VSS_457
AVDD_MOD_3 VSS_53 VSS_146 VSS_253 D27
AD20 AA6 K11 T16 VSS_458
AVDD_MOD_LDO VSS_54 VSS_147 VSS_254 F27
VDDP AB6 L11 U16 VSS_459
VSS_55 VSS_148 VSS_255 K27
AC18 AC6 AA11 V16 VSS_460
VDDP_1 VSS_56 VSS_149 VSS_256 G22 N27
AD17 AD6 AB11 W16 VSS_354 VSS_461
VDDP_2 VSS_57 VSS_150 VSS_257 H22 P27
AD18 AE6 AC11 Y16 VSS_355 VSS_462
VDDP_3 VSS_58 VSS_151 VSS_258 J22 R27
AF6 AE11 AA16 VSS_356 VSS_463
VSS_59 VSS_152 VSS_259 U27
AD11 AG6 AF11 AE16 VSS_464
AVDD_DVI_1 VSS_60 VSS_153 VSS_260 L22 V27
AD12 AG11 AF16 VSS_357 VSS_465
AVDD_DVI_2 VSS_154 VSS_261 M22 W27
AC12 F7 AH11 VSS_358 VSS_466
AVDD_HDMITX_1 VSS_61 VSS_155 T22 Y27
AC13 G7 AJ11 VSS_359 VSS_467
AVDD_HDMITX_2 VSS_62 VSS_156 U22 AA27
AD15 H7 AJ16 VSS_360 VSS_468
AVDD_RX_1 VSS_63 VSS_262 V22 AB27
AC16 J7 D12 AM16 VSS_361 VSS_469
AVDD_RX_2 VSS_64 VSS_157 VSS_263 W22
AC17 K7 E12 A17 VSS_362
AVDD_RX_3 VSS_65 VSS_158 VSS_264 AC22 F28
AD16 L7 F12 B17 VSS_363 VSS_470
AVDD_RX_4 VSS_66 VSS_159 VSS_265 AD22 K28
AVDD_PLL G12 G17 VSS_364 VSS_471
VSS_160 VSS_266 AE22 P28
AD14 H12 H17 VSS_365 VSS_472
AVDD_XTAL VSS_161 VSS_267 AF22 U28
AC14 J12 J17 VSS_366 VSS_473
AVDD_PLL_1 VSS_162 VSS_268 AL22 AC28
+1.5V_U_DDR
AC15 T7 K12 K17 VSS_367 VSS_474
AVDD_PLL_2 VSS_67 VSS_163 VSS_269 AK28
M18 U7 L12 L17 VSS_475
AVDD_DDR0_1 VSS_68 VSS_164 VSS_270 A29
M19 V7 M12 N17 VSS_476
AVDD_DDR0_2 VSS_69 VSS_165 VSS_271 A23 C29
M20 W7 N12 P17 VSS_368 VSS_477
AVDD_DDR0_3 VSS_70 VSS_166 VSS_272 E23 D29
M21 Y7 P12 R17 VSS_369 VSS_478
AVDD_DDR0_4 VSS_71 VSS_167 VSS_273 F23 E29
M16 AA7 R12 T17 VSS_370 VSS_479
AVDD_DDR0_5 VSS_72 VSS_168 VSS_274 G23 F29
M17 AB7 T12 U17 VSS_371 VSS_480
AVDD_DDR0_6 VSS_73 VSS_169 VSS_275 H23 J29
AC7 U12 V17 VSS_372 VSS_481
VSS_74 VSS_170 VSS_276 J23 M29
P21 AD7 V12 W17 VSS_373 VSS_482
AVDD_DDR1_1 VSS_75 VSS_171 VSS_277 K23 R29
R21 AE7 W12 Y17 VSS_374 VSS_483
AVDD_DDR1_2 VSS_76 VSS_172 VSS_278 V29
P22 AF7 Y12 AA17 VSS_484
AVDD_DDR1_3 VSS_77 VSS_173 VSS_279 M23 AA29
R22 AG7 AA12 AB17 VSS_375 VSS_485
AVDD_DDR1_4 VSS_78 VSS_174 VSS_280 AC29
N21 AH7 AB12 AE17 VSS_486
AVDD_DDR1_5 VSS_79 VSS_175 VSS_281 P23 AK29
N22 AJ7 AE12 AF17 VSS_376 VSS_487
AVDD_DDR1_6 VSS_80 VSS_176 VSS_282 A30
AF12 VSS_488
VSS_177 T23 B30
AG12 VSS_377 VSS_489
VSS_178 V23 AC30
AH12 AJ17 VSS_378 VSS_490
VSS_179 VSS_283 W23 AK30
AJ12 AL17 VSS_379 VSS_491
VSS_180 VSS_284 Y23 AM30
VSS_380 VSS_492
AA23 A31
VSS_381 VSS_493
AB23 B31
G13 VSS_382 VSS_494
VSS_181 AC23 C31
H13 VSS_383 VSS_495
VSS_182 AD23 J31
J13 VSS_384 VSS_496
VSS_183 AE23 L31
K13 VSS_385 VSS_497
VSS_184 AF23 AD31
L13 VSS_386 VSS_498
VSS_185 AJ23 AF31
VSS_387 VSS_499
AM23 AH31
VSS_388 VSS_500
B32
VSS_501
E32
VSS_502
J32
VSS_503
L32
VSS_504
P32
VSS_505
U32
VSS_506
Y32
VSS_507
AE32
VSS_508
AG32
VSS_509
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-14Y-UD-133-HD
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_Power
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
MAX 4.7A
TCON_PWR_5pin_Wafer
P13401
+12V
+1.5V URSA DDR +1.15V URSA9 Core
+1.5V_U_DDR
20037WR-05A00
T-con power L13411
BLM18PG121SN1D
POWER_ON/OFF2_1 DCDC_TI
IC13403-*1
TPS54327DDAR [EP]GND
1 EN
1 8
VIN
THERMAL
VFB VBST
R13404
10K
9
2 7
C13443 C13410
2 10uF 0.1uF
VREG5
3 6
SW UB85/95/UC97_URSA9core
PANEL_VCC R13407
R13408
DCDC_ROHM R13411-*1
4.87K
1/16W
16V SS GND 39K
IC13403 4 5 100
R13424 R1
1%
3 BD9D320EFJ [EP]FIN 1/16W
1/16W 1%
L13409 10K 5%
1%
1/16W
91K
R13406
MLB-201209-0120P-N2
C13403
R13411R13409
[EP]
GND2
GND1
NC_3
TRIP
4 EN VIN
1/16W 1/16W
1 8 1000pF
5.1K
VO
16V 50V R2
1%
1/16W
27K
R13405
THERMAL
1%
R13410
0.1uF
1%
1/16W
20K
5 R13421 R13422 FB BOOT C13447
28
27
26
25
24
9
2 7
RF FB
0
L13410 R1 1 23
5%
18K 3.6K L13412
6 MLB-201209-0120P-N2 1% 1% THERMAL
C13434 C13435 C13440 C13442 VREG SW 2.2uH PGOOD GND
10uF 0.1uF 10uF 0.1uF 3 6 2 29 22 +12V
UB98/UC9_URSA9core
25V 25V 25V 25V C13444 R13401 1K
100pF NR5040T2R2N EN 3 21 MODE
OPT 50V POWER_ON/OFF2_3 16V
SS GND 0.1uF IC13402
1.0V_DCDC_TI 4
3A 5 C13448
22uF
C13449
22uF
ZD13401 VBST 4
TPS53513RVER
20 VREG L13402
R13403
10V 10V 2.5V
C13446-*1 R13423 C13405 NC_1 VDD
OPT 5 19
4.7
3300pF C13445 C13446 C13402 R13400
22K 2K
50V 1uF 2200pF SW_1 NC_2
1% 6 18
10V 50V
0.1uF 1/16W C13407 C13409
1.0V_DCDC_ROHM SW_2 7 17 VIN_3 C13408
R2 16V 5% 1uF 10uF
VDDC 10uF
10V 16V
L13403 SW_3 8 16 VIN_2 16V
Vout=0.765*(1+R1/R2)=1.516V 1uH
SW_4 9
8A 15 VIN_1
R13402
10
11
12
13
14
1/10W
3.3
D13400
C13400 C13401 C13411
5%
C13406
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
22uF 22uF 22uF
30V
2200pF
ZD13400
50V
2.5V
OPT
C13404
470pF
50V
Vout=0.6*(1+R1/R2)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-134-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
UB85/95/UC89 only
Front speaker
+3.3V_NORMAL
R5613
AMP_RESET_N 100
L5601 R5614 C5627 L5602
1/16W 10uH
BLM18PG121SN1D 4.7K 1000pF
SPK_L+
50V SP-7850_10
AUD_MASTER_CLK
50V
+24V_AMP
PGND1A 22000pF
R5605
C5606
5.6
+24V +24V_AMP 1/10W R5609
C5626 C5620
C5605 0.1uF 4.7K
50V
L5600
10uF
0.1uF [EP]GND C5608 C5624
C5614
390pF
VDD_IO
GND_IO
PVDD1A
PVDD1B
UBW2012-121F 10V 0.1uF 50V
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
35V
C5618
0.47uF SPEAKER_L
50V
AD
C5615
390pF
50V C5621 R5610
R5606 0.1uF
5.6 50V 4.7K
40
39
38
37
36
35
34
33
32
31
1/10W
L5605
NC_1 1 30 OUT1B 10uH
SPK_L-
SP-7850_10
VDD_PLL 2 29 PGND1B C5610
THERMAL 22000pF
NC_2 3 41 28 BST1B 50V
C5603
1uF
10V GND 4 27 VDR1
NC_3 5 IC5600 26 NC_4
C5604
1uF
10V
DVDD 6 NTP7514 25 AGND
AUD_LRCH
SDATA 7 24 VDR2
From DACLRCH
WCK 0x54 BST2A
C5612
1uF
C5613
1uF
AUD_LRCK 8 23 10V 10V
AUD_SCK
BCK 9 22 PGND2A C5611
22000pF
R5602
I2C_SDA2
100 SDA 10 21 OUT2A 50V
R5603
100
11
12
13
14
15
16
17
18
19
20
I2C_SCL2
C5601 C5602
33pF 33pF L5603
50V 50V 10uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+
SP-7850_10
+3.3V_NORMAL +24V_AMP
R5607
5.6
1/10W C5622 R5611
R5601 0.1uF 4.7K
10K C5616 C5619 50V
C5625 390pF 0.47uF
R5604 C5609 0.1uF
50V
50V
C5617
50V
SPEAKER_R
C 100 10uF 390pF
35V 50V
R5600 C5600 C5623 R5612
B Q5600 C5607
AMP_MUTE 1000pF 0.1uF 4.7K
MMBT3904(NXP) R5608
10K 50V 22000pF 5.6 50V
E L5604
50V 1/10W
I2S_AMP
10uH
SPK_R-
SP-7850_10
WOOFER_MUTE
I2S_AMP
WAFER-ANGLE
SPK_L+
4
SPK_L-
3
SPK_R+
2
SPK_R-
1
P5400
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-056-02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
UB85/95 : Woofer Amp
UC97 : Height Amp
UB85/95/UC97 only OPTION Selection
Woofer/Height_Amp Woofer_Amp Height_Amp
UB85/95
UC97
+3.3V_NORMAL
+3.3V_NORMAL
R5713
50V
AMP_RESET_N 100
R5714 C5725
22000pF
1/16W
C5705
L5701 4.7K 1000pF +24V_AMP_WOOFER_L
50V
BLM18PG121SN1D
AUD_MASTER_CLK
4.7K R5702
C5707 C5718
0.1uF
C5720 10uF 50V
+24V_AMP_WOOFER_L C5704 35V
+24V
[EP]GND
10uF
0.1uF
VDD_IO
GND_IO
PGND1A
PVDD1A
PVDD1B
10V SPK_WOOFER_L+
16V R5703
CLK_I
RESET
BST1A
OUT1A
L5700 5.6
UBW2012-121F 1/10W L5702
10uH C5716 R5705
0.1uF
AD
C5712 50V 4.7K
390pF SP-7850_10
50V C5715
L5703 0.47uF
C5713
10uH 50V
Woofer/Height
390pF C5717
40
39
38
37
36
35
34
33
32
31
50V SP-7850_10 0.1uF R5706
R5704 50V
5.6 4.7K
NC_1 1 30 OUT1B 1/10W
C5702 SPK_WOOFER_L-
1uF
-.Separation Of I2S 10V VDD_PLL PGND1B
2 29 C5709
UB85/95 : Woofer Amp(LRCH) THERMAL 22000pF
UC97 : Height Amp(LRCH1) NC_2 3 41 28 BST1B 50V
GND 4 27 VDR1
R5715
0
C5703 NC_3 5 IC5700 26 NC_4
AUD_LRCH1 1uF
Height_Amp 10V DVDD 6 NTP7514 25 AGND
R5716
From DACLRCH AUD_LRCH
0 SDATA 7 24 VDR2
Woofer_Amp
WCK 0x56 BST2A
C5711
1uF
C5714
1uF
AUD_LRCK 8 23 10V 10V
AUD_SCK
BCK 9 22 PGND2A C5710
22000pF
R5700 50V
I2C_SDA2
100 SDA 10 21 OUT2A
R5701
100
11
12
13
14
15
16
17
18
19
20
I2C_SCL2
C5700 C5701
33pF 33pF
50V 50V
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_WOOFER_R+
Height_Amp
+24V_AMP_WOOFER_L
Woofer_Amp
R5709 Height_Amp
3.3 L5704
Height_Amp 10uH C5723 R5711
1/10W Height_Amp
R5707 0.1uF 4.7K
SP-7850_10 Height_Amp 50V
4.7K
C5726 Height_Amp C5722
C5719 390pF 0.47uF
WOOFER_MUTE C5708 0.1uF
50V
50V L5705 50V Height
Height_Amp
C5721 10uH
10uF 390pF Height_Amp Height_Amp
35V 50V SP-7850_10 Height_Amp C5724 R5712
C5706
R5710 0.1uF 4.7K
22000pF 3.3 Height_Amp 50V
50V 1/10W
SPK_WOOFER_R-
Woofer_Amp
R5708
4.7K
I2S_WOOFER
WAFER-ANGLE WAFER-ANGLE
SPK_WOOFER_L+
4 2
I2S_WOOFER
SPK_WOOFER_L-
3 1
SPK_WOOFER_R+
2
FW25001-02(SPK 2P)
P5701
SPK_WOOFER_R-
1
Woofer_Amp
P5700 UB85/95
Height_Amp
UC97
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-057-02-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Repair Guide
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
3 A. Video error Picture broken/ Freezing 3
4 Color error 4
Vertical/Horizontal bar, residual image,
5 5
light spot, external device color error
6 No power 6
B. Power error Off when on, off while viewing, power
7 7
auto on/off
8 No audio/Normal video 8
C. Audio error
9 Wrecked audio/discontinuation/noise 9
10 Remote control & Local switch checking 10
11 MR13 operating checking 11
12 D. Function error Wifi operating checking 12
13 Camera operating checking 13
14 External device recognition error 14
15 E. Noise Circuit noise, mechanical noise 15
16 F. Exterior error Exterior defect 16
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
No video/ Normal audio Revised date 1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable, Speaker Cable, IR B/D Cable,,,)
☞A1 ☞A18
No video Normal Y Check Back Light Y Check Power Normal Y Replace T-con/Main
Normal audio On Board or module
audio On with naked eye Board voltage
24V, 12V,3.5V etc. And Adjust VCOM
N N N
Move to No Check Power Board 24V output Repair Power
☞A18
video/No audio Board or parts
Replace Inverter
Normal Y
or module
voltage
End
N
Repair Power
Board or parts
※Precaution ☞A4 & A2
Always check & record S/W Version and White
Replace Main Board Re-enter White Balance value
Balance value before replacing the Main Board
1
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
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Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
No video/ No audio Revised date 2/16
☞A18
Check various Check and
Y
No Video/ voltages of Power Normal
replace
No audio Board ( 3.5V,12V,20V voltage?
MAIN B/D
or 24V…)
N End
Replace Power
Board and repair
parts
2
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
Picture broken/ Freezing Revised date 3/16
. By using Digital signal level meter
☞ A3
. By using Diagnostics menu on OSD
Check RF Signal level ( Setting→ Quick Setting → Programmes → Programme Tuning → Manual Tuning → Check the Signal )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Y Check whether other equipments have problem or not.
Normal
(By connecting RF Cable at other equipment)
Signal?
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
☞ A4
Check RF Cable
Normal Y Check SVC N Check Y
Connection Close
1. Reconnection Picture? S/W Version Bulletin? Tuner soldering
2. Install Booster N
Y
N
S/W Upgrade
N Contact with signal distributor
Normal
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture? Replace
Main B/D
Y
Close
Close
3
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Standard Repair Process
Established
Error A. Video error date 2013.01.31
LCD TV symptom
Color error Revised date 4/16
☞A6 ☞ A7
※ Check
Check color by input
Y
and replace
Y Y
-External Input
Color Link Cable Color Color
-COMPONENT Replace Main B/D Replace module
error? (V by one) error? error?
-AV
and contact
-HDMI N N N
condition
Check error End
color input
mode
☞A8 Check
External Input/ External device Y
external
Check Test pattern Component /Cable Replace Main/T-con B/D
device and
error normal
cable
N
Request repair
for external
device/cable
N
Check external External device Y
HDMI
device and /Cable Replace Main/T-con B/D
error
cable normal
4
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
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Standard Repair Process
A. Video error Established
Error date 2013.01.31
LCD TV symptom Vertical / Horizontal bar, residual image,
light spot, external device color error Revised date 5/16
Vertical/Horizontal bar, residual image, light spot Replace
Module
☞A6
☞ A7 N
Check color condition by input Check external
Check and
-External Input Screen Y device Y Screen N Replace Main/T-con B/D Screen
-Component Normal? replace Link
normal? connection normal? (adjust VCOM) normal?
-HDMI Cable
condition
N N For LGD panel Y
Y
Replace Main B/D
Replace Request repair End End
module for external
☞A8 device
Check Test pattern
For other panel
External device screen error-Color error
Check screen
Check S/W Version N condition by input External
Check
-External Input Input Connect other external N
version
-Component error device and cable Screen Replace
-HDMI/DVI (Check normal operation of normal? Main/T-con
Y External Input, Component, B/D
Component RGB and HDMI/DVI by
Y
S/W Upgrade error connecting Jig, pattern
Generator ,Set-top Box etc.
Request repair for
external device
Y
Connect other external
Normal N HDMI/
device and cable N
screen? DVI
(Check normal operation of Screen Replace
External Input, Component, normal? Main /T-con
Y RGB and HDMI/DVI by B/D
connecting Jig, pattern
Generator ,Set-top Box etc.
End
5
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Standard Repair Process
Established
Error B. Power error date 2013.01.31
LCD TV symptom
No power Revised date 6/16
☞A17 ☞A18
DC Power on Replace
Check Power LED Y Normal N Check Power Y
by pressing Power Key OK? Power
Logo LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red or Turn On
N Y
. Operating: Turn Off
Check Power cord Replace Main B/D
was inserted properly
☞A18
N Measure voltage of each output of Power B/D
Normal?
Y
Y Y
※ Normal
voltage?
Replace Main B/D
Close Normal
Check ST-BY 3.5V
Y
voltage? N
☞A18 Replace Power B/D
N
Replace Power
B/D
6
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
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Standard Repair Process
Established
Error B. Power error date 2013.01.31
LCD TV symptom
Off when on, off while viewing, power auto on/off Revised date 7/16
Check outlet
☞A19
N Y
Check A/C cord Error? Check Power Off CPU
Replace Main B/D Normal? End
Mode Abnormal
N
Check for all 3- phase
power out Y Abnormal Replace Power B/D
1
Fix A/C cord & Outlet ☞A18
and check each 3
(If Power Off mode
phase out
is not displayed) Normal Y
Replace Main B/D
Check Power B/D voltage?
voltage
N
※ Caution
Check and fix exterior Replace Power B/D
of Power B/D Part
* Please refer to the all cases which Status Power off List Explanation
"POWEROFF_REMOTEKEY" Power off by REMOTE CONTROL
can be displayed on power off mode.
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
Normal "POWEROFF_ONTIMER" Power off by ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF_UNKNOWN" Power off by unknown status except listed case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
7
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Standard Repair Process
Established
Error C. Audio error date 2013.01.31
LCD TV symptom
No audio/ Normal video Revised date 8/16
☞A20 ☞A21+A18
No audio
Check user N Check audio B+
Normal Y
menu > Off 24V of Power
Screen normal voltage
Speaker off Board
Y N
Cancel OFF Replace Power Board and repair parts
Check N
Disconnection Replace MAIN Board End
Speaker
disconnection
Y
Replace Speaker
8
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Standard Repair Process
Established
Error C. Audio error date 2013.01.31
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Wrecked audio/
☞A21+A18
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (24V)
connector
Check input all audio
signal Y Y
Signal
-RF
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV
N
Wrecked audio/
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
Request repair to external Wrecked audio/ Replace Main B/D End
cable/ANT provider Discontinuation/
Noise only
for External Input
(In case of N
External Input Connect and check Normal
signal error) other external audio?
Check and fix device
external device Y
Check and fix external device
9
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Standard Repair Process
D. Function error Established
Error date 2013.01.31
LCD TV symptom
Remote control & Local switch checking Revised date 10/16
1. Remote control(R/C) operating error Replace
Main B/D
☞A22 ☞A22 ☞A22
Check & Repair N Check B+ Y Y
Check R/C itself Normal Y Normal Normal Check IR Normal
operating? Cable connection operating? 3.5V Voltage? Signal?
Operation Output signal
Connector solder On Main B/D
N
Y N N
☞A18
Check R/C Operating Check & Replace Close Check 3.5v on Power B/D Repair/Replace
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal Y
operating? Close
Explain the customer
cause is interference
from light in room. N
Replace R/C
10
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Standard Repair Process
D. Function error Established
Error date 2013.01.31
LCD TV symptom
MR13 operating checking Revised date 11/16
2. MR13(Magic Remocon) operating error
☞A4
Check the N Check MR13
RF Receiver ver Normal Y Press the Is show ok N Turn off/on the
INSTART menu is “00.00”? itself Operation operating? set and press
wheel message?
the wheel
N
Y
Y
☞A23
Check & Replace Close
Check & Repair Battery of MR13
RF assy
connection
Normal Y
☞A4 operating? Close
Is show ok N Press the back
RF Receiver ver N message? key about 5sec
Close N
is “00.00”?
Y
Replace
MR13
Y Close
Down load the Firmware
* If you conduct the loop at 3times, change the M4.
* INSTART MENU14.RF
Remocon Test3. Firmware
download
11
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Standard Repair Process
D. Function error Established
Error date 2013.01.31
LCD TV symptom
Wifi operating checking Revised date 12/16
3.Wifi operating error
☞A4 ☞A24
Check the Wi-Fi Mac value N Check the Wifi wafer Normal N Replace
INSTART menu is “NG”? Voltage?
1pin Main B/D
Y
☞A24 Y
Check & Repair Close
Wifi cable
connection
☞A4
Wi-Fi Mac value N
is “NG”? Close
Y
Change the Wifi
assy
12
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
D. Function error Established
Error date 2013.01.31
LCD TV symptom
Camera operating checking Revised date 13/16
4.Camera operating error
☞A4 ☞A25
Check the Camera Ver. N Check the Camera wafer Normal N Replace
INSTART menu is “NULL”? Voltage?
P4200 12,13pin Main B/D
Y
☞A25 Y
Check & Repair Close
Camera cable
connection
☞A4
Camera Ver. N
is “NULL”? Close
Y
Change the
Camera assy
13
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Only for training and service purposes
Standard Repair Process
Established
Error D. Function error date 2013.01.31
LCD TV symptom
External device recognition error Revised date 14/16
Y Check technical
Check External Input and
Signal information Technical N
input Component Replace Main B/D
input? - Fix information information?
Recognition error
signal
- S/W Version
N Y
HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information
14
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Only for training and service purposes
Standard Repair Process
Established
Error E. Noise date 2013.01.31
LCD TV symptom
Circuit noise, mechanical noise Revised date 15/16
Identify
Circuit Check location of
nose Replace PSU
noise noise
type
Mechanical Check location of
noise noise
※ When the nose is severe, replace the module
※ Mechanical noise is a natural (For models with fix information, upgrade the
phenomenon, and apply the 1st level S/W or provide the description)
description. When the customer does not OR
agree, apply the process by stage. ※ If there is a “Tak Tak” noise from the
※ Describe the basis of the description cabinet, refer to the KMS fix information and
in “Part related to nose” in the Owner’s then proceed as shown in the solution manual
Manual. (For models without any fix information,
provide the description)
15
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Only for training and service purposes
Standard Repair Process
Established
Error F. Exterior defect date 2013.01.31
LCD TV symptom
Exterior defect Revised date 16/16
Zoom part with Module
Replace module
exterior damage damage
Cabinet
Replace cabinet
damage
Remote
controller Replace remote controller
damage
Stand
Replace stand
dent
16
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process Detail Technical Manual
No. Error symptom Content Page Remarks
1 A. Video error_ No video/Normal Check LCD back light with naked eye A1
2 audio Check White Balance value A2
TUNER input signal strength checking
4 A3
method
A. Video error_ video error /Video
5 lag/stop LCD-TV Version checking method A4
6 Tuner Checking Part A5
A. Video error _Vertical/Horizontal bar,
7 LCD TV connection diagram A6
residual image, light spot
Check Link Cable (EPI) reconnection
8 A7
A. Video error_ Color error condition
9 Adjustment Test pattern - ADJ Key A8
10 Exchange Main Board (1) A-1/5
11 Exchange Main Board (2) A-2/5
12 Defected Type caused by T-Con/ Exchange Power Board (PSU) A-3/5
Inverter/ Module
13 Exchange Module (1) A-4/5
14 Exchange Module (2) A-5/5
Continue to the next page
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Only for training and service purposes
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No. Error symptom Content Page Remarks
16 Check front display LED A17
B. Power error_ No power
17 Check power input Voltage & ST-BY 3.5V A18
B. Power error_Off when on, off
18 POWER OFF MODE checking method A19
while viewing
Checking method in menu when there is
19 A20
C. Audio error_ No audio/Normal no audio
video Voltage and speaker checking method
20 A21
when there is no audio
Remote controller operation checking
21 A22
method
Motion Remote operation checking
22 D. Function error A23
method
23 Wifi operation checking method A24
24 Camera operation checking method A25 Not Used
25 E. Etc Tool option changing method A26
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2013.01.31
LCD TV Revised
Content Check LCD back light with naked eye A1
date
<49/55UB850X-XX>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from locations.
* Tuner is different from region
A1
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2014.02.14
LCD TV Revised
Content Check White Balance value A2
date
Entry
Entrymethod
method
1.1.Press
Pressthe
theADJ
ADJbutton
buttonononthe
theremote
remotecontroller
controllerforforadjustment.
adjustment.
2.2.Enter
Enterinto
intoWhite
WhiteBalance
Balanceofofitem
item6.10.
3.3.After
Afterrecording
recordingthe
theR,R,G,G,B B(GAIN,
(GAIN,Cut)
Cut)value
valueofofColor
ColorTemp
Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm),re-enterre-enterthe
thevalue
valueafter
afterreplacing
replacingthe
theMAIN
MAINBOARD.
BOARD.
A2
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
A. Video error_Video error, video lag/stop 2014.02.14
symptom date
LCD TV Revised
Content TUNER input signal strength checking method A3
date
Quick Settings Programmes Programme Tunning
Manual Tuning
When the signal is strong, use the
attenuator (-10dB, -15dB, -20dB etc.)
A3
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Video error, video lag/stop date
2014.02.14
LCD TV Revised
Content LCD-TV Version checking method A4
date
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller for adjustment
A4
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Video error, video lag/stop 2014.02.14
LCD TV date
Revised
Content TUNER checking part A5
date
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.
A5
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Standard Repair Process Detail Technical Manual
Error A. Video error _Vertical/Horizontal bar, Established 2014.02.14
symptom residual image, light spot date
LCD TV Revised
Content LCD TV connection diagram (1) date A6
As the part connecting to the external input, check
the screen condition by signal
A6
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Color error date
2014.02.14
LCD TV Revised
Content Check Link Cable (LVDS) reconnection condition date A7
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7 * Tuner is different from region
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
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Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Color error 2014.02.14
LCD TV date
Adjustment Test pattern - ADJ Key Revised
Content date A8
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
Solder defect, CNT Broken T-Con
T-Con Defect,
Defect,
Solder
T-Con CNT
CNT
defect,CNT
Defect, Broken
Broken
CNTBroken
Broken Abnormal Power Section
Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack
A - 1/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (2)
Abnormal Power Section Abnormal Power Section Solder defect, Short/Crack
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
GRADATION Noise GRADATION
A - 2/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Power Board (PSU)
No Light Dim Light
Dim Light Dim Light
No picture/Sound Ok
A - 3/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (1)
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Crosstalk Press damage Crosstalk
Un-repairable Cases
In this case please exchange the module.
Press damage
A - 4/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (2)
Vertical Block Vertical Line Vertical Block
Source TAB IC Defect Source TAB IC Defect Source TAB IC Defect
Horizontal
TAB ICBlock
Horizontal Block Horizontal line
Gate Defect Gate TAB IC Defect
Gate TAB IC Defect Gate TAB IC Defect Gate TAB IC Defect
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom B. Power error _No power date
2014.02.07
LCD TV Revised
Content Check front Power Indicator date A17
<49/55UB850X-XX>
ST-BY condition: On or Off
Power ON condition: Turn Off
A17
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
B. Power error _No power 2014.02.05
LCD TV date
Revised
Content Check power input voltage and ST-BY 3.5V A18
date
Check the DC 24V, 12V, 3.5V.
P_main
Maker : Yeonho
28Pin SMAW200-H28S5K
28Pin map (LPB)
1 PWR ON 2 DVR_ON
3 P_DIM #1 4 PDIM #2
5 3.5V 6 GND
7 3.5V 8 3.5V
9 GND 10 GND
11 12V 12 12V
13 12V 14 12V
15 12V 16 GND
17 GND 18 24V
19 24V 20 24V
21 24V 22 24V
23 GND 24 GND
25 SCLK 26 GND
27 SIN 28 VSYNC
A18
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Standard Repair Process Detail Technical Manual
Error
symptom B. Power error _Off when on, off whiling viewing Established
date
2014.02.05
LCD TV Revised
Content POWER OFF MODE checking method date A19
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
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Standard Repair Process Detail Technical Manual
Error Established
symptom C. Audio error_No audio/Normal video 2014.02.05
LCD TV date
Revised
Content Checking method in menu when there is no audio date A20
Checking method
1. Press the Setting button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Out
4. Select TV Speaker
A20
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Standard Repair Process Detail Technical Manual
Error Established
symptom C. Audio error_No audio/Normal video date
2014.02.05
LCD TV Revised
Content Voltage and speaker checking method A21
when there is no audio date
<49/55UB850X-XX>
1 PWR ON 2 DVR_ON
3 P_DIM #1 4 PDIM #2
5 3.5V 6 GND
7 3.5V 8 3.5V
①
9 GND 10 GND
② 11 12V 12 12V
13 12V 14 12V
15 12V 16 GND
17 GND 18 24V
19 24V 20 24V
21 24V 22 24V
23 GND 24 GND
25 SCLK 26 GND
27 SIN 28 VSYNC 1 SPK_R-
2 SPK_R+
③
3 SPK_L-
4 SPK_L+
Checking order when there is no audio
1.Check the contact condition of or 24V connector of Main Board
2. Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
3.Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
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Standard Repair Process Detail Technical Manual
Error Established
D. Function error 2014.02.07
symptom date
LCD TV Revised
Content Remote controller operation checking method date A22
<49/55UB850X-XX>
1 GND
Front
2 +3.5V WOL
3 BT_RESET
4 USB_DM
5 NC
6 USB_DP
7 WOL
8 GND
Back
9 SDA
10 GND
11 SCL
12 KEY1
13 GND
14 KEY2
③ 15 IR
16 +3.5V_ST
② 17 LED_R
① Wifi/ BT Combo 18 GND
Checking order to check remote controller
Checking order
1.Check IR cable condition between IR & Main board.( Check picture number① and ②)
2.Check the standby 3.5V on the terminal 16 pin (③)
3.AS checking the Pre-Amp(IR LED light) , the power is in ON condition, an Analog Tester
needle should move slowly, otherwise, it’s defective.
A22
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Standard Repair Process Detail Technical Manual
Error Established
D. Function error 2014.02.07
symptom date
LCD TV Revised
Content Motion Remote / Wifi operation checking method date A23
<49/55UB850X-XX>
1 GND
Front
2 +3.5V WOL
3 BT_RESET
4 USB_DM
5 NC
6 USB_DP
7 WOL
8 GND
Back
9 SDA
10 GND
11 SCL
12 KEY1
13 GND
14 KEY2
③ 15 IR
16 +3.5V_ST
②
17 LED_R
① Wifi/ BT Combo 18 GND
Checking order to check motion remote/wifi
Checking order
1.Check BT/Wifi cable condition between BT/Wifi assy & Main board.
2.Check the 3.5V on the terminal 16
A23
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Standard Repair Process Detail Technical Manual
Error Established
E. Etc 2014.02.05
symptom date
LCD TV Revised
Content Tool option changing method date A26
<49/55UB850X-XX>
① ②
Changing method
1. Contact the USB memory. (USB 1,2,3 jack)
2. Enter the password. (ex. 000000)
* Access USB Memory has each password.
A30
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
