LG 65EC9700

Internal Use Only North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com LED TV SERVICE MANUAL CHASSIS : EC41E MODEL : 65EC9700 65EC9700-CA CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL68662701 (1508-REV00) Printed in Korea

---

CONTENTS CONTENTS ............................................................................................... 2 SAFETY PRECAUTIONS ......................................................................... 3 SERVICING PRECAUTIONS..................................................................... 4 SPECIFICATION........................................................................................ 6 ADJUSTMENT INSTRUCTION............................................................... 13 EXPLODED VIEW ................................................................................... 22 SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX TROUBLE SHOOTING GUIDE ................................................. APPENDIX Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only Only for training and service purposes

---

SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. General Guidance Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet. An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check. power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.) from electrical shocks. and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity. damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA. replace it with the specified. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer. over 1 W), keep the resistor 10 mm away from PCB. Leakage Current Hot Check circuit Keep wires away from high voltage or high temperature parts. Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only Only for training and service purposes

---

SERVICING PRECAUTIONS CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo- NOTE: If unforeseen circumstances create conflict between the sure of the assembly. following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder on page 3 of this publication, always follow the safety precau- ES devices. tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol- der removal devices not classified as “anti-static” can generate General Servicing Precautions electrical charges sufficient to damage ES devices. 1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate source before; electrical charges sufficient to damage ES devices. a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective module or any other receiver assembly. package until immediately before you are ready to install it. b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec- or other electrical connection. trically shorted together by conductive foam, aluminum foil or c. Connecting a test substitute in parallel with an electrolytic comparable conductive material). capacitor in the receiver. 7. Immediately before removing the protective material from the CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate- installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will sion hazard. be installed. 2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir- high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions. FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace- Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the 3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your assemblies. foot from a carpeted floor can generate static electricity suf- 4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.) electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri- (by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F. Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed of contacts in not required. of 60 parts tin/40 parts lead. 5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned. receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire- 6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle. electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners. are correctly installed. 5. Use the following unsoldering technique 7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature. chassis ground before connecting the test receiver positive (500 °F to 600 °F) lead. b. Heat the component lead until the solder melts. Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction- 8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid. service manual. CAUTION: Work quickly to avoid overheating the circuit CAUTION: Do not connect the test fixture ground strap to any board printed foil. heat sink in this receiver. 6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature Electrostatically Sensitive (ES) Devices (500 °F to 600 °F) Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand ily by static electricity. Such components commonly are called against the component lead until the solder melts. Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo- should be used to help reduce the incidence of component dam- nent lead and the foil. age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit 1. Immediately before handling any semiconductor component or board printed foil. semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush. natively, obtain and wear a commercially available discharg- ing wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test. Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only Only for training and service purposes

---

IC Remove/Replacement 3. Solder the connections. Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures. should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique Circuit Board Foil Repair as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit Removal board causing the foil to separate from or "lift-off" the board. The 1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when- gently prying up on the lead with the soldering iron tip as the ever this condition is encountered. solder melts. 2. Draw away the melted solder with an anti-static suction-type At IC Connections solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the the IC. following procedure to install a jumper wire on the copper pattern Replacement side of the circuit board. (Use this technique only on IC connec- 1. Carefully insert the replacement IC in the circuit board. tions). 2. Carefully bend each IC lead against the circuit foil pad and solder it. 1. Carefully remove the damaged copper pattern with a sharp 3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary). (It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern. "Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection. 1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper as possible to the component body. pattern and let it overlap the previously scraped end of the 2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off ing on the circuit board. any excess jumper wire. 3. Bend into a "U" shape the replacement transistor leads. 4. Connect the replacement transistor leads to the corresponding At Other Connections leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the each connection. installation of a jumper wire on the component side of the circuit board. Power Output, Transistor Device Removal/Replacement 1. Remove the defective copper pattern with a sharp knife. 1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous 2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens. 3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern board. break and locate the nearest component that is directly con- 4. Insert new transistor in the circuit board. nected to the affected copper pattern. 5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the 6. Replace heat sink. nearest component on one side of the pattern break to the lead of the nearest component on the other side. Diode Removal/Replacement Carefully crimp and solder the connections. 1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the sible to diode body. it does not touch components or sharp edges. 2. Bend the two remaining leads perpendicular y to the circuit board. 3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board. 4. Securely crimp each connection and solder it. 5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder. Fuse and Conventional Resistor Removal/Replacement 1. Clip each fuse or resistor lead at top of the circuit board hollow stake. 2. Securely crimp the leads of replacement component around notch at stake top. Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only Only for training and service purposes

---

SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application range 3. Test method This specification is applied to the LED TV used EC41E 1) Performance: LGE TV test method followed chassis. 2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IECspecification 2. Requirement for Test Each part is tested as below without special appointment. 1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C 2) Relative Humidity: 65 % ± 10 % 3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. 4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. 5) The receiver must be operated for about 20 minutes prior to the adjustment. 4. Model General Specification No. Item Specification Remarks 1 Market Hong Kong DTV & Analog (1) PAL-I (2) PAL-DK 2 Broadcasting system DTMB : DMB-T (Multi Carrier) + ADTB-T (Single Carrier) (3) NTSC-M (4) DTMB (1) PAL-DK: VHF/UHF 1~69, Cable:1~47 (2) PAL-I: VHF/UHF 1~69 3 Program coverage Cable:1~47 (3) NTSC M: VHF/UHF 2~78 Cable:1~71 (4) DTMB: 21~69 ► DVB-T (Carrier, Code Rate, Constellation, Frame Header, Interleaving) - 3780, 0.4/0.6, 4/16/64QAM, PN945, 720 Analog : Upper Heterodyne 4 Receiving system Digital : COFDM, QAM ► DVB-C - Symbolrate: 4.0 Msymbols/s to 7.2 Msymbols/s - Modulation: 16QAM, 32-QAM, 64-QAM, 128-QAM and 256- QAM 4 System : PAL, SECAM, NTSC, PAL60 5 Video Input (1EA) PAL, NTSC Rear (gender) 6 Component Input (1EA) Y/Cb/Cr, Y/Pb/Pr Rear (gender) PC(HDMI version 1.4) / DTV format, Support HDCP 7 HDMI Input (3EA) Side HDMI1(HDCP2.2), HDMI2(ARC), HDMI3(10bit),HDMI4(MHL) Rear (AV Gender) 8 Audio Input (1EA) Component, AV, DVI Component, AV and DVI use same jack. 9 SPDIF out(1EA) Optical Audio out Rear (1EA) 10 Analog audio out(1EA) Headphone and External speaker out Rear (1EA) Side JPEG, MP3, DivX HD 11 USB Input(3EA) EMF, DivX HD, For SVC (download) (USB 3.0 : 1EA, USB 2.0 : 2EA) 12 Ethernet Lan Jack Rear 13 PCMCIA Card Slot(1EA) Side 14 RS-232C (1EA) For SVC only Rear, Phone type Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only Only for training and service purposes

---

5. External Input Support Format 5.1. Component (Y, PB, PR) No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed 1. 720*480i 15.73 59.94 13.500 SDTV, DVD 480I(525I) 2 720*480i 15.73 60.00 13.514 SDTV, DVD 480I(525I) 3. 720*576i 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz 4 720*480p 31.47 59.94 27.000 SDTV 480P 5 720*480p 31.50 60.00 27.027 SDTV 480P 6 720*576p 31.25 50.00 27.000 SDTV 576P 50Hz 7 1280*720 44.96 59.94 74.176 HDTV 720P 8 1280*720 45.00 60.00 74.250 HDTV 720P 9 1280*720 45.00 50.00 74.250 HDTV 720P 50Hz 10 1920*1080 28.125 50.00 74.250 HDTV 1080I 50Hz, 11 1920*1080 33.72 59.94 74.176 HDTV 1080I 12 1920*1080 33.75 60.00 74.25 HDTV 1080I 13 1920*1080 56.25 50 148.5 HDTV 1080P 14 1920*1080 67.5 60.00 148.5 HDTV 1080P Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only Only for training and service purposes

---

5.2. HDMI : EDID DATA : Refer to adjust specification. (1) DTV Mode No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks 1 640*480 31.469 59.94 25.125 SDTV 480P 2 640*480 31.5 60.00 25.125 SDTV 480P 3 720*480 15.73 59.94 13.500 SDTV, DVD 480I(525I) 4 720*480 15.75 60.00 13.514 SDTV, DVD 480I(525I) Spec. out but display 5 720*576 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz 6 720*480 31.47 59.94 27 SDTV 480P 7 720*480 31.5 60.00 27.027 SDTV 480P 8 720*576 31.25 50.00 27 SDTV 576P 9 1280*720 44.96 59.94 74.176 HDTV 720P 10 1280*720 45 60.00 74.25 HDTV 720P 11 1280*720 37.5 50.00 74.25 HDTV 720P 12 1920*1080 28.125 50.00 74.25 HDTV 1080I 13 1920*1080 33.72 59.94 74.176 HDTV 1080I 14 1920*1080 33.75 60.00 74.25 HDTV 1080I 15 1920*1080 26.97 23.976 63.296 HDTV 1080P 16 1920*1080 27.00 24.000 63.36 HDTV 1080P 17 1920*1080 33.71 29.97 79.120 HDTV 1080P 18 1920*1080 33.75 30.00 79.20 HDTV 1080P 19 1920*1080 56.25 50.00 148.5 HDTV 1080P 20 1920*1080 67.432 59.94 148.350 HDTV 1080P 21 1920*1080 67.5 60.00 148.50 HDTV 1080P 22 3840*2160 53.95 23.98 296.703 UDTV 2160P Only UD Model 23 3840*2160 54 24.00 297.00 UDTV 2160P Only UD Model 24 3840*2160 56.25 25.00 297.00 UDTV 2160P Only UD Model 25 3840*2160 61.43 29.97 296.703 UDTV 2160P Only UD Model 26 3840*2160 67.5 30.00 297.00 UDTV 2160P Only UD Model 27 3840*2160 112.5 50.00 594 UDTV 2160P Only UD Model, Port3 28 3840*2160 135 59.94 593.407 UDTV 2160P Only UD Model, Port3 29 3840*2160 135 60.00 594 UDTV 2160P Only UD Model, Port3 30 4096*2160 53.95 23.98 296.703 UDTV 2160P Only UD Model 31 4096*2160 54 24.00 297 UDTV 2160P Only UD Model 32 4096*2160 56.25 25.00 297 UDTV 2160P Only UD Model 33 4096*2160 61.43 29.97 296.703 UDTV 2160P Only UD Model 34 4096*2160 67.5 30.00 297 UDTV 2160P Only UD Model 35 4096*2160 112.5 50.00 594 UDTV 2160P Only UD Model, Port3 36 4096*2160 135 59.94 593.407 UDTV 2160P Only UD Model, Port3 37 4096*2160 135 60.00 594 UDTV 2160P Only UD Model, Port3 Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only Only for training and service purposes

---

(2) PC Mode No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks 1 640*350 31.468 70.09 25.17 EGA 2 720*400 31.469 70.08 28.32 DOS 3 640*480 31.469 59.94 25.17 VESA(VGA) 4 800*600 37.879 60.31 40 VESA(SVGA) 5 1024*768 48.363 60.00 65 VESA(XGA) 6 1360*768 47.712 60.015 84.75 VESA(WXGA) 7 1152*864 54.348 60.053 80 VESA 8 1280*1024 63.981 60.020 109.00 SXGA Support to HDMI-PC 9 1920*1080 67.5 60 158.40 WUXGA(Reduced Blanking) 10 3840*2160 54 24.00 297.00 UDTV 2160P Only UD Model 11 3840*2160 56.25 25.00 297.00 UDTV 2160P Only UD Model 12 3840*2160 67.5 30.00 297.00 UDTV 2160P Only UD Model 13 4096*2160 53.95 23.97 296.703 UDTV 2160P Only UD Model 14 4096*2160 54 24 297 UDTV 2160P Only UD Model 6. 3D Mode - DTV/HDMI/USB 6.1. RF Input No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks 1 1280*720 37.500 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom 2 1920*1080 28.125 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom 6.2. HDMI Input (1) HDMI 1.4/2.0 (3D Supported mode manually) No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode 1 720*480 31.5 60 27.03 SDTV 480P 2 720*576 31.25 50 27 SDTV 576P 2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Frame Sequential, Row Inter- 45.00 60.00 74.25 HDTV 720P leaving, Column Interleaving 3 1280*720 37.500 50 74.25 HDTV 720P 33.75 60.00 74.25 HDTV 1080I 4 1920*1080 2D to 3D, Side by Side(Half), Top & Bottom 28.125 50.00 74.25 HDTV 1080I 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom, 28.12 25 74.25 HDTV 1080P Checker Board, Row Interleaving, Column 33.75 30.00 74.25 HDTV 1080P Interleaving 5 1920*1080 67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Single Frame Sequential, Row 56.250 50 148.5 HDTV 1080P Interleaving, Column Interleaving 53.95 23.976 296.703 54 24.00 297.00 3840*2160 2D to 3D, 6 56.25 25.00 297.00 HDTV 2160P 4096*2160 Top & Bottom(half), Side by Side(half) 61.43 29.970 296.703 67.5 30.00 297.00 3840*2160 112.5 50 HDTV 2160P 2D to 3D, Top & Bottom(half), Side by Side(half), 7 594 4096*2160 135 60 HDTV 2160P Port3 Only Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only Only for training and service purposes

---

(2) HDMI 1.4b (3D Supported mode automatically) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed Top-and-Bottom Secondary(SDTV 480P) 31.469 / 31.5 59.94/ 60 25.125/25.2 1 Side-by-side(half) Secondary(SDTV 480P) 1 640*480 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P) Frame packing Secondary(SDTV 480P) 62.938/63 59.94/ 60 50.35/50.4 1 Line alternative (SDTV 480P) Top-and-Bottom Secondary(SDTV 480P) 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 Side-by-side(half) Secondary(SDTV 480P) 2 720*480 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P) Frame packing Secondary(SDTV 480P) 62.938/63 59.94 / 60 54/54.06 2,3 Line alternative (SDTV 480P) Top-and-Bottom Secondary(SDTV 576P) 31.25 50 27 17,18 Side-by-side(half) Secondary(SDTV 576P) 3 720*576 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P) Frame packing Secondary(SDTV 576P) 62.5 50 54 17,18 Line alternative (SDTV 576P) Frame packing Secondary(SDTV 576I) Field alternative (SDTV 576I 4 720*576 15.625 50 27 21 Side-by-side(Full) (SDTV 576I Top-and-Bottom Secondary(SDTV 576I) Side-by-side(half) Secondary(SDTV 576I) Top-and-Bottom Primary(HDTV 720P) 37.500 50 74.25 19 Side-by-side(half) Primary(HDTV 720P) 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P) Top-and-Bottom Primary(HDTV 720P) 44.96 / 45 59.94 / 60 74.17/74.25 4 Side-by-side(half) Primary(HDTV 720P) 5 1280*720 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P) Frame packing Primary(HDTV 720P) 75 50 148.5 19 Line alternative (HDTV 720P) Frame packing Primary(HDTV 720P) 89.91/90 59.94 / 60 148.35/148.5 4 Line alternative (HDTV 720P) Top-and-Bottom Secondary(HDTV 1080I) 28.125 50.00 74.25 20 Side-by-side(half) Primary(HDTV 1080I) 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I) Top-and-Bottom Secondary(HDTV 1080I) 33.72 / 33.75 59.94 / 60 74.17/74.25 5 Side-by-side(half) Primary(HDTV 1080I) 6 1920*1080 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I) Frame packing Primary(HDTV 1080I) 56.25 50.00 148.5 20 Field alternative (HDTV 1080I) Frame packing Primary(HDTV 1080I) 67.432/67.50 59.94 / 60 148.35/148.5 5 Field alternative (HDTV 1080I) Top-and-Bottom Primary(HDTV 1080P) 26.97 / 27 23.97 / 24 74.17/74.25 32 Side-by-side(half) Primary(HDTV 1080P) 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P) Top-and-Bottom Secondary(HDTV 1080P) 28.12 25 74.25 33 Side-by-side(half) Secondary(HDTV 1080P) 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P) Top-and-Bottom Primary(HDTV 1080P) 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Side-by-side(half) Secondary(HDTV 1080P) 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P) 7 1920*1080 Frame packing Primary(HDTV 1080P) 43.94/54 23.97 / 24 148.35/148.5 32 Line alternative (HDTV 1080P) Frame packing Secondary(HDTV 1080P) 56.25 25 148.5 33 Line alternative (HDTV 1080P) Frame packing Primary(HDTV 1080P) 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34 Line alternative (HDTV 1080P) Top-and-Bottom Primary(HDTV 1080P) 56.250 50 148.5 31 Side-by-side(half) Secondary(HDTV 1080P) Top-and-Bottom Primary(HDTV 1080P) 67.43 / 67.5 59.94 / 60 148.35/148.50 16 Side-by-side(half) Secondary(HDTV 1080P) Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only Only for training and service purposes

---

(3) HDMI-PC Input (3D) (3D Supported mode manually) No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode 2D to 3D, 1 1024*768 48.36 60 65 HDTV 768P Side by Side(half), Top & Bottom 2D to 3D, 2 1360*768 47.71 60 85.5 HDTV 768P Side by Side(half), 7Top & Bottom 2D to 3D, Side by Side(half), Top & Bottom, 3 1920*1080 67.500 60 148.50 HDTV 1080P Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving 54 24.00 297.00 2D to 3D, 4 3840*2160 56.25 25.00 297.00 HDTV 2160P Top & Bottom(half), Side by Side(half) 67.5 30.00 297.00 2D to 3D, 5 4096*2160 54 24 297.00 HDTV 2160P Top & Bottom(half), Side by Side(half) 640*350 720*400 2D to 3D, 6 Others - - - 640*480 Side by Side(half), Top & Bottom 800*600 1152*864 (4) Component Input (3D) (3D Supported mode manually) No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode 1 1280*720 37.5 50 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom 2 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom 3 1280*720 44.96 59.94 74.176 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom 4 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom 5 1920*1080 33.72 59.94 74.176 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom 6 1920*1080 28.12 50 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom 7 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 8 1920*1080 67.432 59.94 148.352 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 9 1920*1080 27.000 24.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 10 1920*1080 28.12 25 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 11 1920*1080 56.25 50 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 12 1920*1080 26.97 23.976 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 13 1920*1080 33.75 30.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom 14 1920*1080 33.71 29.97 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only Only for training and service purposes

---

(5) USB, DLNA - Movie (3D) (3D supported mode manually) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode 1 Under 704x480 - - - 2D to 3D Over 704x480 Under 2 - - - 2D to 3D, Side by Side(Half), Top & Bottom 1080P interlaced 2D to 3D, Side by Side(Half), Top & Bottom, Check- Over 704x480 - 50 / 60 - er Board, Row Interleaving, Column Interleaving, 3 Under 1080P Frame Sequential progressive 2D to 3D, Side by Side(Half), Top & Bottom, Check- - others - er Board, Row Interleaving, Column Interleaving 2D to 3D, Side by Side(Half), Top & Bottom 4 Over 2160P - 24/25/30/50/60 USB Only (6) USB, DLNA -Photo (3D) (3D supported mode manually) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode 1 Under 320x240 - - - 2D to 3D 2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom (7) USB, DLNA (3D) (3D supported mode automatically) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode 1 1080p 33.75 30 74.25 Side by Side(Half), Top & Bottom, Checker Board, 2 2160p 67.5 30 297 MPO(Photo), JPS(Photo) (8) Miracast, Widi (3D supported mode manually) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode 1 1024*768p - 30/60 - 2 1280*720p - 30/60 - 2D to 3D, Side by Side(Half), Top & Bottom 3 1920*1080p - 30/60 - 4 Others - - - 2D to 3D ■ Remark: 3D Input mode Single Frame Line Column No. Side by Side Top & Bottom Checker board Frame Packing Sequential Interleaving Interleaving L R LLLLL R 1 L R L Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only Only for training and service purposes

---

ADJUSTMENT INSTRUCTION 1. Application Range 3.2. MAC address, ESN, Widevine, HDCP This specification sheet is applied to all of the LED TV with 2.0 key D/L EC41E chassis. (1) Equipment & Condition - Play file: keydownload.exe 2. Designation (2) Communication Port connection 1) Key Write: Com 1,2,3,4 and 115200 (Baudrate) (1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation 2) Barcode: Com 1,2,3,4 and 9600 (Baudrate) transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) Download process (3) The adjustment must be performed in the circumstance of 1) Select the download items. 25 °C ± 5 °C of temperature and 65 % ± 10 % of relative 2) Mode check: Online Only humidity if there is no specific designation. 3) Check the test process : DETECT → MAC_WRITE → (4) The input voltage of the receiver must keep AC 100-240 WIDEVINE_WRITE V~, 50/60 Hz. 4) Play: START (5) The receiver must be operated for about 5 minutes prior to 5) Check of result: Ready, Test, OK or NG the adjustment when module is in the circumstance of over 15 °C. (4) Communication Port connection 1) Connect In case of keeping module is in the circumstance of 0 °C, it : PCBA Jig → RS-232C Port == PC → RS-232C Port should be placed in the circumstance of above 15 °C for 2 hours. In case of keeping module is in the circumstance of below -20 °C, it should be placed in the circumstance of above 15 °C for 3 hours. [Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area. (5) Download 1) AJ/JA Models (14Y LCD TV + MAC + Widevine + ESN Key + HDCP2.0) 3. Automatic Adjustment 3.1. ADC Adjustment ADC adjustment is needed to find the optimum black level and gain in Analog-to-Digital device. 3.1.1. Adjustment method - Using RS-232, adjust items in the other shown in "3.1.2" 3.1.2. Adj. protocol Protocol Command Set ACK Enter adj. mode aa 00 00 a 00 OK00x Source change xb 00 04 b 00 OK04x (Adjust 480i, 1080p Comp1) OKx (Case of Success) Begin adj. ad 00 10 NGx (Case of Fail) Read adj. data ad 00 20 000000000000000000000000007c007b006dx NG 01 00x (Fail) Confirm adj. ad 00 99 OK 01 01x (Success) End adj. aa 00 90 a 00 OK90x 3.1.3. Adj. order - aa 00 00 [Enter ADC adj. mode] - xb 00 04 [Change input source to Component] - ad 00 10 [Adjust Component] - ad 00 90 End adj. Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only Only for training and service purposes

---

3.3. LAN Inspection * Manual Download (Model Name and Serial Number) If the TV set is downloaded by OTA or service man, sometimes 3.3.1. LAN PORT inspection (PING TEST) model name or serial number is initialized.(Not always) Connect SET → LAN Port == PC → LAN Port It is impossible to download by bar code scan, so It need SET PC Manual download. 1) Press the "Instart" key of Adjustment remote control. (1) Play the LAN Port Test Program. 2) Go to the menu "7.Model Number D/L" like below photo. (2) Input IP set up for an inspection to Test 3) Input the Factory model name or Serial number like photo. Program. *IP Number : 12.12.2.2 3.3.2. LAN PORT inspection (PING TEST) (1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN CABLE 4) Check the model name Instart menu. → Factory name displayed. 3.5. WIFI MAC ADDRESS CHECK (1) Using RS232 Command Command Set ACK Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG] (2) Check the menu on in-start. 3.4. Model name & Serial number Download 3.4.1. Model name & Serial number D/L - Press "Power on" key of service remote control. (Baud rate : 115200 bps) - Connect RS232. - Write Serial number by use RS-232C. - Must check the serial number at Instart menu. 3.4.2. Method & notice (1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing Technology Group. (3) Serial number D/L must be conformed when it is produced in production line, because serial number D/L is mandatory by D-book 4.0 Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only Only for training and service purposes

---

3.6. White Balance Adjustment Ex) wb 00 00 → Begin white balance auto-adj. wb 00 10 → Gain adj. 3.6.1. Overview ja 00 ff → Adj. data ▪ W/B adj. Objective & How-it-works jb 00 c0 (1) Objective: To reduce each Panel's W/B deviation ... (2) How-it-works : When R/G/B gain in the OSD is at 192, it ... means the panel is at its Full Dynamic Range. In order to wb 00 1f → Gain adj. completed prevent saturation of Full Dynamic range and data, one *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. of R/G/B is fixed at 192, and the other two is lowered to wb 00 ff → End white balance auto-adj. find the desired value. (3) Adjustment condition : normal temperature ▪ Adj. Map 1) Surrounding Temperature : 25 °C ± 5 °C 2) Warm-up time: About 30 Min Command Data Range (lower case ASCII) (Hex.) Default 3) Surrounding Humidity : 20 % ~ 80 % Adj. item (Decimal) CMD1 CMD2 MIN MAX R Gain j g 00 C0 3.6.2. Equipment G Gain j h 00 C0 (1) Color Analyzer: CA-210 (OLED Module : CH 17) (2) Adjustment Computer(During auto adj., RS-232C protocol B Gain j i 00 C0 Cool is needed) R Cut (3) Adjustment Remote control G Cut (4) Video Signal Generator MSPG-925F 720p/216-Gray B Cut (Model: 217, Pattern: 78) R Gain j a 00 C0 → Only when internal pattern is not available G Gain j b 00 C0 • Color Analyzer Matrix should be calibrated using CS-100. B Gain j c 00 C0 Medium R Cut 3.6.3. Equipment connection MAP G Cut B Cut Color Analyzer R Gain j d 00 C0 Probe RS-232C G Gain j e 00 C0 Computer Warm B Gain j f 00 C0 USB to RS-232 or RS-232C RS-232C R Cut Pattern Generator G Cut Signal Source * If TV internal pattern is used, not needed 3.6.5. Adj. method (1) Auto adj. method 3.6.4. Adj. Command (Protocol) 1) Set TV in adj. mode using POWER ON key. 2) Place optical probe on the center of the display START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP - It need to check probe condition of zero calibration - LEN: Number of Data Byte to be sent before adjustment. - CMD: Command 3) Connect RS-232C Cable. - VAL: FOS Data value 4) Select mode in ADJ Program and begin a adjustment. - CS: Checksum of sent data 5) When WB adjustment is completed with OK message, - A: Acknowledge check adjustment status of pre-set mode(Cool, Medium, Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] Warm) (6) Remove probe and RS-232C cable. ▪ RS-232C Command used during auto-adjustment. RS-232C COMMAND Explanation ▪ W/B Adj. must begin as start command “wb 00 00” , and [CMD ID DATA] finish as end command “wb 00 ff”, and Adj. offset if need. wb 00 00 Begin White Balance adjustment wb 00 10 Gain adjustment(internal white pattern) wb 00 1f Gain adjustment completed wb 00 20 Offset adjustment(internal white pattern) wb 00 2f Offset adjustment completed End White Balance adjustment wb 00 ff (internal pattern disappears ) Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only Only for training and service purposes

---

(2) OLED White balance table 1) Cool Mode 4. Manual Adjustment - Purpose : Especially B-gain fix adjust leads to the 4.1. ADC Calibration luminance enhancement. Adjust the color temperature (1) Enter Service Mode by pushing to reduce the deviation of the module color (2) E nter ADC Calibration by pushing “►” key at “9. ADC temperature. Calibration” - Principle : To adjust the white balance without the (3) Select [Reset] button by pressing Enter key saturation, Adjust the B gain more than 192 ( If R gain (4) Change “OTP” to “Internal” by pushing “►” key or G gain is more than 255 , G gain can adjust less (5) Select [Start] button by pressing Enter key, then it will than 192 ) and change the others ( R/G Gain ). operate ADC adjustment. - Adjustment mode : mode - Cool ADC Calibration ADC Component NG EZ ADJUST 2) Medium ADC SCART RGB OK 0. Tool Option1 ADC Type OPT - Purpose : Adjust the color temperature to reduce the 1. Tool Option2 Start deviation of the module color temperature. 2. Tool Option3 Reset 3. Tool Option4 - Principle : To adjust the white balance without the 4. Tool Option5 ADC Calibration saturation, Fix the B gain to 192 (default data) and 5. Tool Option6 ADC Component NG decrease the others. 6. Tool Option7 7. Area Option ADC SCART RGB OK - Adjustment mode : mode - Medium 8. Continent Detail ADC Type < Internal > 9. ADC Calibration Start 10. White Balance Reset 3) Warm 11. 20 Point WB - Purpose : Adjust the color temperature to reduce the 12. Test Pattern 13. EDID D/L ADC Calibration deviation of the module color temperature. 14. Sub B/C ADC Component OK ADC SCART RGB OK - Principle : To adjust the white balance without the 15. Ext. Input Adjust ADC Type Internal saturation, Fix the W gain to 192 (default data) and Start decrease the others. Reset - Adjustment mode : mode – Warm 4.2. LAN Inspection 4.2.1. Equipment & Condition ▪ Each other connection to LAN Port of IP Hub and Jig 4.2.2. LAN inspection solution ▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation → If automatic setting is finished, you confirm IP and MAC Address. Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only Only for training and service purposes

---

4.3. EDID(The Extended Display Identification (1) EDID # HDMI 1(C/S: 0xE7, 0x04) Data)/DDC(Display Data Channel) download EDID Block 0, Bytes 0-127 4.3.1. Overview 0 1 2 3 4 5 6 7 8 9 A B C D E F It is a VESA regulation. A PC or a MNT will display an optimal 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 resolution through information sharing without any necessity 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 of user input. It is a realization of "Plug and Play". 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 4.3.2. Equipment 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 - Since embedded EDID data is used, EDID download JIG, 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A HDMI cable and D-sub cable are not need. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC - Adjustment remote control 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7 4.3.3. Download method EDID Block 1, Bytes 128-255 (1) Press "ADJ" key on the Adjustment remote control, then 0 1 2 3 4 5 6 7 8 9 A B C D E F select "13.EDID D/L", By pressing "Enter" key, enter EDID 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21 D/L menu. 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 (2) S elect "Start" button by pressing "Enter" key, HDMI1/ 20 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02 HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG. 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C 4.3.4. EDID DATA 50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 ▪ Reference 60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 - HDMI1 ~ HDMI4 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 - In the data of EDID, bellows may be different by Input mode. 0 1 2 3 4 5 6 7 8 9 A B C D E F 0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ # HDMI2 (C/S: 0xE7, 0xF4) 0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 EDID Block 0, Bytes 0-127 0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 0 1 2 3 4 5 6 7 8 9 A B C D E F 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 0x07 ⓓ 01 ⓔ1 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ 0x02 ⓕ 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7 0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E EDID Block 1, Bytes 128-255 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 0 1 2 3 4 5 6 7 8 9 A B C D E F ⓐ Product ID 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21 ⓑ Serial No: Controlled on production line. 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 ⓒ Month, Year: Controlled on production line: 20 09 57 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02 ex) Monthly : ‘01’ → ‘01’, Year : ‘2013’ → ‘17’ 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 ⓓ Model Name(Hex): LGTV 40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C ⓔ Checksum(LG TV): Changeable by total EDID data. 50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 ⓕ Vendor Specific(HDMI) 60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F4 # HDMI3 (C/S: 0xA1, 0x3A) EDID Block 0, Bytes 0-127 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A1 Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only Only for training and service purposes

---

EDID Block 1, Bytes 128-255 4.4. White Balance Adjustment 0 1 2 3 4 5 6 7 8 9 A B C D E F 4.4.1. Overview 0 02 03 55 F1 58 10 9F 04 13 05 14 03 02 12 20 21 ▪ W/B adj. Objective & How-it-works 10 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06 (1) Objective: To reduce each Panel's W/B deviation 20 C0 15 07 50 09 57 07 7C 03 0C 00 30 00 B8 3C 20 (2) How-it-works : When R/G/B gain in the OSD is at 192, it 30 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10 means the panel is at its Full Dynamic Range. In order to 40 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 03 01 prevent saturation of Full Dynamic range and data, one 50 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 of R/G/B is fixed at 192, and the other two is lowered to 60 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E find the desired value. 70 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 3A (3) Adjustment condition : normal temperature 1) Surrounding Temperature : 25 °C ± 5 °C 2) Warm-up time: About 90 Min # HDMI4 (C/S: 0xE7, 0xD4) 3) Surrounding Humidity : 20 % ~ 80 % EDID Block 0, Bytes 0-127 0 1 2 3 4 5 6 7 8 9 A B C D E F 4.4.2. Manual adjustment. method 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 1) Set TV in Adj. mode using POWER ON. 10 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 2) Zero Calibrate the probe of Color Analyzer, then place it 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 on the center of LCD module within 10 cm of the surface. 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 3) Press ADJ key → EZ adjust using adj. R/C → 7. White- 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 Balance then press the cursor to the right(key ►). 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A (When right key(►) is pressed 216 Gray internal pattern 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC will be displayed) 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7 4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value. EDID Block 1, Bytes 128-255 5) Adjustment is performed in COOL, MEDIUM, WARM 3 modes of color temperature. 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21 ** G-fix adjustment 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 Adjust modes (Cool), Fix the G gain to 172 (default data) 20 09 57 07 7C 03 0C 00 40 00 B8 3C 20 C0 8E 01 02 and change the others (G/B Gain). 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 Adjust two modes(Medium / Warm), Fix the one of R/G/B 40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C gain to 192 (default data) and decrease the others. 50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 ▪ If internal pattern is not available, use RF input. In EZ Adj. 60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 menu 7.White Balance, you can select one of 2 Test- 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4 pattern: ON, OFF. Default is inner(ON). By selecting OFF, * Checksum(HDMI 1/2/3/4) you can adjust using RF signal in 216 Gray pattern. Input FFh (Checksum) ▪ Adjustment condition and cautionary items HDMI1 E7 04 1) Lighting condition in surrounding area Surrounding lighting should be lower 10 lux. Try to HDMI2 E7 F4 isolate adj. area into dark surrounding. HDMI3 A1 3A 2) Probe location HDMI4 E7 D4 : Color Analyzer(CA-210) probe should be within 10 cm and perpendicular of the module surface (80° ~ 100°) 3) Aging time - After Aging Start, Keep the Power ON status during 5 Minutes. - In case of LCD, Back-light on should be checked using no signal or Full-white pattern. Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only Only for training and service purposes

---

4.4.3.  R eference (White balance adjusmtment (3) Don't wear a 3D Glasses, Check the picture like below. coordinate and color temperature) ▪ Luminance : 206 Gray ▪ Standard color coordinate and temperature using CS-1000 (over 26 inch) Coordinate Mode Temp ∆uv x y Cool 0.271 0.270 13000 K - 0.0030 Medium 0.286 0.289 9300 K 0.0000 4.7. Option selection per country Warm 0.313 0.329 6500 K + 0.0030 4.7.1. Overview - Option selection is only done for models in AJ/JA/IL. ▪ Standard color coordinate and temperature using CA-210(CH 17) 4.7.2.Method Coordinate (1) Press "ADJ" key on the Adjustment remote control, then Mode Temp ∆uv x y select Country Group Menu. (2) Depending on destination, select Country Group Code or Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K - 0.0030 Country Group then on the lower Country option, select Medium 0.286 ± 0.002 0.289 ± 0.002 9300 K 0.0000 US, CA, MX. Selection is done using +, - or ►◄ KEY. Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K + 0.0030 4.8. Color Sensor Function Inspection This Inspection is available only Power-Only Status. (1) Turn on TV. 4.5. Magic Motion Remote control test (2) Press EYE key of Adj. Remote control. - E quipment : RF Remote control for test, IR-KEY-Code (3) Confirm color sensor raw data for each channel. Remote control for test (4) Cover the Color sensor on the front of the using your hand - You must confirm the battery power of RF-Remote control and wait for 6 seconds. before test(recommend that change the battery per every lot) (5) Confirm that value is lower than 10 of the “Raw Data - Sequence (test) (Sensor data, Backlight)” and “OK” message. 1) If you select the ‘start key(OK)’ on the Adjustment remote If after 6 seconds, value is not lower than 10 and not control, you can pairing with the TV SET. showing the “OK” message, replace color sensor. 2) You can check the cursor on the TV Screen, when select (6) Remove your hand from the color sensor and wait for 6 the "OK" key on the Adjustment remote control. seconds. 3) You must remove the pairing with the TV Set by select (7) Compare step 3) raw data. ‘Mute + OK Key’ on the Adjustment remote control. If the variation is higher than 30 for each channel, replace color sensor. 4.6. 3D function test (Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) * HDMI mode NO. 872 , pattern No.83 (1) Please input 3D test pattern like below. Step 2) Step 3) Step 4) (2) When 3D OSD appear automatically, then select green key. Step 5) Step 6) Step 7) Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only Only for training and service purposes

---

4.9. HDMI ARC Function Inspection 5. GND and Internal Pressure check (1) Test equipment - Optic Receiver Speaker 5.1. Method (1) GND & Internal Pressure auto-check preparation - MSHG-600 (SW: 1220 ↑) - Check that Power Cord is fully inserted to the SET. (If - HDMI Cable (for 1.4 version) loose, re-insert) (2) Perform GND & Internal Pressure auto-check (2) Test method - Unit fully inserted Power cord, Antenna cable and A/V 1) Insert the HDMI Cable to the HDMI ARC port from the arrive to the auto-check process. master equipment (HDMI2). - Connect D-terminal to AV JACK TESTER 2) Check the sound from the TV Set. - Auto CONTROLLER(GWS103-4) ON - Perform GND TEST - If NG, Buzzer will sound to inform the operator. - If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.) - Perform I/P test - If NG, Buzzer will sound to inform the operator. - If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process. 3) Check the Sound from the Speaker or using AV & Optic TEST program (It’s connected to MSHG-600) 5.2. Checkpoint ▪ TEST voltage 4.10. UHD 4K Test - GND: 1.5 KV / min at 100 mA (1) Video Inspection(UDG-4004NS) - SIGNAL: 3 KV / min at 100 mA 1) Insert the HDMI Cable to TV Set. ▪ TEST time: 1 second 2) Convert to HDMI Mode using TV/AV key on ADJ remote ▪ TEST POINT control. - GND TEST = POWER CORD GND & SIGNAL CABLE 3) Inspect the sound and picture operation well. METAL GND (Color condition, Picture noise, Sound distortion etc.) - Internal Pressure TEST = POWER CORD GND & LIVE & 4) Inspection 2D → 3D conversion NEUTRAL ▪ LEAKAGE CURRENT: At 0.5 mArms (2) Pattern Inspection (MSPG-7100) 1) Insert the HDMI Jack to HDMI 1 Port. 2) Convert to UHD Inspection Pattern. (Use remote control) 6. Audio 3) Check Video and Sound. No. Item Min Typ Max Unit 4) Convert to 64 Gray Inspection Pattern. Audio practical max 9 10 12 W EQ Off 5) Check Video and Sound. 1 Output, L/R (Distor- AVL Off 6) Inspect HDMI-CEC function.(Push Play & Pause button) tion=10% max Output) 8.5 8.10 10.8 Vrms Clear Voice Off EQ On (3) If there are HDMI Port 2,3 and 4, do each pattern Inspection. Speaker 2 9 10 12 W AVL On (8 Ω Impedance) Clear Voice On (4) 4K Inspection.(HEVC Inspection model only) 1) Insert USB that 4K video file is saved. Measurement condition: 2) Check that the video plays normally. (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms 4.11. Tool Option selection - Method : Press "ADJ" key on the Adjustment remote control, then select Tool option. Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only Only for training and service purposes

---

7. USB S/W download(Service only) (1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick. - If your downloaded program version in USB Stick, it didn't work. But your downloaded version is new, USB data is automatically detecting.(Download Version High & Power only mode, Set is automatically Download) (3) Show the message "Copying files from memory". (4) Updating is starting. (5) Updating Completed, The TV will restart automatically. (6) If your TV is turned on, check your updated version and Tool option. (explain the Tool option, next stage) * If downloading version is more new than your TV have, TV can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn't have a DTV/ATV test on production line. * After downloading, have to adjust TOOL OPTION again. 1) Push "IN-START" key in service remote control. 2) Select "Tool Option 1" and push "OK" key. 3) Punch in the number. (Each model has their number.) Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only Only for training and service purposes

---

EXPLODED VIEW IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. 710 700 900 400 AV1 811 830 AG1 LV1 LV2 521 Set + Stand 810 522 540 A10 840 530 A22 502 820 541 500 CAM1 570 571 121 501 560 200 120 561 Copyright © LG Electronics. Inc. All rights reserved. - 22 - LGE Internal Use Only Only for training and service purposes

---

System Configuration EEPROM_ST IC102-*1 Clock for LG1154D NVRAM +3.3V_NORMAL M24256-BRMN6TP E0 VCC 1 8 MAIN Clock(24Mhz) E1 2 7 WC EEPROM_RENESAS X-TAL_1 IC102 C103 8pF E2 SCL GND_1 3 6 XIN_MAIN R1EX24256BSAS0A 0.1uF Write Protection C100 VSS 4 5 SDA - Low : Normal Operation A0 VCC 2 1 R108 1 8 - High : Write Protection 24MHz X100 1M EEPROM_ATMEL IC102-*2 AT24C256C-SSHL-T A1 WP 2 7 3 4 A0 VCC 1 8 X-TAL_2 GND_2 8pF XO_MAIN A2 3 A0’h 6 SCL A1 2 7 WP C101 I2C_SCL5 AR102 A2 3 6 SCL VSS SDA I2C_SDA5 4 5 33 GND SDA 4 5 System Clock for Analog block(24Mhz) EB_ADDR[0-14] EMMC_DATA[0-7] EB_DATA[0-7] EPHY_REFCLK EPHY_CRS_DV OPT PLL SET[1:0] : internal pull up EPHY_MDIO EPHY_TXD1 EPHY_TXD0 EPHY_RXD1 EPHY_RXD0 EPHY_MDC R100 33 "00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz) /USB_OCD3 EPHY_EN PLLSET1 /USB_OCD2 USB_CTL3 "01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz) OP MODE[1:0] USB_CTL2 EMMC_CLK EMMC_CMD EMMC_RST R101 33 "10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz) "00" : Normal Mode +3.3V_NORMAL +3.3V_NORMAL EB_ADDR[14] EB_ADDR[13] EB_ADDR[12] EB_ADDR[11] EB_ADDR[10] EB_ADDR[9] EB_ADDR[8] EB_ADDR[7] EB_ADDR[6] EB_ADDR[5] EB_ADDR[4] EB_ADDR[3] EB_ADDR[2] EB_ADDR[1] EB_ADDR[0] EB_DATA[7] EB_DATA[6] EB_DATA[5] EB_DATA[4] EB_DATA[3] EB_DATA[2] EB_DATA[1] EB_DATA[0] EMMC_DATA[7] EMMC_DATA[6] EMMC_DATA[5] EMMC_DATA[4] EMMC_DATA[3] EMMC_DATA[2] EMMC_DATA[1] EMMC_DATA[0] PLLSET0 "11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz) "01/10/11" : Internal Test mode EB_BE_N1 EB_BE_N0 OPT EB_WE_N EB_OE_N INSTANT boot MODE BOOT MODE +3.3V_NORMAL "1 : Instant boot 3.3K 3.3K "0 : EMMC R117 R150 OPT "0 : normal "1 : TEST MODE OPT OPT R133 33 OPM1 (internal pull down) R134 33 INSTANT_BOOT BOOT_MODE +3.3V_NORMAL OPM0 3.3K OPT R118 Jtag I/F For Main AU11 AR10 AT10 AU10 AT11 AR11 T32 K35 K36 K37 L35 H35 H36 J35 J36 H37 G37 G36 G35 F36 F35 E36 E37 E35 D37 D36 D35 C36 C35 B37 B36 B35 C32 B33 A33 C33 A34 B34 C34 A36 Y37 Y36 W35 T36 W36 V35 V37 V36 U35 U36 U37 AU8 AT8 AR8 0.1uF +3.3V_NORMAL INSTANT_MODE0 BOOT_MODE0 EB_CS3/GPIO93 EB_CS2/GPIO92 EB_CS1/GPIO91 EB_CS0/GPIO90 EB_WE_N/GPIO95 EB_BE_N1/GPIO81 EB_WAIT/GPIO94 EB_OE_N/GPIO82 EB_BE_N0/GPIO80 EB_ADDR15/GPIO89 EB_ADDR14/GPIO88 EB_ADDR13/GPIO103 EB_ADDR12/GPIO102 EB_ADDR11/GPIO101 EB_ADDR10/GPIO100 EB_ADDR9/GPIO99 EB_ADDR8/GPIO98 EB_ADDR7/GPIO97 EB_ADDR6/GPIO96 EB_ADDR5/GPIO111 EB_ADDR4/GPIO110 EB_ADDR3/GPIO109 EB_ADDR2/GPIO108 EB_ADDR1/GPIO107 EB_ADDR0/GPIO106 EB_DATA7/GPIO105 EB_DATA6/GPIO104 EB_DATA5/GPIO119 EB_DATA4/GPIO118 EB_DATA3/GPIO117 EB_DATA2/GPIO116 EB_DATA1/GPIO115 EB_DATA0/GPIO114 EMMC_CLK EMMC_CMD EMMC_RESETN EMMC_DATA7 EMMC_DATA6 EMMC_DATA5 EMMC_DATA4 EMMC_DATA3 EMMC_DATA2 EMMC_DATA1 EMMC_DATA0 RMII_REF_CLK RMII_CRS_DV RMII_MDIO RMII_MDC RMII_TXEN RMII_TXD1 RMII_TXD0 RMII_RXD1 RMII_RXD0 OPT R175 3.3K P100 R167 12505WS-10A00 33 T32 HDMI_MUX_SEL 1 TRST_N0 H13D_XTAL_560ohm A26 AL34 2 XIN_MAIN XIN GPIO31 CAM_SLIDE_DET TDI0 R152 560 B26 AM33 XO_MAIN XOUT GPIO30 3 TDO0 AM32 H13D_XTAL_100ohm GPIO29 Compensation_Done 4 AF30 TMS0 R152-*1 100 GPIO28 B27 AN34 5 TCK0 XTAL_BYPASS GPIO27 /RST_PHY AT37 AK34 6 H13DA_XTAL GPIO26 RF_SWITCH_CTL SOC_RESET AL33 10K 10K 10K +3.3V_NORMAL 10K GPIO25 HDMI_HPD_3 7 AL32 GPIO24 HDMI_HPD_2 OPT AR9 For ISP OPT OPT OPT 8 GPIO23/UART2_TX For connecting R163 R160 R166 R168 3.3K AU16 AM5 R103 9 SOC_RESET PORES_N GPIO22/UART2_RX SIC debug tool AM6 10 GPIO21 AUD_LRCH2 To surround amp C108 AD34 AM7 R107 100 11 OPM1 OPM1 GPIO20 0.1uF AD33 AL6 OPM0 OPM0 GPIO19 INSTANT_BOOT AK7 GPIO18 AT26 AK6 H13A_SCL H13DA_SCL GPIO17 SC_DET local dimming AU26 AK5 H13A_SDA H13DA_SDA GPIO16 AV1_CVBS_DET I2C port AJ5 GPIO15 AMP_RESET_N AP9 AJ6 TRST_N0 TRST_N0 GPIO14 COMP1_DET AN9 AJ7 WebOS UHD HW Option TMS0 TCK0 AP11 TMS0 TCK0 GPIO13 GPIO12 AH6 M_RFModule_RESET HP_DET AN11 AG7 TDI0 TDI0 GPIO11 SIL9617_RESET +3.3V_NORMAL AN10 AG6 TDO0 TDO0 GPIO10 /TU_RESET1 AM10 AG5 TRST_N1 GPIO9 U14_RESET AM9 AF5 TMS1 GPIO8 D14_HWRESET AM11 AH30 TCK1 GPIO7 FRC_FLASH_WP AM12 AG30 10K TDI1 GPIO6 /RST_HUB 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K AL11 AN33 BIT6_1 BIT0_1 BIT1_1 BIT7_1 URSA9 TDO1 GPIO5 OLED FHD AL9 AK33 U14 D9 PLLSET1 /TU_RESET2 IC100 PLLSET1 GPIO4 R131 AL10 AE30 PLLSET0 MN864778_RESET R124 R112 R114 R116 R120 R122 R126 R128 R129 PLLSET0 GPIO3 R110 AE34 AD30 BOOT_MODE BOOT_MODE GPIO2 USB3_EN AN32 R105 0 GPIO1 BIT0 Y33 AK32 USB3.0_REDRIVER_CTL D13_INT EXT_INTR3/GPIO70 GPIO0 AMP_RESET_N_1 BIT1 W32 AR101 EPHY_INT 3.3K +3.3V_NORMAL LG1154D_H13D EXT_INTR2/GPIO69 W33 AC32 BIT2 R149 CAM_TRIGGER_DET EXT_INTR1/GPIO68 DDCD0_CK 1/16W W34 AC33 R164 10K H13_CONNECT EXT_INTR0/GPIO67 DDCD0_DA BIT3 AB33 33 5% HPD0 AU12 BIT4 R151 SOC_RX UART0_RXD AT12 AE37 10K SOC_TX UART0_TXD PHY0_ARC_OUT_0 SPDIF_OUT_ARC AU13 AC36 BIT5 M_REMOTE_RX UART1_RXD PHY0_RX0N_0 HDMI_RX0- AT13 AC37 M_REMOTE_TX UART1_TXD PHY0_RX0P_0 HDMI_RX0+ BIT6 AP12 AB36 M_REMOTE_RTS UART1_RTS PHY0_RX1N_0 HDMI_RX1- M_REMOTE_CTS AR12 AB37 BIT7 UART1_CTS PHY0_RX1P_0 HDMI_RX1+ AA36 PHY0_RX2N_0 HDMI_RX2- AE35 AA37 U14 SPI BIT8 SOC_SPI1_CS SPI_CS0/GPIO36 PHY0_RX2P_0 HDMI_RX2+ AE36 AD36 SOC_SPI1_MOSI SPI_DO0/GPIO38 PHY0_RXCN_0 HDMI_CLK- AF36 AD37 BIT9 SOC_SPI1_MISO SPI_DI0/GPIO39 PHY0_RXCP_0 HDMI_CLK+ AF35 SOC_SPI1_SCLK SPI_SCLK0/GPIO37 BIT10 AG34 R32 D13 SPI SOC_SPI0_CS0 SPI_CS1 HUB_PORT_OVER0 /USB_OCD1 AF33 SOC_SPI0_MOSI SPI_DO1 AG33 R33 SOC_SPI0_MISO SPI_DI1 HUB_VBUS_CTRL0 USB_CTL1 AG32 10K SOC_SPI0_SCLK SPI_SCLK1 URSA7/URSA9P 10K 10K 10K 10K 10K 10K 10K R127 LCD 10K 10K 10K R125BIT7_0 R111BIT1_0 NON_U14 BIT0_0 AR15 NOT_D9 BIT6_0 OPT OPT I2C_SCL1 UHD SCL0/GPIO66 AP15 I2C_SDA1 SDA0/GPIO65 R132 AR16 R115 R130 R109 R119 R121 R123 R113 I2C_SCL_MICOM_SOC SCL1/GPIO64 Not Used Net (UB85/95/UC89) AP16 I2C_SDA_MICOM_SOC SDA1/GPIO79 AP17 I2C_SCL2_SOC SCL2/GPIO78 CAM_TRIGGER_DET AR17 I2C_SDA2_SOC SDA2/GPIO77 AP6 H13_CONNECT I2C_SCL4 SCL3 AR6 SOC_SPI1_CS I2C_SDA4 SDA3 CAM_IOIS16_N/GPIO83 AH32 CAM_VCCEN_N/GPIO87 SC_VCC_SEL/GPIO128 SOC_SPI1_MOSI I2C_SCL5 CAM_IREQ_N/GPIO73 CAM_INPACK/GPIO74 CAM_WAIT_N/GPIO84 SC_DETECT/GPIO133 SCL4 AJ33 CAM_CD1_N/GPIO76 CAM_CD2_N/GPIO75 CAM_VS1_N/GPIO86 CAM_VS2_N/GPIO85 CAM_REG_N/GPIO72 SC_VCCEN/GPIO129 SD_DATA3/GPIO121 SD_DATA2/GPIO120 SD_DATA1/GPIO135 SD_DATA0/GPIO134 SOC_SPI1_MISO SC_DATA/GPIO132 SD_CD_N/GPIO123 SD_WP_N/GPIO122 USB3_REFPADCLKM USB3_REFPADCLKP I2C_SDA5 SDA4 SC_CLK/GPIO130 SC_RST/GPIO131 SD_CLK/GPIO125 SD_CMD/GPIO124 USB2_2_TXRTUNE USB2_1_TXRTUNE USB2_0_TXRTUNE 20131016 version AH34 SOC_SPI1_SCLK I2C_SCL6 SCL5 AH33 CAM_SLIDE_DET USB3_RESREF I2C_SDA6 SDA5 USB2_2_DP0 USB2_2_DM0 USB2_1_DP0 USB2_1_DM0 CAM_CE1_N CAM_CE2_N CAM_RESET USB2_0_DP USB2_0_DM USB3_RX0P USB3_RX0M USB3_TX0P USB3_TX0M AUD_LRCH2 BIT(0/1) DVB ATSC JP USB3_DP0 USB3_DM0 GPIO136 GPIO137 GPIO138 GPIO139 AMP_RESET_N_1 00 TW/COL North.AM. U14_RESET NC_1 NC_2 NC_3 NC_4 01 CN/HK /RST_HUB KR JP AMP_RESET_N_1 10 BR F33 F34 D32 E32 G32 G33 F32 G34 D33 H32 E33 D34 H33 T33 U33 T32 V32 V33 V34 A25 C25 B25 E25 D25 E24 D24 C24 L37 L36 K34 M37 M36 K33 AU7 AT7 AP7 P37 P36 N36 N37 R36 R37 N34 P33 P32 L32 L33 M31 AJ31 J32 J33 K32 J34 EU M_REMOTE_RX M_REMOTE_TX 11 AJJA I2C_SDA_MICOM I2C_SDA_MICOM_SOC AR100 M_REMOTE_RTS +3.3V_LNA_TU +3.3V_TUNER I2C_SCL_MICOM 33 I2C_SCL_MICOM_SOC M_REMOTE_CTS 200 1% High Low +3.3V_NORMAL +3.3V_NORMAL 0 R102 0.1uF 0.1uF I2C_SDA2 I2C_SDA2_SOC BIT2 Resolution FHD UHD I2C PULL UP 0 R104 200 1% I2C_SCL2 I2C_SCL2_SOC R159 200 1% R157 200 1% KR_PIP_NOT BIT3 Support U14 U14 Non_U14 R162 R147-*1 R148-*1 KR_PIP_NOT Not Used Net (Only OLED) C104 C105 R135 1.8K R136 1.8K R137 1.8K R138 1.8K R141 1.8K R142 1.8K R143 1.8K R144 1.8K R146 1.8K R147 4.7K R148 4.7K R145 1.8K CAMERA_DP CAMERA_DM HUB_DP HUB_DM WIFI_DP WIFI_DM BIT4 D9 Model D9 Non_D9 3.3K 3.3K DPC_CTL /PCM_CE1 /PCM_CE2 CAM_CD1_N CAM_CD2_N CAM_IREQ_N PCM_RESET PCM_5V_CTL CAM_WAIT_N CAM_REG_N SMARTCARD_PWR_SEL/SD_EMMC_DATA[1] I2C_CH1_pullup_4.7K I2C_CH1_pullup_3.3K BIT5 URSA7/URSA9 URSA9 URSA7/URSA9P R161 DPC_CTL I2C_CH1_pullup_4.7K SIL9617_INT R9531_RESET R9531_FLASH_WP I2C_SDA1 I2C_CH1_pullup_3.3K SMARTCARD_CLK/SD_EMMC_DATA[0] SMARTCARD_DET/SD_EMMC_DATA[3] SMARTCARD_RST/SD_EMMC_DATA[2] R147-*2 R148-*2 I2C_SCL1 Not Used Net (Only OLED 77EC98) BIT(6/7) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP SMARTCARD_DATA/SD_EMMC_CLK AMP_RESET_N 1.2K 1.2K SMARTCARD_VCC/SD_EMMC_CMD I2C_SDA_MICOM_SOC R135-*1 1.5K Only SMART CARD R136-*1 1.5K 00 T/C T/C T/C Default ATSC_PIP ATSC_PIP ISDB_PIP Default I2C_SCL_MICOM_SOC I2C_CH1_pullup_1.2K interface I2C_SDA2_SOC I2C_CH1_pullup_1.2K KR_PIP 01 T2/C/S2/ATV_EXT T2/C_PIP T2/C_PIP ATV_SOC ATV_SOC ISDB KR_PIP +3.3V_NORMAL R154 USB3_DP USB3_DM USB3_RX0P USB3_RX0M USB3_TX0P USB3_TX0M I2C_SCL2_SOC R155 R153 10K 10K CI 10K CI T2/C T2/C I2C_SDA4 CI 10 T2/C ATV_EXT ATV_EXT I2C for tuner AC-coupling CAP I2C_SCL4 Place near by LG1154D 11 T2/C/S2/AT T2/C/S2 I2C_SDA5 I2C_SCL5 High Low I2C_SDA6 I2C_SCL6 I2C for tuner BIT8 Display OLED LCD BIT9 Reserved BIT10 Reserved THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-001-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. H13 D CHIP Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

LG1154A LG1154D LG1154A IC100 H13A_NON_BRAZIL LG1154D_H13D IC100 IC101 +3.3V_Bypass Cap +0.75V VREF_M0_0 LG1154D_H13D A27 Y5 AVDD33 LG1154AN_H13A VREF_M0_1 A24 B5 GND_1 GND_2 GND_185 GND_186 Y8 N21 C5 Y12 +3.3V_NORMAL AVDD33 (2) +3.3V_NORMAL +3.3V_NORMAL +1.24V_Bypass Cap VREF_M1_0 A4 M0_DDR_VREF1 M0_DDR_VREF2 VDDC11_1 VDDC11_2 N22 +1.1V C26 C27 D5 GND_3 GND_4 GND_5 GND_187 GND_188 GND_189 Y13 Y14 Y15 GND_6 GND_190 AVDD33_XTAL(1) AVDD33_CVBS(2) VREF_M1_1 A2 N23 D26 GND_7 GND_191 Y16 Y17 E11 H14 M1_DDR_VREF1 VDDC11_3 E5 GND_8 GND_192 VDD33_1 +1.2V_VDD Y1 P15 E6 Y18 GND_30 L209 L216 M1_DDR_VREF2 VDDC11_4 E7 GND_9 GND_193 Y19 F5 J4 BLM18PG121SN1D L222 VDDC12_XTAL P16 E8 GND_10 GND_194 Y20 VDD33_2 GND_31 BLM18PG121SN1D BLM18PG121SN1D GND_11 GND_195 Y21 F6 J5 VDD25_XTAL VDDC11_5 E22 GND_12 GND_196 VDD33_3 P26 P17 E23 Y22 GND_32 0.1uF 0.1uF GND_13 GND_197 Y23 XTAL_VDD VDDC11_6 E26 0.1uF F11 J6 GND_14 GND_198 C2414.7uF N26 P18 C2554.7uF F7 Y24 C2794.7uF VDD33_4 GND_33 XTAL_VDDP VDDC11_7 F8 GND_15 GND_199 Y25 G5 J8 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF GND_16 GND_200 R15 F22 Y26 H13 VDD33_5 GND_34 J9 +3.3V VDDC11_8 +1.2V_VDD F23 GND_17 GND_18 GND_201 GND_202 Y31 C2974.7uF M21 T15 C3514.7uF F24 Y35 VDD33_6 GND_35 VDD33_1 VDDC11_9 F25 GND_19 GND_203 AA8 J13 J10 VDD33 C218 C259 GND_20 GND_204 Y30 T22 C283 F26 AA12 VDD33_7 GND_36 VDD33_2 VDDC11_10 F27 GND_21 GND_205 AA13 P12 J11 AA30 T23 F31 GND_22 GND_206 AA14 VDD33_8 GND_37 VDD33_3 VDDC11_11 G7 GND_23 GND_207 AA16 C208 C209 C210 C213 C219 P13 J14 AE8 T24 G8 GND_24 GND_208 AA17 VDD33_9 GND_38 VDD33_4 VDDC11_12 G9 GND_25 GND_209 AA18 R5 K4 AF8 U15 G10 GND_26 GND_210 AA19 AVDD33_XTAL VDD33_10 GND_39 GND_27 GND_211 AA20 AVDD33_CVBS R6 K5 VDD33_5 VDDC11_13 G11 GND_28 GND_212 VDD33_11 AK13 U22 G12 AA21 GND_40 VDD33_6 VDDC11_14 G13 GND_29 GND_213 AA22 N16 K6 AK24 U23 G14 GND_30 GND_214 AA23 VDD33_XTAL GND_41 VDD33_7 VDDC11_15 G15 GND_31 GND_215 AA24 T13 K8 GND_32 GND_216 AVDD33_CVBS_1 GND_42 Place at the bottom side AK25 U24 G16 GND_33 GND_217 AA25 AA26 T14 K9 VDD33_8 VDDC11_16 G17 GND_34 GND_218 AVDD25 V15 G18 AA31 AVDD33_CVBS_2 GND_43 VDDC11_17 G19 GND_35 GND_219 AB6 K10 M22 V22 G20 GND_36 GND_220 AB8 GND_44 AVDD33_USB_1 VDDC11_18 G21 GND_37 GND_221 AB12 N10 N11 VDD25_CVBS_1 GND_45 K11 K13 +2.5V_Bypass Cap M23 AVDD33_USB_2 VDDC11_19 V23 G22 G23 GND_38 GND_39 GND_40 GND_222 GND_223 GND_224 AB13 AB16 VDD25_CVBS_2 +1.2V_VDD AK11 V24 G24 AB17 GND_46 AVDD33_BT_USB_1 VDDC11_20 G25 GND_41 GND_225 AB18 VDD25_REF N12 K14 AFE 3CH Power AK12 W22 G26 GND_42 GND_226 AB19 VDD25_VSB_1 GND_47 VDDC12_XTAL GND_43 GND_227 AB20 N13 L1 AVDD33_BT_USB_2 VDDC11_21 G27 GND_44 GND_228 VDD25_VSB_2 AF25 W23 G28 AB21 GND_48 L227 AVDD33_HDMI_1 VDDC11_22 G29 GND_45 GND_229 AB22 U5 L2 +2.5V_Normal AVDD25 VDD25_REF AF26 W24 G30 GND_46 GND_230 AB23 VDD25_REF GND_49 BLM18PG121SN1D GND_47 GND_231 AB25 AVDD33_HDMI_2 VDDC11_23 G31 0.1uF N7 L3 AB15 H9 GND_48 GND_232 AB26 VDD25_COMP_1 GND_50 L225 0.1uF GND_49 GND_233 C298 4.7uF H26 AB30 N8 L4 L220 VDDC11_24 GND_50 GND_234 VDD25_LTX VDD25_COMP_2 GND_51 BLM18PG121SN1D BLM15BD121SN1 +2.5V VDDC11_25 AB24 H27 H28 GND_51 GND_235 AB31 AC8 N9 L5 R31 AC15 H29 GND_52 GND_236 AC12 0.1uF VDD25_AUD VDD25_COMP_3 GND_52 GND_53 GND_237 0.1uF AC13 F14 L6 C222 4.7uF SP_VQPS VDDC11_26 H30 1uF GND_54 GND_238 VDD25_LVDS AC24 H31 AC16 C2424.7uF C2704.7uF C300 C2114.7uF VDD25_APLL GND_53 VDDC11_27 J7 GND_55 GND_239 AC17 M6 L8 C301 GND_56 GND_240 AE23 AD15 J30 AC18 VDD25_AUD_1 GND_54 VDD25_LVRX_1 VDDC11_28 J31 GND_57 GND_241 AC19 N6 L9 AF23 AD16 K7 GND_58 GND_242 AC20 VDD25_LTX C288 VDD25_AUD_2 GND_55 GND_59 GND_243 C224 AC21 M13 L10 VDD25_LVRX_2 VDDC11_29 K30 GND_60 GND_244 C274 L226 AE14 AD17 K31 AC22 VDD25_AAD GND_56 VTXPHY_VDD25_1 VDDC11_30 L30 GND_61 GND_245 AC23 F15 L11 BLM15BD121SN1 VDD25_XTAL AF14 AD18 L31 GND_62 GND_246 AC25 LTX_LVDD_1 GND_57 VTXPHY_VDD25_2 VDDC11_31 M7 GND_63 GND_247 AC30 F16 L13 N25 AD21 M12 GND_64 GND_248 AC31 LTX_LVDD_2 GND_58 VDD25_DR3PLL VDDC11_32 M13 GND_65 GND_249 AD8 H15 L14 VSS25_REF AD26 AD22 M14 GND_66 GND_250 AD12 SDRAM_VDDQ_1 GND_59 GPLL_AVDD25 VDDC11_33 M15 GND_67 GND_251 AD13 J15 L15 AD23 M16 GND_68 GND_252 AD19 SDRAM_VDDQ_2 GND_60 Bottom side of chip 1005 size bead VDDC11_34 M17 GND_69 GND_253 AD20 J16 L16 H10 AD24 M18 GND_70 GND_254 AD25 SDRAM_VDDQ_3 GND_61 Bottom side of chip +1.2V_VDD GND_71 GND_255 AD31 K15 L17 VDD15_M0_1 VDDC11_35 M19 GND_72 GND_256 VDD12_VTXPHY H11 M20 AE12 SDRAM_VDDQ_4 GND_62 VDD15_M0_2 M24 GND_73 GND_257 AE13 K16 L18 +1.5V H12 M25 GND_74 GND_258 AE15 VDD10_XTAL SDRAM_VDDQ_5 GND_63 L201 VDD15_M0_3 M26 GND_75 GND_259 AE16 M1 H13 M30 GND_76 GND_260 AE17 GND_64 BLM18PG121SN1D VDD12_VTXPHY GND_77 GND_261 AE18 R18 M2 VDD15_M0_4 M32 GND_78 GND_262 H14 M33 AE19 VDD10_XTAL 0.1uF 0.1uF GND_65 GND_79 GND_263 C205 4.7uF AE20 G7 M3 VDD15_M0_5 M34 GND_80 GND_264 H15 OPT VDDC10_1 +2.5V_Normal +2.5V_Normal VDDC15_M0 AB14 N12 AE21 GND_66 VDD25_LTX VDD25_AUD VDD15_M0_6 VTXPHY_VDD11_1 N13 GND_81 GND_265 AE22 G8 M4 H16 AC14 N14 GND_82 GND_266 AE24 VDDC10_2 GND_67 VDD15_M0_7 VTXPHY_VDD11_2 N15 GND_83 GND_267 AE25 VDDC10 G9 M5 H17 AD14 N16 GND_84 GND_268 AE26 VDDC10_3 GND_68 L207 L200 VDDC12_XTAL GND_85 GND_269 AE31 H7 M9 VDD15_M0_8 VTXPHY_VDD11_3 N17 C207 C206 BLM18PG121SN1D BLM18PG121SN1D H18 N18 GND_86 GND_270 AF12 VDDC10_4 GND_69 VDD15_M0_9 N19 GND_87 GND_271 AF13 H12 M10 GND_88 GND_272 0.1uF 0.1uF H19 P25 N20 AF15 VDDC10_5 GND_70 GND_89 GND_273 C2164.7uF 4.7uF AF16 VDD15_M0_10 AVDD11_DR3PLL N24 C2754.7uF C200 4.7uF J7 M11 H20 AA15 N30 GND_90 GND_274 AF17 VDDC10_6 GND_71 VDD15_M0_11 AVDD11_DCO N31 GND_91 GND_275 AF18 J12 M14 H21 AC26 +1.2V_VDD N32 GND_92 GND_276 AF19 VDDC10_7 GND_72 VDD15_M0_12 GPLL_VDD11 N33 GND_93 GND_277 AF20 K7 M15 H22 P7 GND_94 GND_278 AF21 VDDC10_8 GND_73 GND_95 GND_279 C223 C202 C204 P12 AF22 K12 M16 VDD15_M0_13 GND_96 GND_280 H23 P13 AF24 VDDC10_9 GND_74 VDD15_M0_14 P14 GND_97 GND_281 AF31 L7 N4 H24 P19 GND_98 GND_282 AG8 VDDC10_10 GND_75 VDD15_M0_15 P20 GND_99 GND_283 AG31 L12 N5 H25 P21 GND_100 GND_284 AH8 VDDC10_11 GND_76 VDD15_M0_16 P22 GND_101 GND_285 AH31 VDD10_XTAL M7 N14 P23 GND_102 GND_286 AJ8 VDDC10_12 GND_77 P24 GND_103 GND_287 AJ30 M12 N15 H7 P30 GND_104 GND_288 AK8 VDDC10_13 GND_78 VDD15_M1_1 P31 GND_105 GND_289 AK9 T17 N17 H8 R12 GND_106 GND_290 AK10 AVDD10_CVBS GND_79 VDD15_M1_2 R13 GND_107 GND_291 AK14 T18 P4 J8 R14 GND_108 GND_292 AK15 AVDD10_VSB GND_80 VDD15_M1_3 R16 GND_109 GND_293 AK16 M8 P5 K8 R17 GND_110 GND_294 AK17 AVDD10_LLPLL GND_81 VDD15_M1_4 R18 GND_111 GND_295 AK18 G10 P6 L7 R19 GND_112 GND_296 AK19 DVDD10_APLL_1 GND_82 VDD15_M1_5 R20 GND_113 GND_297 AK20 G11 P7 L8 R21 GND_114 GND_298 AK21 DVDD10_APLL_2 GND_83 VDD15_M1_6 R22 GND_115 GND_299 AK22 G12 P8 LTX_VDD GND_84 P9 +3.3V_Bypass Cap VDDC15_M1 M8 N7 VDD15_M1_7 R23 R24 R25 GND_116 GND_117 GND_118 GND_300 GND_301 GND_302 AK23 AK26 AK27 GND_85 VDD15_M1_8 R26 GND_119 GND_303 AK28 P10 +3.3V_NORMAL N8 R30 GND_120 GND_304 AK29 GND_86 VDD15_M1_9 R34 GND_121 GND_305 AK30 V5 P11 VDD33 P8 T7 GND_122 GND_306 AK31 VSS25_REF VSS25_REF GND_87 VDD15_M1_10 T12 GND_123 GND_307 AL8 C3 P14 R7 T13 GND_124 GND_308 AL12 GND_1 GND_88 L203 VDD15_M1_11 T14 GND_125 GND_309 AL13 D3 P15 R8 T16 GND_126 GND_310 AL14 GND_2 GND_89 BLM18PG121SN1D T17 GND_127 GND_311 AL15 D4 P16 VDD15_M1_12 GND_128 GND_312 T8 T18 AL16 GND_3 0.1uF 0.1uF 0.1uF GND_90 VDD15_M1_13 T19 GND_129 GND_313 AL17 D17 R4 U8 GND_130 GND_314 C2014.7uF T20 AL18 GND_4 GND_91 VDD15_M1_14 T21 GND_131 GND_315 AL19 E4 R7 V8 T25 GND_132 GND_316 AL20 GND_5 GND_92 F4 GND_6 GND_93 R8 +1.0V_Bypass Cap W8 VDD15_M1_15 VDD15_M1_16 T26 T30 T31 GND_133 GND_134 GND_135 GND_317 GND_318 GND_319 AL21 AL22 AL23 F7 R9 C203 C212 C215 GND_136 GND_320 T34 AL24 GND_7 GND_94 +1.0V_VDD VDD10_XTAL U7 GND_137 GND_321 AL25 F8 R10 U12 GND_138 GND_322 AL26 GND_8 GND_95 U13 GND_139 GND_323 AL27 F9 R11 U14 GND_140 GND_324 AL28 GND_9 GND_96 U16 GND_141 GND_325 AL29 F10 R12 L211 U17 GND_142 GND_326 AL30 GND_10 GND_97 BLM18PG121SN1D U18 GND_143 GND_327 AL31 F12 R13 U19 GND_144 GND_328 AM8 GND_11 GND_98 Place at the bottom side U20 GND_145 GND_329 AM13 0.1uF F13 R14 U21 GND_146 GND_330 AM14 GND_12 GND_99 GND_147 GND_331 C2394.7uF U25 AM15 F17 R15 U26 GND_148 GND_332 AM16 GND_13 GND_100 H13A_BRAZIL U30 GND_149 GND_333 AM17 F18 R16 U31 GND_150 GND_334 AM18 GND_14 GND_101 IC101-*1 V7 GND_151 GND_335 AM19 G4 R17 LG1154AN_H13A_ISDB-T (LG1154AN-IT) V12 GND_152 GND_336 AM20 C246 GND_15 GND_102 V13 GND_153 GND_337 AM21 G6 T4 V14 GND_154 GND_338 AM22 GND_16 GND_103 P17 H18 V16 GND_155 GND_339 AM23 G13 T7 P18 XIN_SUB AAD_ADC_SIF H17 V17 GND_156 GND_340 AM24 GND_17 GND_104 J17 XO_SUB AAD_ADC_SIFM V18 GND_157 GND_341 AM25 G14 T8 VSB_AUX_XIN P2 V19 GND_158 GND_342 AM26 GND_18 GND_105 N18 AUDA_VBG_EXT N1 V20 GND_159 GND_343 AM27 G15 T9 D18 XTAL_BYPASS AUDA_OUTL N2 V21 GND_160 GND_344 AM28 GND_19 GND_106 M18 CLK_24M AUDA_OUTR N3 V25 GND_161 GND_345 AM29 G16 T10 M17 XTAL_SEL0 AUD_SCART_OUTL P1 V26 GND_162 GND_346 AM30 GND_20 GND_107 XTAL_SEL1 AUD_SCART_OUTR V30 GND_163 GND_347 AM31 G17 T11 P3 V31 GND_164 GND_348 AN6 GND_21 GND_108 +1.0V_VDD AUAD_L_CH4_IN R1 W5 GND_165 GND_349 AN12 G18 H4 GND_22 GND_109 T12 T15 VDDC10 +2.5V_Bypass Cap E3 K3 PORES_N AUAD_R_CH4_IN AUAD_L_CH3_IN AUAD_R_CH3_IN R2 T1 U2 W6 W7 W12 GND_166 GND_167 GND_168 GND_350 GND_351 GND_352 AN13 AN15 AN16 GND_23 GND_110 +2.5V_Normal K2 OPM0 AUAD_L_CH2_IN U3 W13 GND_169 GND_353 AN17 H5 T16 L206 +2.5V_Normal OPM1 AUAD_R_CH2_IN GND_170 GND_354 GND_24 GND_111 BLM18PG121SN1D VDD25_XTAL (1) VDD25_LVDS(4) A8 AUAD_L_CH1_IN V2 V3 W14 W15 GND_171 GND_355 AN18 AN19 H6 U4 B8 H13A_SCL AUAD_R_CH1_IN U1 W16 GND_172 GND_356 AN20 GND_25 GND_112 H13A_SDA AUAD_R_REF T3 W17 GND_173 GND_357 AN21 0.1uF H8 U6 L234 L238 AUAD_M_REF T2 W18 GND_174 GND_358 AN22 C2144.7uF GND_26 GND_113 BLM18PG121SN1D BLM18PG121SN1D AUAD_L_REF R3 W19 GND_175 GND_359 AN23 H9 U18 U13 AUAD_REF_PO W20 GND_176 GND_360 AN24 GND_27 GND_114 V14 CVBS_IN3 K17 W21 GND_177 GND_361 AN25 0.1uF 0.1uF 0.1uF H10 V4 V15 CVBS_IN2 ANTCON K18 W25 GND_178 GND_362 AN26 C3644.7uF C3784.7uF GND_28 GND_115 V13 CVBS_IN1 RFAGC J18 W26 GND_179 GND_363 AN27 H11 V16 CVBS_VCM IFAGC GND_180 GND_364 C251 W30 AN28 GND_29 GND_116 U15 U16 W31 GND_181 GND_182 GND_365 GND_366 AN29 BUF_OUT1 ADC_I_INCOM U14 U17 Y3 AN30 BUF_OUT2 ADC_I_INP GND_183 GND_367 V17 Y4 AN31 ADC_I_INN GND_184 GND_368 C368 C381 C217 F3 GPIO0 U7 F2 REFT GPIO1 V6 F1 REFB GPIO2 V7 G3 ADC1_COM GPIO3 U10 G2 ADC2_COM GPIO4 V12 G1 ADC3_COM GPIO5 T5 H3 SC1_SID GPIO6 T6 H2 SC1_FB GPIO7 U8 H1 Place at the bottom side V8 PB1_IN Y1_IN GPIO8 GPIO9 J3 V9 E18 SOY1_IN GPIO10 U9 E17 PR1_IN GPIO11 V10 H16 PB2_IN GPIO12 U11 J2 Y2_IN GPIO13 V11 J1 SOY2_IN GPIO14 U12 K1 PR2_IN GPIO15 +1.5V_DDR VDDC15_M0 +1.5V_Bypass Cap VDDC15_M0 VDDC15_M0 +1.5V_DDR VDDC15_M1 VDDC15_M1 VDDC15_M1 GND JIG POINT VREF_M0_1 VREF_M1_0 VREF_M1_1 VREF_M0_0 R300 R302 1K 1% 1K 1% R200 R202 1K 1% 1K 1% L230 L228 JP203 JP204 JP202 JP205 BLM18PG121SN1D OPT OPT BLM18PG121SN1D OPT OPT 0.1uF C303 22uF C299 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1% 1% OPT OPT OPT OPT OPT OPT 1% 1% R301 R303 R203 R201 C307 C310 C304 1K 1K C302 C306 C308 C305 C309 C311 C312 C313 C314 C350 C352 C354 C356 C357 C358 C359 C361 C362 C365 C366 C367 C369 C370 C371 C372 C353 C355 C360 C363 C296 C344 1K 1K THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-003-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN POWER 11/05/31 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

IC101 IC100 LG1154AN_H13A H13A_NON_BRAZIL LG1154D_H13D OP MODE Setting INTR_GBB E1 AT16 INTR_GBB STPI0_CLK/GPIO47 AK35 FE_DEMOD2_TS_CLK +3.3V_NORMAL CLK_54M_VTT Clock for H13A & Select XTAL Input +3.3V_NORMAL INTR_AFE3CH E2 AU17 INTR_AFE3CH STPI0_SOP/GPIO46 AK36 FE_DEMOD2_TS_SYNC D1 AT17 AK37 INTR_AGPIO INTR_AGPIO STPI0_VAL/GPIO45 FE_DEMOD2_TS_VAL AJ35 10K 10K 10K 10K STPI0_ERR/GPIO44 FE_DEMOD2_TS_ERROR 1/16W A6 AT24 AJ36 R464 AUD_FS20CLK AUD_FS20CLK STPI0_DATA/GPIO43 FE_DEMOD2_TS_DATA B6 AU24 AH35 1K 1% MAIN Clock(24Mhz) X-TAL_1 OPT AUD_FS21CLK AUD_FS21CLK STPI1_CLK/GPIO42 D13_STPO_CLK A5 AT23 AH37 GND_1 R482 OPT R481 OPT R484 OPT 12pF AUD_FS23CLK AUD_FS23CLK STPI1_SOP/GPIO41 D13_STPO_SOP C404 XIN_SUB B5 AU23 AH36 1/16W D13_STPO_VAL R465 0.01uF C426 AUD_FS24CLK AUD_FS24CLK STPI1_VAL/GPIO40 390 OP MODE[0:1] : SW[2:1] A4 AT22 AG35 R483 50V 1% 2 00 => Normal Operaiton Mode AUD_FS25CLK AUD_FS25CLK STPI1_ERR/GPIO55 D13_STPO_ERR 1 C4 AG36 24MHz R441 D13_STPO_DATA X400 /T32 Debug Mode AUDCLK_OUT_SUB STPI1_DATA/GPIO54 1M 01 => Internal Test Purpose 10 => Internal Test Purpose 100 C18 AU36 AM36 R459 FE_DEMOD1_TS_CLK 3 4 DAC_START_PULLDOWN 11 => Internal Test Purpose OPM[0] AUD_HDMI_MCLK AUD_HDMI_MCLK TP_DVB_CLK 100 AL36 X-TAL_2 GND_2 R460 TP_DVB_SOP FE_DEMOD1_TS_SYNC 12pF OPM[1] A2 AT20 AL35 XTAL SEL[1:0] : SW[4:3] 1/16W XOUT_SUB 100 AUD_DAC1_LRCK AUD_DAC1_LRCK TP_DVB_VAL FE_DEMOD1_TS_VAL R466 00 => Xtal Input R461 XTAL_SEL[0] B2 AU20 AL37 C427 AUD_DAC1_SCK AUD_DAC1_SCK TP_DVB_ERR FE_DEMOD1_TS_ERROR 82 1% 01 => CLK 24M from H13D 100 B1 AT19 AM35 R462 XTAL_SEL[1] FE_DEMOD1_TS_DATA[0] FE_DEMOD1_TS_DATA[1-7] 10 => XTAL Bypass from H13D AUD_DAC1_LRCH AUD_DAC1_LRCH TP_DVB_DATA0 C2 AU19 AN36 FE_DEMOD1_TS_DATA[1] AUD_DAC0_LRCK AUD_DAC0_LRCK TP_DVB_DATA1 FOR EMI C1 AT18 AN37 FE_DEMOD1_TS_DATA[2] AUD_DAC0_SCK AUD_DAC0_SCK TP_DVB_DATA2 D2 AU18 AN35 FE_DEMOD1_TS_DATA[3] AUD_DAC0_LRCH AUD_DAC0_LRCH TP_DVB_DATA3 B4 AU22 AP37 FE_DEMOD1_TS_DATA[4] AUD_ADC_LRCK AUD_ADC_LRCK TP_DVB_DATA4 A3 AT21 AP36 Place JACK Side Place SOC Side IC101 H13A_NON_BRAZIL AUD_ADC_SCK B3 AU21 AUD_ADC_SCK TP_DVB_DATA5 AR37 FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[6] L408 1uH LG1154AN_H13A AUD_ADC_LRCH AUD_ADC_LRCH TP_DVB_DATA6 AR36 R434 FE_DEMOD1_TS_DATA[7] 100 C424 0.047uF TP_DVB_DATA7 AV1_CVBS_IN AV1_CVBS_IN_SOC A7 AT25 5.5V C405 BB_SCL BB_SCL C410 R410 B7 AU25 A28 D404 150pF 150pF 75 BB_SDA BB_SDA TPI_CLK TPI_CLK P17 H18 C450 0.1uF E8 AP23 B29 50V 1% XIN_SUB XIN_SUB AAD_ADC_SIF TU_SIF BB_TP_CLK BB_TPI_CLK TPI_SOP TPI_SOP TP402 TPI_ERR 3216 EU XOUT_SUB R453 330P18 H17 C451 0.1uF C457 D8 AR23 B28 TPI_VAL EU XO_SUB AAD_ADC_SIFM BB_TP_ERR BB_TPI_ERR TPI_VAL L409 1uH R433 J17 C452 10uF 1000pF C8 AP22 C28 100 C425 0.047uF SC_CVBS_IN_SOC VSB_AUX_XIN BB_TP_SOP BB_TPI_SOP TPI_ERR TPI_ERR TPI_DATA[0] TPI_DATA[0-7] SC_CVBS_IN P2 C453 2.2uF OPT E7 AR22 B32 C408 AUDA_VBG_EXT BB_TP_VAL BB_TPI_VAL TPI_DATA0 TPI_DATA[1] EU C462 N18 N1 D7 AP21 C31 150pF 150pF R411 XTAL_BYPASS AUDA_OUTL AUDA_OUTL BB_TP_DATA7 BB_TPI_DATA7 TPI_DATA1 EU D18 N2 C7 AR21 B31 TPI_DATA[2] 50V EU 75 SC_CVBS_IN_SOY AUDA_OUTR 1% CLK_24M AUDA_OUTR BB_TP_DATA6 BB_TPI_DATA6 TPI_DATA2 TPI_DATA[3] EU M18 N3 E6 AP20 A31 3216 XTAL_SEL[0] XTAL_SEL0 AUD_SCART_OUTL SCART_Lout_SOC BB_TP_DATA5 BB_TPI_DATA5 TPI_DATA3 R432 M17 P1 EU 100 R479 D6 AR20 C30 TPI_DATA[4] 100 C423 0.047uF XTAL_SEL[1] XTAL_SEL1 AUD_SCART_OUTR SCART_Rout_SOC BB_TP_DATA4 BB_TPI_DATA4 TPI_DATA4 TU_CVBS TU_CVBS_SOC EU 100 R480 C6 AP19 A30 TPI_DATA[5] 0.01uF 0.01uF C402 BB_TP_DATA3 BB_TPI_DATA3 TPI_DATA5 P3 E5 AR19 B30 TPI_DATA[6] 150pF AUAD_L_CH4_IN BB_TP_DATA2 BB_TPI_DATA2 TPI_DATA6 EU R426 EU R442 50V R1 D5 AP18 C29 TPI_DATA[7] 22K 22K OPT AUAD_R_CH4_IN BB_TP_DATA1 BB_TPI_DATA1 TPI_DATA7 E3 R2 C5 CLK_54M_VTT AR18 SOC_RESET PORES_N AUAD_L_CH3_IN AUAD_L_CH3_IN BB_TP_DATA0 BB_TPI_DATA0 T1 R467 82 D30 TPO_CLK C458 TPO_ERR C460 EU EU SCART_FB_DIRECT AUAD_R_CH3_IN AUAD_R_CH3_IN TPIO_CLK/GPIO53 TP400 C415 K3 U2 B10 1/16W 1% AU28 D31 TPO_SOP R423 100 OPM[0] OPM0 AUAD_L_CH2_IN AUAD_L_CH2_IN CLK_F54M CLK_54M TPIO_SOP/GPIO52 SC_FB SC_FB_SOC 0.1uF K2 U3 C9 AR24 F30 TPO_VAL OPM[1] OPM1 AUAD_R_CH2_IN AUAD_R_CH2_IN CVBS_GC2 CVBS_GC2 TPIO_VAL/GPIO51 10K EU V2 B9 AU27 E31 TPO_ERR R435 AUAD_L_CH1_IN CVBS_GC1 CVBS_GC1 TPIO_ERR/GPIO50 TPO_DATA[0-7] SC_ID SC_ID_SOC A8 V3 A9 AT27 E30 TPO_DATA[0] H13A_SCL H13A_SCL AUAD_R_CH1_IN CVBS_GC0 CVBS_GC0 TPIO_DATA0/GPIO58 B8 U1 D9 AP24 F29 TPO_DATA[1] SCART_FB_DIRECT EU H13A_SDA H13A_SDA AUAD_R_REF AUAD_R_REF CVBS_UP CVBS_UP TPIO_DATA1/GPIO59 R422 NON_EU T3 E9 AR25 E29 TPO_DATA[2] NON_EU R436 R436-*1 AUAD_M_REF AUAD_M_REF CVBS_DN CVBS_DN TPIO_DATA2/GPIO60 R422-*1 75 2.7K T2 F28 TPO_DATA[3] 0 0 AUAD_L_REF AUAD_L_REF Close to LG1154A TPIO_DATA3/GPIO61 R3 Close to IC4300 B11 R492 330 AU29 E28 TPO_DATA[4] AUAD_REF_PO AUAD_REF_PO FS00CLK FS00CLK TPIO_DATA4/GPIO62 U13 A11 R407 330 AT29 D28 TPO_DATA[5] AV1_CVBS_IN_SOC CVBS_IN3 AUDCLK_OUT H13A_AUDCLK_OUT TPIO_DATA5/GPIO63 V14 K17 DAC_START_PULLDOWN E27 TPO_DATA[6] SC_CVBS_IN_SOC CVBS_IN2 ANTCON NON_TU_W_BR/TW/CO TPIO_DATA6/GPIO48 V15 K18 D11 AP27 D27 TPO_DATA[7] TU_CVBS_SOC CVBS_IN1 RFAGC R487 DAC_START DAC_START TPIO_DATA7/GPIO49 C443 0.047uF V13 J18 C11 AR27 I2S_I/F R400 EU 33 C417 EU 0.047uF CVBS_VCM IFAGC IF_AGC DAC_DATA4 DAC_DATA4 SC_B COMP1_PB_IN_SOC R450 68 0 E10 AP26 AD5 R495 100 R405 EU 33 C418 EU 0.047uF DTV/MNT_V_OUT_SOC C459 DAC_DATA3 DAC_DATA3 AUDCLK_OUT AUD_MASTER_CLK SC_G COMP1_Y_IN_SOC U15 U16 D10 AR26 AD6 R496 100 C428 EU 1000pF C454 0.1uF 0.1uF AUD_LRCH To front, woofer, COMP1_Y_IN_SOC_SOY BUF_OUT1 ADC_I_INCOM DAC_DATA2 DAC_DATA2 DACLRCH SC_CVBS_IN_SOY U14 U17 TU_W_BR/TW/CO C10 AP25 Y6 R452 100 R427 EU 33 C419 EU 0.047uF C439 BUF_OUT2 ADC_I_INP ADC_I_INP DAC_DATA1 DAC_DATA1 DACSLRCH/GPIO127 AUD_LRCH1 center amp FOR UB98/UB9 SC_R COMP1_PR_IN_SOC OPT 100pF V17 A10 R451 AT28 Y7 330 OPT 50V 10pF OPT 50V 10pF C472 C473 OPT 50V 10pF R414 1% 75 To height amp FOR UB98/UB9 R416 1% 75 EU ADC_I_INN 1% 75 C474 50V ADC_I_INN DAC_DATA0 DAC_DATA0 PCMI3SCK/GPIO112 AC6 R497 100 EU DACSCK AUD_SCK Placed as close as possible to SOC F3 D13 AR30 AC5 R498 100 EU GPIO0 BIT0 AAD_GC4 AAD_GC4 DACLRCK AUD_LRCK U7 F2 C13 AP29 AA6 C411 R412 REFT REFT GPIO1 BIT1 TU_W_BR/TW/CO AAD_GC3 AAD_GC3 PCMI3LRCK/GPIO113 10pF V6 F1 R487-*1 E12 AR29 AB7 50V REFB REFB GPIO2 BIT2 AAD_GC2 AAD_GC2 PCMI3LRCH R447 68 C440 0.047uF V7 G3 D12 AP28 AB5 OPT ADC1_COM GPIO3 BIT3 10K AAD_GC1 AAD_GC1 DACCLFCH/GPIO126 URSA_RESET_SoC R448 68 C441 0.047uF U10 G2 C12 AR28 AU14 R424 C420 0.047uF ADC2_COM GPIO4 BIT4 AAD_GC0 AAD_GC0 IEC958OUT SPDIF_OUT COMP1_Pb 33 COMP2_PB_IN_SOC R449 68 C442 0.047uF V12 G1 AA32 R425 C421 0.047uF ADC3_COM GPIO5 BIT5 DACSUBMCLK COMP1_Y 33 COMP2_Y_IN_SOC T5 H3 C17 AP35 AA34 C429 1000pF SC_ID_SOC SC1_SID GPIO6 BIT6 AAD_DATA9 AAD_DATA9 DACSUBLRCH COMP2_Y_IN_SOC_SOY T6 H2 E16 AR35 AA33 AR403 BIT7 COMP1_Pr 33 C422 0.047uF COMP2_PR_IN_SOC SC_FB_SOC U8 SC1_FB GPIO7 H1 AAD_DATA8 D16 AP34 AAD_DATA8 DACSUBSCK AB34 33 D403 D406 1/16W D401 BIT8 50V 10pF 50V 10pF R415 1% 75 R417 1% 75 R431 COMP1_PB_IN_SOC R413 1% 75 C430 C431 50V 10pF PB1_IN GPIO8 AAD_DATA7 AAD_DATA7 DACSUBLRCK C470 V8 J3 C16 AR34 AE32 +3.3V_NORMAL COMP1_Y_IN_SOC Y1_IN GPIO9 BIT9 AAD_DATA6 AAD_DATA6 TEST1 V9 E18 E15 AP33 AE33 5.5V 5.5V 5.5V COMP1_Y_IN_SOC_SOY SOY1_IN GPIO10 BIT10 AAD_DATA5 AAD_DATA5 TEST2 U9 E17 D15 AR33 COMP1_PR_IN_SOC PR1_IN GPIO11 AAD_DATA4 AAD_DATA4 V10 H16 C15 AP32 AT6 COMP2_PB_IN_SOC PB2_IN GPIO12 AAD_DATA3 AAD_DATA3 TX0N TXB0P/TX5P U11 J2 E14 AR32 AU6 COMP2_Y_IN_SOC Y2_IN GPIO13 AAD_DATA2 AAD_DATA2 TX0P TXB0N/TX5N V11 J1 D14 AP31 AT5 COMP2_Y_IN_SOC_SOY SOY2_IN GPIO14 AAD_DATA1 AAD_DATA1 TX1N TXB1P/TX4P U12 K1 C14 AR31 AU5 Near Place Scart AMP COMP2_PR_IN_SOC PR2_IN GPIO15 SC_FB_BUF AAD_DATA0 AAD_DATA0 TX1P TXB1N/TX4N E13 AP30 AT4 EU EU AAD_DATAEN AAD_DATAEN TX2N TXB2P/TX3P AU4 SCART_AMP_R_FB TX2P TXB2N/TX3N 10K B18 AT36 AU3 4.7uF 10V ADCO_OUT_CLK ADCO_OUT_CLK TX3N TXBCLKP/TX2P C6006 R6006 AU2 TX3P TXBCLKN/TX2N A12 AT30 AT2 EU EU +2.5V_Normal HSR_AP0 B12 AU30 HSR_AP TX4N AT1 TXB3P/TX1P SCART_AMP_L_FB HSR_AM0 HSR_AM TX4P TXB3N/TX1N Placed as close as possible to IC4300 A13 AT31 AR4 4.7uF 10V 10K HSR_BP0 HSR_BP TX5N TXB4P/TX0P C6001 R6005 +3.3V_NORMAL B13 AU31 AR3 HSR_BM0 HSR_BM TX5P TXB4N/TX0N A14 AT32 AP1 AUDIO IN L407 HSR_CP0 HSR_CM0 B14 AU32 HSR_CP HSR_CM TX6N TX6P AP2 TXA0P/TX11P TXA0N/TX11N AUAD_REF_PO A15 AT33 AP4 OPT HSR_CLKP0 HSR_CLKP TX7N TXA1P/TX10P 1% C447 1% C455 B15 AU33 AP3 IC400 TXA1N/TX10N R418 EU 27K C432 EU 4.7uF NJM2561BF1 1uF R455 10uF HSR_CLKM0 A16 AT34 HSR_CLKM TX7P AN4 SC_L_IN AUAD_L_CH3_IN 25V 51K TXA2P/TX9P AUAD_L_REF HSR_DP0 HSR_DP TX8N 1% B16 AU34 AN3 R437 EU 10K 1% HSR_DM0 HSR_DM TX8P TXA2N/TX9N R457 A17 AT35 AM4 4.7uF C449 1% POWER_SAVE V+ 51K HSR_EP0 HSR_EP TX9N TXACLKP/TX8P 47K R456 1% 1 6 B17 AU35 AM3 R419 EU 27K C433 EU 4.7uF EU TXACLKN/TX8N SC_R_IN AUAD_R_CH3_IN C412 HSR_EM0 HSR_EM TX9P AL4 0.1uF TX10N TXA3P/TX7P R438 EU 10K 1% VOUT GND AT14 AL3 0.1uF 2 EU 5 C414 AUD_HPDRV_LRCH TX10P TXA3N/TX7N AT15 AK1 DTV/MNT_V_OUT AUD_HPDRV_LRCK TX11N TXA4P/TX6P NC AU15 AK2 EU VSAG VIN AUD_HPDRV_SCK TX11P TXA4N/TX6N 3 4 AK4 TX12N TXD0P/TX17P DTV/MNT_V_OUT_SOC AC7 AK3 AUAD_R_REF FRC_LR_O_SYNC_FLAG TX12P TXD0N/TX17N R402 33 AN5 1% L/DIM0_VS L_VSOUT_LD COMP1/AV1/DVI_L_IN AUAD_M_REF AR14 AJ4 R420 27K C434 4.7uF L/DIM0_SCLK TXD1P/TX16P AUAD_L_CH2_IN AR404 DIM0_SCLK TX13N AP14 AJ3 1/10W L/DIM0_MOSI TXD1N/TX16N DIM0_MOSI TX13P R454 33 OPT R439 10K 1% 1% C456 AN14 AH4 1% R458 TXD2P/TX15P 5% COMP1/AV1/DVI_R_IN 4.7uF DIM1_SCLK TX14N AP13 2 R421 27K C435 4.7uF 47K AH3 AUAD_R_CH2_IN 10V DIM1_MOSI TX14P TXD2N/TX15N C448 OPT L/DIM0_VS AG4 4.7uF L/DIM0_SCLK TX15N TXDCLKP/TX14P R440 10K 1% AF6 AG3 10V PWM0 TX15P TXDCLKN/TX14N L/DIM0_MOSI PWM1 AF7 AF1 PWM1 TX16N TXD3P/TX13P TU_W_BR/TW TU_W_BR/TW TU_W_BR/TW BPL_IN AD7 AF2 PWM2 R443-*1 R444-*1 C436-*1 PWM2 TX16P TXD3N/TX13N AE6 AF4 100pF BPL_IN PWM_IN TX17N TXD4P/TX12P 220 220 AF3 NON_TU_W_BR/TW TX17P TXD4N/TX12N +12V AP5 AE4 R443 C437 EPI_EO TX18N TXC0P/TX23P AN8 AE3 ADC_I_INN IF_N EPI_VST TX18P TXC0N/TX23N 51 0.01uF AP8 AD4 NON_TU_W_BR/TW EPI_DPM TX19N TXC1P/TX22P AR7 AD3 AFE 3CH REF Setting 100K R403 100K R408 EU EU C436 L406 EPI_MCLK TX19P TXC1N/TX22N To ADC 22pF OPT AN7 AC4 TXC2P/TX21P EPI_GCLK TX20N SCART_FB_BUFFER SCART_Lout EU NON_TU_W_BR/TW AC3 +3.3V_NORMAL R444 C438 TX20P TXC2N/TX21N SCART_Lout_SOC AB1 C403 ADC_I_INP IF_P TX21N TXCCLKP/TX20P 51 0.01uF Placed as close as possible to IC4300 AB2 SCART_Rout 2.2uF EU TX21P TXCCLKN/TX20N 10V AB4 R446 4.7K C444 TX22N TXC3P/TX19P C406 SCART_Rout_SOC Tuner IF Filter Placed as close as possible to IC100 REFT AB3 TX22P TXC3N/TX19N 100K R404 AA4 100K R409 EU 0.1uF EU 2.2uF SC_FB_BUF TXC4P/TX18P 10V TX23N C446 AA3 SCART_FB_BUFFER C Must be used TX23P TXC4N/TX18N 0.1uF SC_FB R401 HP_OUT HP_OUT 470 B L400 C445 AR5 R6450 MMBT3904(NXP) L401 BLM18PG121SN1D BLM18PG121SN1D REFB TX_LOCKN HP_LOUT_MAIN 100 1/16W Q400 HP_ROUT 0.1uF AUDA_OUTL 5% E SCART_FB_BUFFER HP_LOUT 1K R406 SCART_FB_BUFFER HP_LOUT_AMP HP_OUT HP_ROUT_AMP HP_OUT R430 1/16W C400 C409 22K OPT C407 Not Used Net (UB85/95/UC89) 0.01uF 0.22uF 0.22uF 1% OPT 10V 10V AUD_LRCH1 HP_ROUT_MAIN R6451 DIMMING NON_OLED 100 AUDA_OUTR Place at JACK SIDE AR402 33 LG1154A LG1154D R445 C401 1/16W 22K OPT 0.01uF PWM2 PWM_DIM OPT PWM_DIM2 PWM1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-004-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR MAIN AUDIO/VIDEO THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

DDR_VTT IC100 LG1154D_H13D DDR_HYNIX DDR_HYNIX DDR_HYNIX DDR_HYNIX IC500 IC502 M0_1_DDR_VREFCA IC504 M0_DDR_VREFCA_T AR7 AR8 AR9 AR10 AR11 AR12 F15 M0_DDR_A0 H5TQ4G83AFR-PBC M0_DDR_VREFCA H5TQ4G83AFR-PBC H5TQ4G83AFR-PBC 56 56 56 56 56 56 R3104 56 IC505 M0_1_DDR_VREFCA_T M0_DDR_A[0] F13 M0_DDR_A1 M0_DDR_VREFDQ_T H5TQ4G83AFR-PBC M0_DDR_A[1] M0_1_DDR_VREFDQ F17 M0_DDR_VREFDQ M0_DDR_A[2] F19 M0_DDR_A2 DDR3 DDR3 DDR3 M0_1_DDR_VREFDQ_T K3 J8 K3 J8 M0_DDR_A[3] E10 M0_DDR_A3 M0_DDR_A0 K3 A0 4Gbit VREFCA J8 M0_DDR_A0 A0 4Gbit VREFCA M0_DDR_A0 A0 4Gbit VREFCA DDR3 M0_DDR_A4 L7 L7 L7 K3 J8 M0_DDR_A[4] M0_DDR_A1 A1 M0_DDR_A1 A1 M0_DDR_A0 E18 M0_DDR_A5 M0_DDR_A1 L3 A1 L3 L3 L7 A0 4Gbit VREFCA M0_DDR_A[5] M0_DDR_A2 A2 M0_DDR_A2 A2 M0_DDR_A1 A1 E11 M0_DDR_A2 A2 K2 E1 K2 E1 L3 M0_DDR_A[6] M0_DDR_A6 K2 E1 M0_DDR_A3 M0_DDR_A3 M0_DDR_A2 F18 M0_DDR_A3 A3 VREFDQ A3 VREFDQ A3 VREFDQ A2 M0_DDR_A7 L8 L8 L8 K2 E1 M0_DDR_A[7] M0_DDR_A4 A4 M0_DDR_A4 A4 M0_DDR_A3 A3 VREFDQ F11 M0_DDR_A4 A4 L2 L2 L8 M0_DDR_A[8] M0_DDR_A8 L2 M0_DDR_A5 VDDC15_M0 M0_DDR_A5 VDDC15_M0 M0_DDR_A4 F16 M0_DDR_A5 A5 R558 VDDC15_M0 A5 R560 A5 R559 A4 M0_DDR_A9 M8 H8 M8 H8 M8 H8 L2 M0_DDR_A[9] M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ M0_DDR_A5 A5 R561 VDDC15_M0 E9 M0_DDR_A6 A6 ZQ M2 M2 M8 H8 M0_DDR_A[10] M0_DDR_A10 M2 240 240 240 E12 M0_DDR_A7 M0_DDR_A7 A7 1% M0_DDR_A7 A7 1% M0_DDR_A6 A6 ZQ A7 1% N8 N8 M2 240 M0_DDR_A[11] M0_DDR_A11 N8 M0_DDR_A8 M0_DDR_A8 M0_DDR_A7 E13 M0_DDR_A8 A8 A8 A8 A7 1% M0_DDR_A12 M3 A2 M3 A2 M3 A2 N8 M0_DDR_A[12] M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1 M0_DDR_A8 A8 E16 M0_DDR_A9 A9 VDD_1 H7 A9 H7 A9 M3 A2 M0_DDR_A[13] M0_DDR_A13 H7 A9 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A9 F12 M0_DDR_A10 A10/AP VDD_2 A9 VDD_1 M0_DDR_A14 M7 D7 M7 D7 M7 D7 H7 A9 M0_DDR_A[14] M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 M0_DDR_A10 A10/AP VDD_2 F14 M0_DDR_A11 A11 VDD_3 K7 G2 K7 G2 M7 D7 M0_DDR_A[15] M0_DDR_A15 K7 G2 M0_DDR_A12 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A11 A11 VDD_3 A12/BC VDD_4 N3 G8 N3 G8 K7 G2 N3 G8 M0_DDR_A13 M0_DDR_A13 M0_DDR_A12 E19 M0_DDR_A13 A13 VDD_5 A13 VDD_5 A13 VDD_5 A12/BC VDD_4 M0_DDR_BA[0] M0_DDR_BA0 N7 K1 N7 K1 N7 K1 N3 G8 F10 M0_DDR_A14 M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 M0_DDR_A13 A13 VDD_5 A14 VDD_6 J7 K9 J7 K9 N7 K1 M0_DDR_BA[1] M0_DDR_BA1 J7 K9 M0_DDR_A15 M0_DDR_A15 M0_DDR_A14 E15 M0_DDR_A15 A15 VDD_7 A15 VDD_7 A15 VDD_7 A14 VDD_6 M0_DDR_BA[2] M0_DDR_BA2 M1 M1 M1 J7 K9 VDD_8 VDD_8 M0_DDR_A15 A15 VDD_7 VDD_8 J2 M9 J2 M9 M1 J2 M9 M0_DDR_BA0 M0_DDR_BA0 B10 M0_DDR_BA0 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 VDD_8 M0_U_CLK K8 K8 K8 J2 M9 M0_DDR_U_CLK M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_BA0 BA0 VDD_9 A10 M0_DDR_BA1 BA1 J3 J3 K8 M0_DDR_U_CLKN M0_U_CLKN J3 M0_DDR_BA2 M0_DDR_BA2 M0_DDR_BA1 A19 M0_DDR_BA2 BA2 BA2 BA2 BA1 M0_DDR_D_CLK M0_D_CLK B9 B9 B9 J3 B19 VDDQ_1 VDDQ_1 M0_DDR_BA2 BA2 VDDQ_1 F7 C1 F7 C1 B9 M0_DDR_D_CLKN M0_D_CLKN F7 C1 M0_D_CLK M0_U_CLK E14 M0_D_CLK CK VDDQ_2 CK VDDQ_2 CK VDDQ_2 VDDQ_1 M0_DDR_CKE G7 E2 0.1uF G7 E2 C583 0.1uF G7 E2 C568 0.1uF F7 C1 M0_DDR_CKE C559 M0_D_CLKN CK VDDQ_3 M0_U_CLKN CK VDDQ_3 M0_U_CLK CK VDDQ_2 M0_D_CLKN CK VDDQ_3 G9 E9 0.1uF G9 E9 0.1uF G7 E2 0.1uF G9 E9 C560 0.1uF C574 C569 C572 F21 M0_DDR_CKE M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 M0_U_CLKN CK VDDQ_3 CKE VDDQ_4 G9 E9 C577 0.1uF M0_DDR_ODT M0_DDR_ODT M0_DDR_CKE E21 CKE VDDQ_4 M0_DDR_RASN H2 H2 H2 M0_DDR_RASN CS CS E20 CS G1 G1 H2 M0_DDR_CASN M0_DDR_CASN G1 M0_DDR_ODT ODT M0_DDR_ODT ODT F20 M0_DDR_ODT ODT CS M0_DDR_WEN F3 F3 F3 G1 M0_DDR_WEN M0_DDR_RASN RAS M0_DDR_RASN RAS M0_DDR_ODT ODT M0_DDR_RASN RAS G3 G3 F3 G3 M0_DDR_CASN M0_DDR_CASN M0_DDR_RASN E17 M0_DDR_CASN CAS CAS CAS RAS M0_DDR_RESET_N H3 H3 H3 G3 M0_DDR_RESET_N M0_DDR_WEN WE M0_DDR_WEN WE M0_DDR_CASN CAS M0_DDR_WEN WE H3 F9 R500 M0_DDR_WEN WE 240 N2 N2 M0_DDR_ZQCAL N2 M0_DDR_RESET_N RESET M0_DDR_RESET_N RESET 1% M0_DDR_RESET_N RESET N2 B20 M0_DDR_RESET_N RESET M0_DDR_DQS[0] M0_DDR_DQS0 A20 C3 C3 M0_DDR_DQS_N[0] M0_DDR_DQS_N0 C3 M0_DDR_DQS1 M0_DDR_DQS2 C19 M0_DDR_DQS0 DQS DQS DQS M0_DDR_DQS1 D3 D3 D3 C3 M0_DDR_DQS[1] M0_DDR_DQS_N1 DQS M0_DDR_DQS_N2 DQS M0_DDR_DQS3 DQS D19 M0_DDR_DQS_N0 DQS D3 M0_DDR_DQS_N[1] M0_DDR_DQS_N1 M0_DDR_DQS_N3 A11 DQS M0_DDR_DQS2 B7 A1 B7 A1 B7 A1 M0_DDR_DQS[2] M0_DDR_DM1 DM/TDQS VSS_1 M0_DDR_DM2 DM/TDQS VSS_1 B11 M0_DDR_DM0 DM/TDQS VSS_1 A7 A8 A7 A8 B7 A1 M0_DDR_DQS_N[2] M0_DDR_DQS_N2 A7 A8 M0_DDR_DM3 C10 NF/TDQS VSS_2 NF/TDQS VSS_2 NF/TDQS VSS_2 DM/TDQS VSS_1 M0_DDR_DQS[3] M0_DDR_DQS3 B1 B1 B1 A7 A8 DDR_SAMSUNG IC505-*1 D10 VSS_3 VSS_3 DDR_SAMSUNG VSS_3 NF/TDQS VSS_2 K4B4G0846D-BCK0 M0_DDR_DQS_N[3] M0_DDR_DQS_N3 D8 D8 IC502-*1 K4B4G0846D-BCK0 D8 DDR_SAMSUNG IC504-*1 B1 VSS_4 DDR_SAMSUNG VSS_4 VSS_4 K4B4G0846D-BCK0 VSS_3 K3 A0 VREFCA J8 F2 IC500-*1 K4B4G0846D-BCK0 F2 K3 J8 F2 D8 L7 L3 A1 A2 D18 VSS_5 VSS_5 L7 A0 A1 VREFCA VSS_5 K3 A0 VREFCA J8 VSS_4 K2 L8 A3 VREFDQ E1 M0_DDR_DM[0] M0_DDR_DM0 F8 K3 J8 F8 L3 K2 A2 A3 VREFDQ E1 F8 L7 L3 A1 A2 F2 L2 M8 A4 A5 H8 C20 VSS_6 L7 A0 A1 VREFCA VSS_6 L8 L2 A4 VSS_6 K2 L8 A3 VREFDQ E1 VSS_5 M2 A6 A7 ZQ M0_DDR_DM1 B3 J1 L3 A2 B3 J1 M8 A5 H8 B3 J1 L2 A4 F8 N8 A8 M0_DDR_DM[1] K2 L8 A3 VREFDQ E1 M0_DDR_DQ8 DQ0 VSS_7 M2 A6 A7 ZQ M0_DDR_DQ16 DQ0 VSS_7 M8 A5 A6 ZQ H8 VSS_6 M3 H7 A9 VDD_1 A2 A9 D9 M0_DDR_DQ0 DQ0 VSS_7 L2 A4 A5 C7 J9 N8 M3 A8 A2 C7 J9 M2 N8 A7 B3 J1 M7 A10/AP A11 VDD_2 VDD_3 D7 M0_DDR_DM[2] M0_DDR_DM2 C7 J9 M8 M2 A6 ZQ H8 M0_DDR_DQ9 DQ1 H7 A9 VDD_1 A9 M0_DDR_DQ17 DQ1 M3 A8 A2 M0_DDR_DQ24 K7 A12/BC VDD_4 G2 C11 M0_DDR_DQ1 DQ1 VSS_8 N8 A7 VSS_8 M7 A10/AP A11 VDD_2 VDD_3 D7 VSS_8 H7 A9 A10/AP VDD_1 VDD_2 A9 DQ0 VSS_7 N3 N7 A13 VDD_5 G8 K1 M0_DDR_DM3 C2 L1 M3 A8 A2 C2 L1 K7 A12/BC VDD_4 G2 C2 L1 M7 K7 A11 VDD_3 D7 G2 C7 J9 A14 VDD_6 K9 M0_DDR_DM[3] H7 A9 A10/AP VDD_1 VDD_2 A9 M0_DDR_DQ10 DQ2 VSS_9 N3 N7 A13 VDD_5 G8 K1 M0_DDR_DQ18 DQ2 VSS_9 N3 A12/BC VDD_4 G8 M0_DDR_DQ25 DQ1 VSS_8 VDD_7 VDD_8 M1 M0_DDR_DQ2 DQ2 VSS_9 M7 K7 A11 A12/BC VDD_3 VDD_4 D7 G2 C8 L9 A14 VDD_6 VDD_7 K9 C8 L9 N7 A13 A14 VDD_5 VDD_6 K1 K9 C2 L1 J2 K8 BA0 VDD_9 M9 C8 L9 N3 A13 VDD_5 G8 M0_DDR_DQ11 DQ3 J2 VDD_8 M1 M9 M0_DDR_DQ19 DQ3 VDD_7 M1 M0_DDR_DQ26 J3 BA1 D22 M0_DDR_DQ3 DQ3 VSS_10 N7 A14 VDD_6 K1 K9 VSS_10 K8 BA0 VDD_9 VSS_10 J2 BA0 VDD_8 VDD_9 M9 DQ2 VSS_9 BA2 VDDQ_1 B9 M0_DDR_DQ0 E3 N1 VDD_7 M1 E3 N1 J3 BA1 E3 N1 K8 BA1 C8 L9 F7 G7 CK VDDQ_2 C1 E2 M0_DDR_DQ[0] J2 BA0 VDD_8 VDD_9 M9 M0_DDR_DQ12 DQ4 VSS_11 BA2 VDDQ_1 B9 M0_DDR_DQ20 DQ4 VSS_11 J3 BA2 B9 M0_DDR_DQ27 DQ3 VSS_10 G9 CK VDDQ_3 E9 C15 M0_DDR_DQ4 DQ4 VSS_11 K8 J3 BA1 E8 N9 F7 G7 CK VDDQ_2 C1 E2 E8 N9 F7 CK VDDQ_1 VDDQ_2 C1 E3 N1 CKE VDDQ_4 M0_DDR_DQ[1] M0_DDR_DQ1 E8 N9 BA2 B9 M0_DDR_DQ13 G9 CK CKE VDDQ_3 VDDQ_4 E9 M0_DDR_DQ21 G7 CK VDDQ_3 E2 M0_DDR_DQ28 H2 G1 CS C23 M0_DDR_DQ5 DQ5 VSS_12 F7 CK VDDQ_1 VDDQ_2 C1 DQ5 VSS_12 H2 DQ5 VSS_12 G9 CKE VDDQ_4 E9 DQ4 VSS_11 F3 ODT RAS M0_DDR_DQ2 D2 G7 CK VDDQ_3 E2 D2 G1 CS D2 H2 E8 N9 G3 CAS M0_DDR_DQ[2] G9 CKE VDDQ_4 E9 M0_DDR_DQ14 DQ6 F3 ODT RAS M0_DDR_DQ22 DQ6 G1 CS ODT M0_DDR_DQ29 DQ5 VSS_12 H3 WE D16 M0_DDR_DQ6 DQ6 H2 CS E7 G3 H3 CAS E7 F3 G3 RAS D2 N2 RESET M0_DDR_DQ[3] M0_DDR_DQ3 E7 G1 F3 ODT M0_DDR_DQ15 WE M0_DDR_DQ23 H3 CAS M0_DDR_DQ30 B24 M0_DDR_DQ7 DQ7 G3 RAS DQ7 N2 RESET DQ7 WE DQ6 C3 M0_DDR_DQ[4] M0_DDR_DQ4 B2 H3 CAS WE B2 B2 N2 RESET E7 D3 DQS DQS B15 VSSQ_1 N2 RESET VSSQ_1 C3 D3 DQS VSSQ_1 C3 M0_DDR_DQ31 DQ7 B7 DM/TDQS VSS_1 A1 M0_DDR_DQ5 A3 B8 A3 B8 DQS A3 B8 D3 DQS B2 A7 NU/TDQS VSS_2 A8 M0_DDR_DQ[5] C3 NC_1 VSSQ_2 B7 DM/TDQS VSS_1 A1 NC_1 VSSQ_2 DQS VSSQ_1 VSS_3 B1 D8 D23 NC_1 VSSQ_2 D3 DQS DQS F1 C9 A7 NU/TDQS VSS_2 A8 B1 F1 C9 B7 A7 DM/TDQS VSS_1 A1 A8 A3 B8 VSS_4 VSS_5 F2 M0_DDR_DQ[6] M0_DDR_DQ6 F1 C9 B7 A1 VSS_3 D8 NU/TDQS VSS_2 B1 VSS_6 F8 A15 NC_2 VSSQ_3 A7 DM/TDQS VSS_1 A8 NC_2 VSSQ_3 VSS_4 VSS_5 F2 NC_2 VSSQ_3 VSS_3 VSS_4 D8 NC_1 VSSQ_2 B3 C7 DQ0 VSS_7 J1 J9 M0_DDR_DQ7 F9 D1 NU/TDQS VSS_2 B1 F9 D1 VSS_6 F8 F9 D1 VSS_5 F2 F8 F1 C9 C2 DQ1 VSS_8 L1 M0_DDR_DQ[7] VSS_3 VSS_4 D8 NC_3 VSSQ_4 B3 C7 DQ0 VSS_7 J1 J9 NC_3 VSSQ_4 B3 VSS_6 J1 NC_2 VSSQ_3 C8 DQ2 DQ3 VSS_9 VSS_10 L9 C16 NC_3 VSSQ_4 VSS_5 F2 F8 H1 D9 C2 DQ1 DQ2 VSS_8 VSS_9 L1 H1 D9 C7 DQ0 DQ1 VSS_7 VSS_8 J9 F9 D1 E3 E8 DQ4 VSS_11 N1 N9 M0_DDR_DQ[8] M0_DDR_DQ8 H1 D9 B3 DQ0 VSS_6 VSS_7 J1 C8 E3 DQ3 VSS_10 L9 N1 C2 C8 DQ2 VSS_9 L1 L9 D2 DQ5 VSS_12 D21 NC_4 VSSQ_5 C7 C2 DQ1 VSS_8 J9 L1 NC_4 VSSQ_5 E8 DQ4 VSS_11 N9 NC_4 VSSQ_5 E3 DQ3 DQ4 VSS_10 VSS_11 N1 NC_3 VSSQ_4 E7 DQ6 DQ7 M0_DDR_DQ9 H9 C8 DQ2 VSS_9 L9 H9 D2 DQ5 VSS_12 H9 E8 DQ5 VSS_12 N9 H1 D9 A3 VSSQ_1 B2 B8 M0_DDR_DQ[9] E3 DQ3 DQ4 VSS_10 VSS_11 N1 NC_5 E7 DQ6 DQ7 NC_5 D2 E7 DQ6 NC_4 VSSQ_5 F1 NC_1 VSSQ_2 C9 D17 NC_5 E8 D2 DQ5 VSS_12 N9 A3 VSSQ_1 B2 B8 DQ7 VSSQ_1 B2 H9 F9 NC_2 NC_3 VSSQ_3 VSSQ_4 D1 M0_DDR_DQ[10] M0_DDR_DQ10 E7 DQ6 F1 NC_1 NC_2 VSSQ_2 VSSQ_3 C9 A3 NC_1 VSSQ_2 B8 H1 H9 NC_4 VSSQ_5 D9 C22 A3 DQ7 VSSQ_1 B2 B8 F9 H1 NC_3 NC_4 VSSQ_4 VSSQ_5 D1 D9 F1 F9 NC_2 NC_3 VSSQ_3 VSSQ_4 C9 D1 NC_5 J7 NC_5 NC_6 M0_DDR_DQ[11] M0_DDR_DQ11 F1 F9 NC_1 NC_2 VSSQ_2 VSSQ_3 C9 D1 H9 J7 NC_5 NC_6 H1 H9 NC_4 NC_5 VSSQ_5 D9 C18 H1 NC_3 NC_4 VSSQ_4 VSSQ_5 D9 J7 NC_6 M0_DDR_DQ[12] M0_DDR_DQ12 H9 J7 NC_5 NC_6 C21 M0_DDR_DQ[13] M0_DDR_DQ13 C17 M0_DDR_DQ[14] M0_DDR_DQ14 D20 M0_DDR_DQ[15] M0_DDR_DQ15 C13 M0_DDR_DQ[16] M0_DDR_DQ16 D7 M0_DDR_DQ[17] M0_DDR_DQ17 D13 M0_DDR_DQ[18] M0_DDR_DQ18 C6 M0_DDR_DQ[19] M0_DDR_DQ19 D14 M0_DDR_DQ[20] M0_DDR_DQ20 D6 M0_DDR_DQ[21] M0_DDR_DQ21 C14 M0_DDR_DQ[22] M0_DDR_DQ22 A5 M0_DDR_DQ[23] M0_DDR_DQ23 C7 M0_DDR_DQ[24] M0_DDR_DQ24 D12 Real USE : 1Gbit M0_DDR_DQ[25] M0_DDR_DQ25 D8 M0_DDR_DQ[26] M0_DDR_DQ26 H5TQ1G63DFR-PBC(x16) B13 M0_DDR_DQ[27] M0_DDR_DQ27 C9 M0_DDR_DQ[28] M0_DDR_DQ28 C12 1Gbit : T7(NC_6) OPT M0_DDR_DQ[29] M0_DDR_DQ29 OPT C8 M0_DDR_DQ[30] M0_DDR_DQ30 IC501 4Gbit : T7(A14) IC503 DDR_HYNIX D11 M1_DDR_VREFCA DDR_HYNIX M1_1_DDR_VREFCA IC503-*1 M0_DDR_DQ[31] M0_DDR_DQ31 K4B4G1646B-HCK0 IC501-*1 K4B4G1646B-HCK0 H5TQ4G63AFR-PBC H5TQ4G63AFR-PBC N3 M8 A0 VREFCA P7 N3 M8 A1 A0 VREFCA P3 P7 A2 A1 N2 H1 P3 A3 VREFDQ A2 P8 N2 H1 A4 M1_DDR_VREFDQ A3 VREFDQ M1_1_DDR_VREFDQ P2 N3 DDR3 M8 P8 P2 R8 A4 A5 L8 M1_DDR_A0 N3 A0 DDR3 VREFCA M8 R8 R2 A5 A6 A7 ZQ L8 M1_DDR_A0 A0 VREFCA R2 A6 ZQ P7 T8 A8 4Gbit A7 R3 B2 T8 A9 VDD_1 P7 L7 D9 4Gbit A8 M1_DDR_A1 A1 R3 L7 A9 A10/AP VDD_1 VDD_2 B2 D9 M1_DDR_A1 A1 R7 N7 A10/AP A11 VDD_2 VDD_3 G7 K2 R7 G7 P3 A12/BC VDD_4 M1_DDR_A2 P3 A2 (x16) N7 T3 A11 A12/BC A13 VDD_3 VDD_4 VDD_5 K2 K8 M1_DDR_A2 A2 (x16) T3 T7 M7 A13 A14 VDD_5 VDD_6 K8 N1 N9 N2 H1 T7 M7 A14 A15 VDD_6 VDD_7 N1 N9 N2 H1 M2 A15 VDD_7 VDD_8 R1 R9 M1_DDR_A3 A3 VREFDQ M2 VDD_8 R1 R9 M1_DDR_A3 A3 VREFDQ N8 BA0 BA1 VDD_9 P8 N8 BA0 BA1 VDD_9 P8 M3 BA2 A1 M1_DDR_A4 A4 M3 BA2 VDDQ_1 A1 M1_DDR_A4 A4 J7 K7 CK VDDQ_1 VDDQ_2 A8 C1 IC100 P2 J7 K7 CK VDDQ_2 A8 C1 P2 K9 CK CKE VDDQ_3 VDDQ_4 C9 M1_DDR_A5 A5 K9 CK CKE VDDQ_3 VDDQ_4 C9 M1_DDR_A5 A5 L2 VDDQ_5 D2 E9 LG1154D_H13D R8 L8 R543 L2 VDDQ_5 D2 E9 R8 L8 R545 240 K1 J3 CS ODT VDDQ_6 VDDQ_7 F1 H2 M1_DDR_A6 240 K1 CS ODT VDDQ_6 VDDQ_7 F1 M1_DDR_A6 A6 ZQ K3 RAS VDDQ_8 H9 A6 ZQ J3 K3 RAS VDDQ_8 H2 H9 R2 L3 CAS WE VDDQ_9 R2 VDDC15_M1 L3 CAS VDDQ_9 M1_DDR_A7 NC_1 J1 M1_DDR_A7 A7 WE NC_1 J1 A7 VDDC15_M1 T2 RESET NC_2 J9 L1 T8 T2 RESET NC_2 J9 L1 T8 NC_3 NC_4 L9 M1_DDR_A8 A8 NC_3 NC_4 L9 M1_DDR_A8 A8 F3 G3 DQSL R3 B2 F3 G3 DQSL DQSL R3 B2 C7 DQSL A9 N6 M1_DDR_A9 A9 VDD_1 C7 A9 M1_DDR_A9 A9 VDD_1 B7 DQSU DQSU VSS_1 VSS_2 B3 M1_DDR_A[0] M1_DDR_A0 L7 D9 B7 DQSU DQSU VSS_1 VSS_2 B3 L7 D9 E7 VSS_3 E1 G8 R6 M1_DDR_A10 A10/AP VDD_2 E7 DML VSS_3 VSS_4 E1 G8 M1_DDR_A10 A10/AP VDD_2 D3 DML DMU VSS_4 VSS_5 J2 J8 M1_DDR_A[1] M1_DDR_A1 D3 J2 R7 G7 VSS_6 DDR3 1.5V bypass Cap - Place these caps near Memory R7 G7 DMU VSS_5 J8 E3 DQL0 VSS_7 M1 DDR3 1.5V bypass Cap - Place these caps near Memory L6 M1_DDR_A11 A11 VDD_3 E3 DQL0 VSS_6 VSS_7 M1 M1_DDR_A11 A11 VDD_3 F7 F2 DQL1 VSS_8 M9 P1 M1_DDR_A[2] M1_DDR_A2 N7 K2 F7 F2 DQL1 DQL2 VSS_8 VSS_9 M9 P1 N7 K2 F8 H3 DQL2 DQL3 VSS_9 VSS_10 P9 T1 J6 M1_DDR_A12 A12/BC VDD_4 F8 H3 DQL3 VSS_10 P9 T1 M1_DDR_A12 A12/BC VDD_4 H8 DQL4 DQL5 VSS_11 VSS_12 T9 M1_DDR_A[3] M1_DDR_A3 T3 K8 H8 DQL4 DQL5 VSS_11 VSS_12 T9 T3 K8 G2 H7 DQL6 U5 M1_DDR_A13 A13 VDD_5 G2 H7 DQL6 DQL7 M1_DDR_A13 A13 VDD_5 D7 DQL7 VSSQ_1 B1 B9 M1_DDR_A[4] M1_DDR_A4 T7 N1 D7 VSSQ_1 B1 B9 T7 N1 C3 DQU0 DQU1 VSSQ_2 VSSQ_3 D1 J5 M1_DDR_A14 A14 VDD_6 C3 DQU0 DQU1 VSSQ_2 VSSQ_3 D1 M1_DDR_A14 A14 VDD_6 C8 C2 DQU2 VSSQ_4 D8 E2 M1_DDR_A[5] M1_DDR_A5 M7 N9 C8 C2 DQU2 VSSQ_4 D8 E2 M7 N9 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 T5 VDDC15_M0 M0_DDR_CKE A7 DQU3 VSSQ_5 E8 M1_DDR_A15 A15 VDD_7 A2 DQU5 VSSQ_7 F9 M1_DDR_A6 M1_DDR_A15 A15 VDD_7 A2 DQU4 VSSQ_6 F9 R1 B8 A3 DQU6 VSSQ_8 G1 G9 M1_DDR_A[6] R1 B8 DQU5 DQU6 VSSQ_7 VSSQ_8 G1 DQU7 VSSQ_9 K6 VDD_8 A3 DQU7 VSSQ_9 G9 VDD_8 M1_DDR_A[7] M1_DDR_A7 M2 R9 M2 R9 U6 R541 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9 M1_DDR_A[8] M1_DDR_A8 R520 N8 N8 M6 10K M1_DDR_BA1 BA1 M1_DDR_BA1 BA1 M1_DDR_A[9] M1_DDR_A9 10K M3 M3 V5 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2 M1_DDR_A[10] M1_DDR_A10 A1 A1 R5 VDDQ_1 VDDQ_1 M1_DDR_A[11] M1_DDR_A11 M0_DDR_RESET_N J7 A8 P5 VDDC15_M1 M1_DDR_CKE J7 A8 M1_U_CLK M1_D_CLK CK VDDQ_2 CK VDDQ_2 M1_DDR_A[12] M1_DDR_A12 K7 C1 K7 C1 L5 M1_D_CLKN CK VDDQ_3 M1_U_CLKN CK VDDQ_3 M1_DDR_A[13] M1_DDR_A13 K9 C9 K9 C9 T6 R540 M1_DDR_CKE CKE VDDQ_4 M1_DDR_CKE CKE VDDQ_4 M1_DDR_A[14] M1_DDR_A14 D2 D2 P6 M0_U_CLK R521 10K VDDQ_5 VDDQ_5 M1_DDR_A[15] M1_DDR_A15 M0_D_CLK L2 E9 L2 E9 10K CS VDDQ_6 CS VDDQ_6 K1 F1 K1 F1 200 R535 H5 M1_DDR_ODT 200 R519 M1_DDR_ODT ODT VDDQ_7 ODT VDDQ_7 M1_DDR_BA[0] M1_DDR_BA0 J3 H2 J3 H2 C561 0.1uF V6 M1_DDR_RESET_N C529 0.1uF M1_DDR_RASN RAS VDDQ_8 M1_DDR_BA1 M1_DDR_RASN RAS VDDQ_8 K3 H9 M1_DDR_BA[1] K3 H9 C530 C562 0.1uF M5 M1_DDR_CASN 0.1uF M1_DDR_CASN CAS VDDQ_9 M1_DDR_BA[2] M1_DDR_BA2 M0_U_CLKN CAS VDDQ_9 L3 M0_D_CLKN L3 M1_DDR_WEN M1_DDR_WEN WE WE J1 J1 R2 NC_1 NC_1 DDR_SAMSUNG M1_DDR_U_CLK M1_U_CLK M0_U_CLK M1_D_CLK M1_U_CLK T2 J9 T2 J9 IC503-*2 R1 M0_D_CLK M1_DDR_RESET_N RESET NC_2 K4B4G1646D-BCK0 M1_U_CLKN M1_DDR_RESET_N RESET NC_2 L1 M1_DDR_U_CLKN L1 DDR_SAMSUNG 100 F1 IC501-*2 NC_3 N3 M8 100 200 R581 NC_3 A0 VREFCA R530 M1_D_CLK L9 P7 200 R580 K4B4G1646D-BCK0 M1_DDR_D_CLK R518 F2 L9 P3 A1 NC_4 NC_4 N2 A2 A3 VREFDQ H1 M1_DDR_D_CLKN M1_D_CLKN F3 N3 A0 VREFCA M8 F3 P8 P2 A4 N5 M1_DDR_DQS0 DQSL P7 P3 A1 M1_DDR_DQS2 DQSL R8 A5 A6 ZQ L8 M1_DDR_CKE M1_DDR_CKE G3 N2 A2 A3 VREFDQ H1 G3 R2 A7 M0_U_CLKN M1_D_CLKN M1_U_CLKN M1_DDR_DQS_N0 P8 A4 M1_DDR_DQS_N2 DQSL T8 A8 M0_D_CLKN DQSL P2 R8 A5 L8 R3 L7 A9 A10/AP VDD_1 VDD_2 B2 D9 A6 ZQ G6 R2 T8 A7 R7 N7 A11 VDD_3 G7 K2 M1_DDR_ODT M1_DDR_ODT C7 A9 R3 A8 B2 C7 A9 T3 A12/BC A13 VDD_4 VDD_5 K8 F5 M1_DDR_DQS1 DQSU VSS_1 L7 A9 A10/AP VDD_1 VDD_2 D9 M1_DDR_DQS3 DQSU VSS_1 T7 M7 A14 VDD_6 N1 N9 M1_DDR_RASN M1_DDR_RASN B7 B3 R7 N7 A11 VDD_3 G7 K2 B7 B3 A15 VDD_7 VDD_8 R1 G5 M1_DDR_DQS_N1 DQSU VSS_2 T3 A12/BC A13 VDD_4 VDD_5 K8 M1_DDR_DQS_N3 DQSU VSS_2 M2 N8 BA0 VDD_9 R9 M1_DDR_CASN M1_DDR_CASN E1 T7 M7 A14 VDD_6 N1 N9 E1 M3 BA1 H6 VSS_3 A15 VDD_7 VDD_8 R1 VSS_3 BA2 VDDQ_1 A1 M1_DDR_WEN M1_DDR_WEN E7 G8 M2 N8 BA0 VDD_9 R9 E7 G8 J7 K7 CK VDDQ_2 A8 C1 M1_DDR_DM0 DML VSS_4 M3 BA1 M1_DDR_DM2 DML VSS_4 K9 CK CKE VDDQ_3 VDDQ_4 C9 D3 J2 BA2 VDDQ_1 A1 D3 J2 L2 VDDQ_5 D2 E9 K5 M1_DDR_DM1 DMU VSS_5 J7 K7 CK VDDQ_2 A8 C1 M1_DDR_DM3 DMU VSS_5 K1 CS ODT VDDQ_6 VDDQ_7 F1 M1_DDR_RESET_N M1_DDR_RESET_N J8 K9 CK CKE VDDQ_3 VDDQ_4 C9 D2 J8 J3 K3 RAS VDDQ_8 H2 H9 VSS_6 L2 VDDQ_5 E9 VSS_6 L3 CAS VDDQ_9 E3 M1 K1 CS ODT VDDQ_6 VDDQ_7 F1 E3 M1 WE NC_1 J1 F6 240 R501 M1_DDR_DQ0 DQL0 VSS_7 J3 K3 RAS VDDQ_8 H2 H9 M1_DDR_DQ16 DQL0 VSS_7 T2 RESET NC_2 J9 L1 M1_DDR_ZQCAL VDDC15_M0 F7 M9 L3 CAS VDDQ_9 F7 M9 NC_3 NC_4 L9 1% VDDC15_M0 VDDC15_M1 VDDC15_M1 M1_DDR_DQ1 DQL1 VSS_8 WE J1 M1_DDR_DQ17 DQL1 VSS_8 F3 DQSL VDDC15_M0 T2 NC_1 J9 F2 P1 G3 DQSL E2 VDDC15_M0 F2 P1 RESET NC_2 L1 M1_DDR_DQ18 M1_DDR_DQ2 DQL2 VSS_9 NC_3 NC_4 L9 DQL2 VSS_9 C7 DQSU VSS_1 A9 M1_DDR_DQS[0] M1_DDR_DQS0 M0_1_DDR_VREFCA F8 P9 F3 G3 DQSL F8 P9 B7 DQSU VSS_2 B3 E1 E1 M0_1_DDR_VREFCA_T M1_1_DDR_VREFCA M1_DDR_DQ3 DQSL M1_DDR_DQ19 DQL3 VSS_10 E7 VSS_3 G8 M1_DDR_DQS_N[0] M1_DDR_DQS_N0 M0_DDR_VREFCA M0_DDR_VREFCA_T M1_DDR_VREFCA DQL3 VSS_10 C7 A9 H3 T1 D3 DML VSS_4 J2 F3 H3 T1 B7 DQSU VSS_1 B3 M1_DDR_DQ20 DMU VSS_5 J8 M1_DDR_DQ4 DQL4 VSS_11 DQSU VSS_2 E1 DQL4 VSS_11 E3 DQL0 VSS_6 VSS_7 M1 R536 1K 1% M1_DDR_DQS[1] M1_DDR_DQS1 H8 T9 E7 VSS_3 G8 H8 T9 F7 DQL1 VSS_8 M9 R514 1K 1% DML VSS_4 F2 P1 R531 F4 M1_DDR_DQ21 1K 1% D3 J2 DQL5 VSS_12 R510 R554 1K 1% DQL2 VSS_9 1K 1% M1_DDR_DQ5 DQL5 VSS_12 DMU VSS_5 J8 F8 DQL3 VSS_10 P9 R550 M1_DDR_DQS_N1 G2 1K 1% M1_DDR_DQS_N[1] G2 E3 DQL0 VSS_6 VSS_7 M1 H3 H8 DQL4 VSS_11 T1 T9 P1 M1_DDR_DQ6 DQL6 F7 F2 DQL1 VSS_8 M9 P1 M1_DDR_DQ22 DQL6 G2 DQL5 VSS_12 M1_DDR_DQS[2] M1_DDR_DQS2 H7 F8 DQL2 DQL3 VSS_9 VSS_10 P9 H7 H7 DQL6 DQL7 P2 M1_DDR_DQ7 DQL7 H3 H8 DQL4 VSS_11 T1 T9 M1_DDR_DQ23 DQL7 D7 VSSQ_1 B1 B9 M1_DDR_DQS_N[2] M1_DDR_DQS_N2 B1 G2 DQL5 VSS_12 B1 C3 DQU0 DQU1 VSSQ_2 VSSQ_3 D1 R3 0.1uF DQL6 VSSQ_1 H7 DQL7 VSSQ_1 C8 DQU2 VSSQ_4 D8 0.1uF C2 E2 M1_DDR_DQS3 B1 D7 B9 0.1uF M1_DDR_DQS[3] 1% DQU3 VSSQ_5 0.1uF 0.1uF D7 B9 D7 VSSQ_1 B9 A7 DQU4 VSSQ_6 E8 1% R4 M1_DDR_DQ24 0.1uF DQU0 VSSQ_2 DQU0 VSSQ_2 A2 F9 1% M1_DDR_DQ8 C3 D1 1% 1% DQU0 VSSQ_2 DQU1 VSSQ_3 DQU5 VSSQ_7 R537 B8 G1 M1_DDR_DQS_N[3] M1_DDR_DQS_N3 C8 D8 C3 D1 1% DQU6 VSSQ_8 C3 D1 DQU2 VSSQ_4 A3 G9 R515 C2 E2 R532 M1_DDR_DQ25 DQU1 VSSQ_3 DQU7 VSSQ_9 R511 R555 DQU3 VSSQ_5 M1_DDR_DQ9 DQU1 VSSQ_3 A7 DQU4 VSSQ_6 E8 R551 C8 D8 A2 DQU5 VSSQ_7 F9 C8 D8 C512 B8 G1 1K G4 M1_DDR_DQ10 DQU2 VSSQ_4 A3 DQU6 VSSQ_8 G9 M1_DDR_DQ26 DQU2 VSSQ_4 C504 1K M1_DDR_DM0 C508 C2 E2 1K DQU7 VSSQ_9 M1_DDR_DM[0] C500 C552 1K 1K C2 E2 C550 E3 M1_DDR_DQ27 1K M1_DDR_DQ11 DQU3 VSSQ_5 DQU3 VSSQ_5 M1_DDR_DM[1] M1_DDR_DM1 A7 E8 A7 E8 T4 M1_DDR_DQ12 DQU4 VSSQ_6 M1_DDR_DQ28 DQU4 VSSQ_6 M1_DDR_DM[2] M1_DDR_DM2 A2 F9 A2 F9 P3 M1_DDR_DQ13 DQU5 VSSQ_7 M1_DDR_DQ29 DQU5 VSSQ_7 M1_DDR_DM[3] M1_DDR_DM3 B8 G1 B8 G1 M1_DDR_DQ14 DQU6 VSSQ_8 M1_DDR_DQ30 DQU6 VSSQ_8 A3 G9 A3 G9 C4 M1_DDR_DQ15 DQU7 VSSQ_9 M1_DDR_DQ31 DQU7 VSSQ_9 M1_DDR_DQ[0] M1_DDR_DQ0 K3 M1_DDR_DQ[1] M1_DDR_DQ1 B3 M1_DDR_DQ[2] M1_DDR_DQ2 J4 M1_DDR_DQ[3] M1_DDR_DQ3 A3 M1_DDR_DQ[4] M1_DDR_DQ4 VDDC15_M0 K2 VDDC15_M0 VDDC15_M0 VDDC15_M1 VDDC15_M1 VDDC15_M1 M1_DDR_DQ[5] M1_DDR_DQ5 VDDC15_M0 B4 M1_DDR_DQ[6] M1_DDR_DQ6 M0_1_DDR_VREFDQ K1 M0_1_DDR_VREFDQ_T M1_1_DDR_VREFDQ M1_DDR_DQ[7] M1_DDR_DQ7 M0_DDR_VREFDQ M0_DDR_VREFDQ_T M1_DDR_VREFDQ J3 M1_DDR_DQ8 R538 1K 1% M1_DDR_DQ[8] R516 1K 1% R533 D4 1K 1% * DDR_VTT R512 R556 1K 1% 1K 1% M1_DDR_DQ9 R552 1K 1% M1_DDR_DQ[9] H4 M1_DDR_DQ[10] M1_DDR_DQ10 C3 M1_DDR_DQ[11] M1_DDR_DQ11 G3 0.1uF 0.1uF M1_DDR_DQ12 0.1uF M1_DDR_DQ[12] 1% 0.1uF 0.1uF 1% D3 0.1uF 1% 1% 1% M1_DDR_DQ13 1uF 1uF R539 M1_DDR_DQ[13] 1% R517 R534 H3 R513 R557 M1_DDR_DQ14 R553 M1_DDR_DQ[14] VDDC15_M0 +3.3V_NORMAL C513 1K E4 C505 1K M1_DDR_DQ15 C509 C502 C516 1K M1_DDR_DQ[15] C501 C553 1K 1K C551 M3 1K M1_DDR_DQ[16] M1_DDR_DQ16 V4 R546 IC506 M1_DDR_DQ[17] M1_DDR_DQ17 10K 1% TPS51200DRCR [EP] L501 M4 UBW2012-121F M1_DDR_DQ[18] M1_DDR_DQ18 W3 R549 C510 M1_DDR_DQ[19] M1_DDR_DQ19 10K L4 1000pF REFIN VIN M1_DDR_DQ[20] M1_DDR_DQ20 1% 1 10 W4 THERMAL M1_DDR_DQ[21] M1_DDR_DQ21 L3 M1_DDR_DQ22 11 M1_DDR_DQ[22] VLDOIN PGOOD C515 Y2 2 9 4700pF M1_DDR_DQ[23] M1_DDR_DQ23 V3 M1_DDR_DQ[24] M1_DDR_DQ24 DDR_VTT N4 C511 VO GND M1_DDR_DQ[25] M1_DDR_DQ25 3 8 U4 22uF DDR_VTT M1_DDR_DQ[26] M1_DDR_DQ26 Place at the bottom side 10V M2 M1_DDR_DQ[27] M1_DDR_DQ27 PGND EN T3 L500 4 7 M1_DDR_DQ[28] M1_DDR_DQ28 UBW2012-121F N3 M1_DDR_DQ[29] M1_DDR_DQ29 U3 VOSNS REFOUT M1_DDR_DQ[30] M1_DDR_DQ30 5 6 C519 C520 C521 C522 P4 0.47uF 0.47uF 0.47uF 0.47uF M1_DDR_DQ[31] M1_DDR_DQ31 C503 C506 C507 C514 6.3V 6.3V 6.3V 6.3V 22uF 22uF 22uF 0.1uF 10V 10V 10V Close to REFOUT pin THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-005-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

+5V_CI_ON C702 C703 CI_DATA[0-7] 0.1uF 4.7uF 10V CI CI JK700 CI 10125901-115LF /PCM_CE1 35 1 R716 100 36 2 CI_DATA[3] /CI_CD1 CI 37 3 CI_DATA[4] CI_TS_DATA[3] 38 4 CI_DATA[5] CI_TS_DATA[4] 39 5 CI_DATA[6] CI_DATA[0-7] CI_TS_DATA[5] CI 40 6 CI_DATA[7] CI_TS_DATA[6] AR712 CI R721 33 CI_DATA[0] 33 EB_DATA[0] CI_TS_DATA[7] 41 7 CI_ADDR[10] CI_DATA[1] EB_DATA[1] /PCM_CE2 42 8 CI_ADDR[10] /PCM_IORD CI_DATA[2] EB_DATA[2] /PCM_IOWR 43 9 /PCM_OE CI_ADDR[11] CI_DATA[3] EB_DATA[3] 44 10 CI_ADDR[11] +5V_CI_ON CI_IN_TS_DATA[0-7] 45 11 CI_ADDR[9] CI_ADDR[9] 46 12 CI_ADDR[8] CI CI_ADDR[8] @netLa CI_IN_TS_DATA[0] CI_ADDR[13] R723 CI_DATA[4] AR713 EB_DATA[4] 47 13 CI_ADDR[13] 33 10K CI_IN_TS_DATA[1] 48 14 CI_ADDR[14] CI_DATA[5] EB_DATA[5] CI_ADDR[14] CI CI_IN_TS_DATA[2] 49 15 CI_DATA[6] EB_DATA[6] /PCM_WE CI_IN_TS_DATA[3] 50 16 CI_DATA[7] EB_DATA[7] /PCM_IRQA 51 17 C706 0.1uF C707 CI EB_DATA[0-7] CI 0.1uF +5V_CI_ON 52 18 16V CI_IN_TS_DATA[4] 53 19 CI_DATA[0-7] CI_IN_TS_DATA[5] 54 20 CI_IN_TS_DATA[6] 55 21 CI_ADDR[12] R709 CI_ADDR[12] 10K CI_IN_TS_DATA[7] 56 22 CI_ADDR[7] CI_ADDR[7] CI 57 23 CI_ADDR[6] CI_TS_CLK CI_ADDR[6] R701 33 CI 58 24 CI_ADDR[5] PCM_RESET CI_ADDR[5] R702 33 CI 59 25 CI_ADDR[4] /PCM_WAIT CI_ADDR[4] 60 26 CI_ADDR[3] CI_ADDR[3] /PCM_REG 61 27 CI_ADDR[2] CI_ADDR[2] CI_TS_VAL 62 28 CI_ADDR[1] CI_ADDR[1] CI_TS_SYNC 63 29 CI_ADDR[0] CI_ADDR[0] 64 30 CI_DATA[0] CI_TS_DATA[0] 65 31 CI_DATA[1] CI_TS_DATA[1] 66 32 CI_DATA[2] CI_TS_DATA[2] /CI_CD2 R717 CI 100 67 33 68 34 /PCM_CE2 G2 69 G1 CI_IN_TS_VAL CI_IN_TS_CLK CI_IN_TS_SYNC C705 12pF 50V OPT TPO_DATA[0-7] CI AR701 TPO_DATA[0] 33 CI_IN_TS_DATA[0] TPO_DATA[1] CI_IN_TS_DATA[1] TPO_DATA[2] CI_IN_TS_DATA[2] TPO_DATA[3] CI_IN_TS_DATA[3] TPO_DATA[4] CI_IN_TS_DATA[4] TPO_DATA[5] CI_IN_TS_DATA[5] TPO_DATA[6] CI_IN_TS_DATA[6] TPO_DATA[7] CI_IN_TS_DATA[7] AR706 CI 33 CI CI AR707 AR711 33 33 CI CI_ADDR[3] EB_ADDR[3] CI_ADDR[12] EB_ADDR[12] AR705 33 CI_ADDR[0] EB_ADDR[0] CI_ADDR[13] EB_ADDR[13] TPO_CLK CI_IN_TS_CLK CI_ADDR[2] EB_ADDR[2] CI_ADDR[14] EB_ADDR[14] TPO_SOP CI_IN_TS_SYNC CI_ADDR[1] EB_ADDR[1] /PCM_REG CAM_REG_N TPO_VAL CI_IN_TS_VAL CI AR708 CI 33 CI_ADDR[4] EB_ADDR[4] AR710 33 CI_ADDR[5] EB_ADDR[5] /PCM_OE EB_OE_N CI_ADDR[6] EB_ADDR[6] /PCM_WE EB_WE_N CI_ADDR[7] EB_ADDR[7] /PCM_IORD EB_BE_N1 /PCM_IOWR EB_BE_N0 +5V_NORMAL CI AR709 33 CI_ADDR[8] EB_ADDR[8] CI_ADDR[9] EB_ADDR[9] CI_ADDR[10] EB_ADDR[10] R703 R705 AR702 CI_ADDR[11] EB_ADDR[11] 10K 10K /PCM_WAIT CAM_WAIT_N /PCM_IRQA CAM_IREQ_N /CI_CD2 CAM_CD2_N 100 /CI_CD1 CAM_CD1_N CI CI C700 C701 0.1uF 0.1uF 16V 16V AR703 CI CI_TS_CLK TPI_CLK CI_TS_VAL TPI_VAL C704 100 CI_TS_SYNC TPI_SOP 12pF 50V OPT AR704 CI CI_TS_DATA[7] TPI_DATA[7] CI_TS_DATA[6] TPI_DATA[6] CI_TS_DATA[5] TPI_DATA[5] 100 CI POWER ENABLE CONTROL CI_TS_DATA[4] TPI_DATA[4] IC700 +5V_NORMAL AP2151WG-7 +5V_CI_ON AR700 CI CI_TS_DATA[3] TPI_DATA[3] IN OUT 5 1 CI_TS_DATA[2] TPI_DATA[2] C709 CI CI_TS_DATA[1] TPI_DATA[1] 0.1uF C708 100 50V GND CI_TS_DATA[0] TPI_DATA[0] 2 1uF CI CI R706 25V 10K R704 CI 100 EN FLG CI PCM_5V_CTL 4 3 R700 10K CI THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-007-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCIA Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

RESET_IC_DIODES IC2307-*1 Power_DET RESET 2 APX803D29 3 VCC 1 GND PD_20_24V_DIODES +12V +3.5V_ST +3.5V_ST IC2308-*1 R2337 100K APX803D29 PD_+12V PD_+3.5V RESET_IC_ROHM R2338 RESET 2 3 VCC R2325 R2330 IC2307 10K 2.7K 0 1 OPT 1% 5% BD48K28G GND POWER_DET VDD 3 2 VOUT OLED_AC_DET C2355 1 PD_OLED_AC PD_+12V R2369 0.1uF GND 39K R2326 16V 1% 1.2K PWR_DET_MERGE 1% C2365 0.1uF R2315 16V PD_20_24V not to RESET 0 +24V R2336 at 8kV ESD 100K C2362 PD_20_24V_ROHM 0.1uF PWR_DET_SEPARATE PD_20V PD_24V IC2308 16V PD_UHD_24V R2327-*2 R2327-*1 R2327 BD48K28G 9.1K 5.6K 8.2K 1% 1% 1% R2316 POWER_DET_1 VDD VOUT 0 3 2 1 PWR_DET_SEPARATE PD_UHD_24V PD_20V PD_24V C2356 R2328-*1 R2328 0.1uF GND R2328-*2 24V-->3.48V 1.6K 1.3K 1.5K 16V 1% 1% 1% PD_20_24V 20V-->3.51V 12V-->3.58V ST_3.5V-->3.5V +2.5V T2 : Max 1.7A else : Max 0.7A +12V Main +1.5V +1.5V_DDR L2301 +2.5V_Normal BLM18PG121SN1D IC2302 R2312 AP2132MP-2.5TRG1 [EP] POWER_ON/OFF2_2 1.2K R2321 DCDC_TI 10K IC2303-*1 C2341 C2302 C2360 TPS54327DDAR [EP]GND 1 8 R2 10uF 0.1uF eMMC POWER 0.1uF 16V DCDC_ROHM EN VIN THERMAL +3.3V_NORMAL PG GND 1 8 IC2303 THERMAL VFB VBST R2322 BD9D320EFJ 3.9K 9 9 2 7 R1 [EP]FIN 2 7 +3.3V_NORMAL 3.3V_EMMC ADJ VREG5 SW EN 3 6 +3.3V_NORMAL POWER_ON/OFF2_3 SS GND 3 6 R2313 EN VIN 4 5 10K 1 8 VIN VOUT 16V THERMAL C2327 UB95/95/UC97_H13_DDR_Voltage 0.1uF L2302 0.1uF +5V_NORMAL 4 2A 5 R2303 R2305 FB BOOT C2318 9 BLM18PG121SN1D R2341 2 7 R2346 16V 10K 11K VCTRL NC R1 18K 4.3K L2308 ZD2302 EAN61387601 C2342 1% 1% 2.2uH VREG SW OPT 5V 10uF 3 6 C2305 B C2300 10V C2303 0.1uF +3.5V_ST 22uF 100pF NR5040T2R2N 16V 50V 10V SS GND C2337 1.0V_DCDC_TI 4 3A 5 C2320 22uF C2321 ZD2303 C E 22 1.5K 22uF 2.5V 1uF C2315-*1 10V 10V R2333 LD2300 R2342 R2307 OPT Q2303 3300pF 22K C2313 C2315 2SC3052 50V 1uF 2200pF 1% 10V 50V UB98/UC9_H13_DDR_Voltage 1.0V_DCDC_ROHM Vout=0.6*(1+R1/R2) R2305-*1 R2 4.99K 1% Vout=0.765*(1+R1/R2)=1.516V +12V LG1154A +1.0V_VDD L2300 BLM18PG121SN1D +1.0V_VDD +1.2V_CORE R2368 1/16W 100 C2301 C2359 1% 10uF 0.1uF R2359 DCDC_ROHM 10K 16V IC2300 R1 BD9D320EFJ R2362 ZD2300 [EP]FIN 2.5V R2363 1/16W 39K 5.1K OPT 1% R2304 1/16W POWER_ON/OFF2_3 10K EN VIN 5% 1% 1/16W 91K 1 8 R2361 16V THERMAL 0.1uF C2370 [EP] GND2 GND1 NC_3 TRIP R2364 4.87K 1/16W 1% FB BOOT C2314 1000pF +12V 9 VO 2 7 50V R2 1% 1/16W 27K NR5040T2R2N 1% R2360 R2302 L2307 R1 1% 1/16W 20K R2365 28 27 26 25 24 11K VREG SW 2.2uH DCDC_TI IC2300-*1 3 6 RF 1 23 FB C2308 TPS54327DDAR [EP]GND 100pF THERMAL 50V EN VIN PGOOD GND L2322 SS GND 1 8 2 29 22 3A C2340 THERMAL 1.0V_DCDC_TI 4 5 C2348 22uF VFB VBST R2356 1K EN MODE 9 22uF 2 7 POWER_ON/OFF2_4 3 21 C2312-*1 R2306 10V 16V 10V 3300pF VREG5 3 6 SW 0.1uF VBST IC2309 VREG 33K C2310 C2312 4 20 50V 1uF 2200pF SS GND TPS53513RVER R2358 4 5 C2372 NC_1 VDD 10V 50V 5 19 4.7 1% 1.0V_DCDC_ROHM C2369 R2355 2K R2 SW_1 6 18 NC_2 0.1uF 1/16W C2374 C2376 Vout=0.765*(1+R1/R2) 16V 5% SW_2 7 17 VIN_3 1uF 10V C2375 10uF 10uF SW_3 VIN_2 16V 16V +1.2V_VDD L2321 8 16 1uH SW_4 9 8A 15 VIN_1 10 11 12 13 14 R2357 1/10W ZD2304 3.3 C2361 C2353 C2366 2.5V D2301 5% C2373 PGND_1 PGND_2 PGND_3 PGND_4 PGND_5 OPT 22uF 22uF 30V 22uF OPT 2200pF 50V C2371 470pF 50V Vout=0.6*(1+R1/R2) POWER UP SEQUENCE 5V/3.3V->2.5V->1.5V/1.1V->1.0V LG1154D : 3.3V->2.5V->1.5V->1.1V LG1154AN : 3.3V->2.5V->1.0V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-023-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

+3.3V_NORMAL for UB98, UC9 R2339 1/16W 18K 1% R2323 10K R1 R2335 R2340 1/16W 39K 3.6K 1% 1/16W 5% 1% 1/16W 91K R2334 C2326 [EP] GND2 GND1 NC_3 TRIP R2366 4.87K 1/16W 1000pF +12V VO 50V 1% R2 1/16W 27K 1% R2331 1% 1/16W 20K R2367 28 27 26 25 24 RF 1 23 FB THERMAL PGOOD 2 22 GND L2309 29 R2311 1K EN MODE POWER_ON/OFF2_1 3 21 16V 0.1uF VBST IC2301 VREG 4 20 TPS53513RVER R2320 C2332 NC_1 VDD 5 19 4.7 C2325 R2308 2K SW_1 NC_2 6 18 0.1uF 1/16W C2363 C2367 +3.3V_NORMAL SW_2 7 17 VIN_3 C2364 16V 5% 1uF 10uF 10uF 10V 16V L2305 SW_3 8 16 VIN_2 16V 1uH SW_4 9 8A 15 VIN_1 10 11 12 13 14 R2319 1/10W ZD2301 3.3 C3346 C2304 C2319 C2323 2.5V D2300 5% C2345 PGND_1 PGND_2 PGND_3 PGND_4 PGND_5 OPT 22uF 22uF 22uF 30V 22uF OPT 2200pF 50V C2328 470pF 50V Vout=0.6*(1+R1/R2) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

+5.0V normal & USB (65EC97 Only) 1% R2505150K 1% R2 R2502 16K 1% C2506 OPT +12V 2200pF C2507 C2508 R2504 16K 50V 1% 1/16W 100pF 0.047uF 6.8K R2509 R2506 50V 25V 10K C2512 C2513 C2514 10uF RSET2 RSET1 22uF 22uF [EP] AGND RLIM COMP C2510 R1 10V 10V FB SS L2501 120-ohm 82pF 1% 1/16W 51K 50V R2510 28 27 26 25 24 23 22 VIN_1 1 21 LX_3 L2502 THERMAL 4.7uH VIN_2 2 29 20 LX_2 C2501 C2502 C2504 VIN_3 3 19 LX_1 C2509 10uF 10uF 0.1uF 50V PGND_1 IC2501 BST R2507 0 0.047uF 25V +5V_NORMAL 35V 35V 4 18 OPT SN1302001(TPS65286RHDR) PGND_2 5 17 SW_IN2 C2511 R2508 1/16W 100K 100K R2511 PGND_3 SW_IN1 1/16W 6 16 1uF 5% 5% V7V 7 6A 15 NFAULT1 10V /USB_OCD3 25V 1uF C2503 10 11 12 13 14 8 9 5% 1/16W 0 R2501 MODE/SYNC EN SW_OUT2 SW_OUT1 SW_EN2 SW_EN1 NFAULT2 /USB_OCD2 C2505 +5V_USB_2 +5V_USB_3 USB_CTL2 USB_CTL3 R2503 10K 0.0068uF POWER_ON/OFF1 50V Vout=0.6*(1+R1/R2)=5.1V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

55/65 UHD OLED POWER MMBT3906(NXP) +3.5V_ST +3.3V_NORMAL 10K R2602 1 R2607 R2601 1K Q2601 RL_ON 10K 2 R2606 100 INV_CTL 3 P2600 SMAW200-H24S5 +3.3V_NORMAL PWM_DIM 3.3K PWR ON 1 2 INV CTL R2604 PD_OLED_AC OPT 3.5V_ST 3.5V 3 4 DPC_CTL 0 L2601 OLED_AC_DET DPC_CTL R2608 0 R2609 0 +3.5V_ST 3.5V 5 6 3.5V R2603 UBW2012-121F 3.3K GND 7 8 GND R2605 C2601 24V 9 10 24V PWM_DIM2 0.1uF GND 11 12 GND +12V 16V 12V 12V DPC_CTL UBW2012-121F 13 14 12V 15 16 24V L2605 +24V GND 17 18 GND UBW2012-121F C2602 D2601 L2602 0.1uF NC 19 20 NC 23.2V 50V UBW2012-121F 12V 12V 21 22 L2606 C2605 GND 23 24 GND UBW2012-121F 0.1uF L2603 50V 25 UBW2012-121F L2604 +12V C2603 C2604 C2606 10uF 10uF 10uF 16V 16V 16V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-026-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS OLED 2014-03-08 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER WAFER Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

SW2800 +3.5V_ST JS2235S R2806 EL_DET_22V 10K R2802 EL_VDD_DETECT_22V 100K 1 6 OLED_DEBUG R2803 PD_22V_ONSEMI 0 EL_DET_22V IC2850 OPT 2 5 EL_VDD_MONITOR R2800 NCP803SN293 R2804 OLED_DEBUG R2805 5.6K 0 0 1% OPT OLED_MP 3 4 To monitor EL_VDD voltage. VCC 3 2 RESET EL_DET_22V 1 C2800 R2801 0.1uF GND 1.3K 16V 1% EL_DET_22V R2807 0 EL_VDD_MONITOR POWER_DET_1 PD_22V_DIODES IC2850-*1 PWR_DET_MERGE APX803D29 VCC 3 2 RESET 1 GND THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-028-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS OLED 2014-03-11 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ELVDD DETECT Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Renesas MICOM For Debug +3.5V_ST CAM_PWR_ON_CMD 8pF 8pF MICOM_DEBUG R3013 1K R3010 10K C3002 C3003 LOGO_LIGHT Don’t remove R3014, MICOM_DEBUG MICOM_DEBUG LOGO_LIGHT MICOM_RESET P3000 12507WS-04L not making float P40 X3000 1 32.768KHz +3.5V_ST 2 MICOM_DEBUG HDMI_WAUP:HDMI_INIT R3020 3 4.7M 4 MHL_DET OPT MICOM_RESET TP3009 5 10K MHL_DET R3019 R3022 10K POWER_DET_1 MICOM_RESET_SW GND MICOM_RESET_22OHM SW3000 JTP-1127WEM 2 1 22 R3023 270K CAM_PWR_ON_CMD OPT C3004 P124/XT2/EXCLKS 0.47uF 0.1uF +3.5V_ST 4 3 16V R3021 P122/X2/EXCLK P41/TI07/TO07 C3001 P137/INTP0 P120/ANI19 P40/TOOL0 CAM_RESET CAM_RESET P123/XT1 C3000 P121/X1 0.1uF MICOM_RESET_33OHM R3021-*1 33 RESET +3.5V_ST REGC VDD VSS R3018 10K GP4 High/MID Power SEQUENCE 48 47 46 45 44 43 42 41 40 39 38 37 P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON I2C_SCL_MICOM POWER_ON/OFF! P61/SDAA0 P00/TI00/TXD1 I2C_SDA_MICOM 2 35 SCART_MUTE SCART_MUTE P62 3 34 P01/TO00/RXD1 POWER_ON/OFF2_4 MODEL1_OPT_4 POWER_ON/OFF2_4 POWER_ON/OFF2_1 PANEL_CTL P63 4 33 P130 PANEL_CTL P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP POWER_ON/OFF2_1 WOL/WIFI_POWER_ON 5 32 KEY2 IR P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB 31 P21/ANI1/AVREFM POWER_ON/OFF2_2 KEY1 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2 HDMI_CEC P73/KR3/SO01 MICOM_LEAD_Au P23/ANI3 POWER_ON/OFF2_3 POWER_ON/OFF2_2 8 29 MODEL1_OPT_3 POWER_ON/OFF2_3 P72/KR2/SO21 9 28 P24/ANI4 MODEL1_OPT_0 P71/KR1/SI21/SDA21 10 27 P25/ANI5 POWER_ON/OFF2_4 EYE_SDA SIDE_HP_MUTE P70/KR0/SCK21/SCL21 11 26 P26/ANI6 EYE_SCL MODEL1_OPT_2 CAM_SLEEP CAM_SLEEP P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7 TP3002 MODEL1_OPT_1 SOC_RESET 13 14 15 16 17 18 19 20 21 22 23 24 EYE_Q_10P AR3000 +3.5V_ST 3.3K P50/INTP1/SI11/SDA11 P51/INTP2/SO11 P17/TI02/TO02 P16/TI01/TO01/INTP5 P15/PCLBUZ1/SCK20/SCL20 P14/RXD2/SI20/SDA20 P13/TXD2/SO20 P12/SO00/TXD0/TOOLTXD P11/SI00/RXD0/TOOLRXD/SDA00 P10/SCK00/SCL00 P146 P147/ANI18 MICOM MODEL OPTION MICOM MODEL OPTION +3.5V_ST 0 1 P124/XT2/EXCLKS MODEL_OPT_0 NON LOGO LOGO For LOGO LIGHT P122/X2/EXCLK P41/TI07/TO07 98UB98_Moving_SPK MICOM_LOGO_LIGHT P137/INTP0 P120/ANI19 Non_OLED_AC_DET P40/TOOL0 MICOM_H13/H14 P123/XT1 10K 10K 10K 10K 10K 10K 10K LCD / UHD MICOM_OLED P121/X1 MODEL_OPT_1 OLED Need to Assign ADC port MICOM_GED MICOM_EPI RESET REGC VDD VSS R3006-*2 R3000 R3002 R3004 R3006 R3011 R3006-*1 MODEL_OPT_2 NON_EPI EPI 48 47 46 45 44 43 42 41 40 39 38 37 P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 MODEL_OPT_3 M14 H13 / H14 P61/SDAA0 2 35 P00/TI00/TXD1 P62 3 34 P01/TO00/RXD1 MODEL_OPT_4 P63 4 33 P130 NON_GED GED MODEL1_OPT_0 P31/TI03/TO03/INTP4 5 IC3000-*1 32 P20/ANI0/AVREFP P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM MODEL1_OPT_1 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2 P73/KR3/SO01 MICOM_LEAD_Cu P23/ANI3 8 29 MODEL1_OPT_2 P72/KR2/SO21 P24/ANI4 9 28 MODEL1_OPT_3 P71/KR1/SI21/SDA21 10 27 P25/ANI5 P70/KR0/SCK21/SCL21 11 26 P26/ANI6 SOC_RX POWER_DET AMP_MUTE CAM_CTL CAM_CTL WOL/ETH_POWER_ON EDID_WP INV_CTL WOL_CTL MODEL1_OPT_4 POWER_ON/OFF1 SOC_TX P30/INTP3/RTC1HZ/SCK11/SCL11 P27/ANI7 LED_R 12 25 13 14 15 16 17 18 19 20 21 22 23 24 MICOM_NON_LOGO_LIGHT 98UB98_Moving_SPK P50/INTP1/SI11/SDA11 P51/INTP2/SO11 P17/TI02/TO02 P16/TI01/TO01/INTP5 P15/PCLBUZ1/SCK20/SCL20 P14/RXD2/SI20/SDA20 P13/TXD2/SO20 P12/SO00/TXD0/TOOLTXD P11/SI00/RXD0/TOOLRXD/SDA00 P10/SCK00/SCL00 P146 P147/ANI18 MICOM_NON_GED MICOM_LCD/UHD MICOM_NON_EPI 0.1uF 10K 10K 10K 10K 10K 10K 10K OLED_AC_DET C3005 MICOM_M14 MODEL_OPT_1 LCD_MICOM_CODE OLED_MICOM_CODE R3007-*2 R3001 R3003 R3007 R3012 R3007-*1 R3005 Pull Up MICOM_OLED Non_POWER_AC_DET For CEC LED_R Pull Down MICOM_LCD/UHD POWER_AC_DET EDID_WP +3.5V_ST Pull up + pull down 98UB98_Moving_SPK SOC_RESET R3024 R3025 27K 120K G D3000 BAT54_SUZHO CEC_REMOTE HDMI_CEC D S Q3000 RUE003N02 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-030-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014.03.11 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

5V_HDMI_1 5V_HDMI_1 HDMI_3.3V 3.3V_Sil9617 Current Limit 5V_HDMI_4 +5V_NORMAL 5V_MHL L3216 ESD_HDMI +5V_NORMAL TX0SDA VA3216 MN864778_RESET R3298 R3234 R3234-*1 IC3207 BLM31PG500SN1 33 C3233 0 10 5V_MHL TPS2553DBV 50-ohm HDMI_HPD_1 TX0SCL L3208 P_XOUT L3202 HDMI_Damping0ohm HDMI_Damping10ohm BLM18PG121SN1D BLM18PG121SN1D X3200 20pF Test1_ANA_MON1 R3265 R3266 R3267 R3268 I2C_SDA5 I2C_SCL5 27MHz TX1SDA R3235 1.8K 1.8K 1.8K 1.8K BODY_SHIELD X-TAL_1 GND_2 IN OUT D3211 R3241 P_XOUT 47K 1 6 2.2M 1 4 Test2_ANA_MON2 P_XIN AR3207 TX1SCL C3218 C3249 ZD3200 30V 20 33 GND_1 X-TAL_2 C3219 C3236 2 3 0.1uF 0.1uF 5V 1% OPT C3242 10K R3243 10K R3244 1/16W Test3_ANA_MON3 R3269 0 0.1uF GND ILIM R3289 ESD_HDMI 22uF 16V OPT VA3203 TX0SDA 16V 16V 2 5 10uF DDC_SDA_1_R9531 C3214 10V 100K 19 R3270 0 20K 10V HOT_PLUG_DETECT P_AVDD11 DDC_SCL_1_R9531 P_XIN TX0SCL P_VDD33 R3295 18 EN FAULT VDD[+5V] 20pF R3271 0 MHL_DET 3 4 P_AVDD33 TX1SDA P_VDD11 #MHL_OCP 0 0 17 R3272 0 DDC/CEC_GND VA3204 VA3207 ESD_HDMI R3294 ESD_HDMI TX1SCL P_VDD33 +1.0V_R9531 3.3V_Sil9617 16 10K R3230 R3258 SDA 15 SCL 14 #MHL_OCP TP3203 RESERVED CEC_REMOTE 13 AVDD10_2 CEC D3202 [EP]GND VDD33_2 RSVD_16 RSVD_15 RSVD_14 RSVD_13 RSVD_12 RSVD_11 RSVD_10 VDD33_1 RSVD_9 12 IP4294CZ10-TBR R1X2P R1X2N R1X1P R1X1N R1X0P R1X0N R1XCP R1XCN TMDS_CLK- CH1ALRCLK SYSCLK/XI C3203 C3209 C3210 C3211 CH0AMCLK CH1ABCLK TX0ARCIN TX1ARCIN 11 0.1uF 0.1uF 0.1uF 10uF 16V VDD11_6 CH1ASD0 VDD11_5 VDD33_4 TMDS_CLK_SHIELD 1 10 10V 16V 16V TX0SDA TX0SCL TX1SDA TX1SCL NRESET RX3P5V CK-_HDMI1_R9531 P_AVDDH33 10 NC_11 NC_10 LPSA0 LPSA1 NC/XO HSDA0 HSCL0 NIRQ1 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 TMDS_CLK+ 2 9 [EP] NC_9 NC_8 NC_7 NC_6 NC_5 NC_4 NC_3 NC_2 NC_1 CEC1 CEC5 9 CK+_HDMI1_R9531 AVDD10_1 1 57 R0X2P VSS D2+_HDMI4_JACK TMDS_DATA0- 3 8 RSVD_1 2 56 R0X2N 8 OPT THERMAL D2-_HDMI4_JACK RSVD_2 R0X1P TMDS_DATA0_SHIELD 4 7 3 77 55 D1+_HDMI4_JACK 7 D0-_HDMI1_R9531 RSVD_3 4 54 R0X1N D1-_HDMI4_JACK TMDS_DATA0+ 5 6 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 RSVD_4 5 53 R0X0P D0+_HDMI1_R9531 D0+_HDMI4_JACK 6 RSVD_5 R0X0N R3255 5.1 TMDS_DATA1- VDD33_1 1 108 VDD11_4 P_AVDDH11 6 52 D0-_HDMI4_JACK 5 D3203 RSVD_6 7 51 R0XCP R3256 5.1 TMDS_DATA1_SHIELD VDD11_1 AVDDH33_4 CK+_HDMI4_JACK IP4294CZ10-TBR 2 107 RSVD_7 8 50 R0XCN 4 THERMAL RSVD_8 VDD10_2 CK-_HDMI4_JACK TMDS_DATA1+ P1TX2P 3 106 P0RX2P 9 49 PWRMUX_OUT_SIL9617 HDMI_1_RX2+ 145 D2+_HDMI4_MHL VDD10_1 IC3206 ARC 3 1 10 10 48 R3227 I2C_SCL2 C3213 TMDS_DATA2- D1-_HDMI1_R9531 AVDD33_1 4 105 P0RX2M TAVDD10 SPDIF_IN 10K 10uF D2-_HDMI4_MHL 11 SIL9617 47 I2C_SDA2 2 2 9 TX2P CSCL TMDS_DATA2_SHIELD D1+_HDMI1_R9531 P1TX2M 5 104 P0RX1P D2+_HDMI4_MHL 12 46 HDMI TX port 1 HDMI_1_RX2- D1+_HDMI4_MHL TX2N CSDA 1 3 8 D2-_HDMI4_MHL 13 45 5V_HDMI_4 TMDS_DATA2+ OPT P1TX1P 6 103 P0RX1M TX1P PWRMUX_OUT +5V_NORMAL HDMI_1_RX1+ D1-_HDMI4_MHL D1+_HDMI4_MHL 14 44 4 7 TX1N SBVCC5 R3249 10 D2-_HDMI1_R9531 AVDD11_1 7 102 AVDD11_12 D1-_HDMI4_MHL 15 43 R3251 TX0P R0PWR5V 10 05008WR-H19C. 5 6 D0+_HDMI4_MHL 16 42 D2+_HDMI1_R9531 P1TX1M 8 101 P0RX0P TX0N CBUS_HPD0 JK3203 HDMI_1_RX1- D0+_HDMI4_MHL D0-_HDMI4_MHL 17 41 HDMI_HPD_4_MHL C3220 R3250 P1TX0P P0RX0M TXCP 18 40 DSCL0 9 100 CK+_HDMI4_MHL DDC_SCL_MHL 1uF 5.1K HDMI1 HDMI_1_RX0+ AVDD33_2 AVDD11_11 D0-_HDMI4_MHL CK-_HDMI4_MHL TXCN 19 39 DSDA0 DDC_SDA_MHL 10V 10 99 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 HDMI4 P_AVDD33 HDMI_1_RX0- P1TX0M 11 IC3200 98 P0RXCP CK+_HDMI4_MHL TPWR_CI2CA RSVDL_1 INT RESET_N CD_SENSE DSDA4[VGA] DSCL4[VGA] RSVDH_1 RSVDH_2 RSVDL_2 RSVDL_3 RSVDH_3 RSVDH_4 RSVDL_4 RSVDL_5 DSDA1 DSCL1 CBUS_HPD1 R1PWR5V P1TXCP 12 97 P0RXCM 5V_HDMI_2 HDMI_1_CLK+ CK-_HDMI4_MHL AVDD11_2 P1RX2P 510 R3225 13 96 P1TXCM MN864778P P1RX2M D2+_HDMI3 SIL9617_RESET VA3205 R3205 AR3204 HDMI_1_CLK- 14 95 D2-_HDMI3 1K R3218 33 ESD_HDMI P1EXT_SWING P1RX1P R3216 5.1K R3217 5.1K 4.7K 1/16W 15 94 D1+_HDMI3 C 4.7K R3233 HDMI_INT_EDID DDC_SDA_2 NC[ANA_MON3] P1RX1M R3210 Q3200 16 93 MMBT3904(NXP) B 1K Test3_ANA_MON3 D1-_HDMI3 BODY_SHIELD HDMI_HPD_2 DDC_SCL_2 R3202 P0TX2P 17 92 AVDD11_10 HDMI_0_RX2+ +3.3V_NORMAL 100K R3247 VA3209 VA3214 20 E ESD_HDMI AVDD33_3 18 91 P1RX0P 4.7K ESD_HDMI D0+_HDMI3 ESD_HDMI VA3201 HDMI_EXT_EDID P0TX2M 19 90 P1RX0M HDMI TX port 0 19 HDMI_0_RX2- D0-_HDMI3 HOT_PLUG_DETECT R3222 47K P0TX1P 20 89 AVDD11_9 18 SIL9617_INT R3223 47K HDMI3 HDMI_0_RX1+ VDD[+5V] +5V_NORMAL 5V_HDMI_2 AVDD11_3 21 88 P1RXCP +3.3V_NORMAL PWRMUX_OUT_SIL9617 17 CK+_HDMI3 DDC/CEC_GND S P0TX1M P1RXCM Q3203 R3206 16 HDMI_0_RX1- 22 87 CK-_HDMI3 R3201 SI1012CR-T1-GE3 10K OPT SDA G R3224 R3226 R3229 R3246 P0TX0P AVDDH33_3 1K C3200 23 86 47K 47K 47K MHL_DET 15 SPDIF_OUT_ARC HDMI_0_RX0+ 47K SCL 1uF D AVDD33_4 24 85 NC[ANA_MON1] 14 R3207 10V OPT Test1_ANA_MON1 +3.3V_NORMAL RESERVED 3.9K D3204 VA3208 P_AVDD33 P0TX0M CEC0 OPT CEC_REMOTE ESD_HDMI C3201 25 84 13 CEC RCLAMP0544T.TCT 0.1uF HDMI_0_RX0- P_AVDDH33 6.5VTO11.0V 16V P0TXCP 26 83 CEC2 12 HDMI_0_CLK+ R3200 R3209 TMDS_CLK- 1 8 R3212 5.1K R3215 5.1K ARC AVDD11_4 CEC3 +5V_NORMAL R3211 47K 47K 47K CK-_HDMI2 510 R3228 27 82 R3213 47K 11 TMDS_CLK_SHIELD 2 7 AR3209 CK+_HDMI2 P0TXCM 28 81 CEC4 47K 10 HDMI_0_CLK- TMDS_CLK+ 3 6 1/16W D0-_HDMI2 P0EXT_SWING 29 80 RX0SCL 9 TMDS_DATA0- 4 5 D0+_HDMI2 CH0ABCLK 30 79 RX0SDA 8 TMDS_DATA0_SHIELD 9 OPT CH0ALRCLK 31 78 RX1SCL 7 DDC_SCL_3 TMDS_DATA0+ CH0ASD3 32 77 RX1SDA 6 DDC_SDA_3 TMDS_DATA1- CH0ASD2 33 76 RX2SCL 5 DDC_SCL_2 TMDS_DATA1_SHIELD D3205 CH0ASD1 34 75 RX2SDA 4 DDC_SDA_2 TMDS_DATA1+ RCLAMP0544T.TCT CH0ASD0 RX3SCL 3 6.5VTO11.0V 35 74 DDC_SCL_1 TMDS_DATA2- 1 8 VDD11_2 36 73 RX3SDA 2 D1-_HDMI2 DDC_SDA_1 TMDS_DATA2_SHIELD 2 7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 D1+_HDMI2 TMDS_DATA2+ 3 6 D2-_HDMI2 S3200 4 5 RAC33437501 VDD33_2 NIRQA0 NIRQA1 TX1HPD TX0HPD NTEST PVDD33 NC[ANA_MON2] AVDDH33_1 P3RXCM P3RXCP AVDD11_5 P3RX0M P3RX0P AVDD11_6 P3RX1M P3RX1P P3RX2M P3RX2P P2RXCM P2RXCP AVDD11_7 P2RX0M P2RX0P AVDD11_8 P2RX1M P2RX1P P2RX2M P2RX2P AVDDH33_2 VDD11_3 NC[VDDQ] RX2P5V VDD33_3 RX1P5V RX0P5V 05008WR-H19C. D2+_HDMI2 JK3200 9 OPT S3201 HDMI2 with ARC RAC33437501 R3297 120K SPI_CS_R9531 X3201 AR3208 DVDD10_R9531 SPI_DI_R9531 S3202 33 SPI_DO_R9531 27MHz RAC33437501 X-TAL_1 GND_2 CK-_HDMI1 R9531_XTAL_IN D2+_HDMI1 CK+_HDMI1 1 4 D0-_HDMI1 D0+_HDMI1 D1-_HDMI1 D1+_HDMI1 D2-_HDMI1 GND_1 X-TAL_2 5V_HDMI_3 C3267 2 3 R9531_XTAL_OUT S3203 AVDD33_R9531 CVDD10_R9531 DVDD10_R9531 18pF RAC33437501 50V C3270 R3219 18pF VA3202 1K R3220 50V ESD_HDMI C 4.7K P_PVDD33 S3204 R3245 HDMI_INT_EDID RAC33437501 Q3201 B 1K HDMI_HPD_3 +1.1V_VDD_D14 +1.1V_VDD_D14 P_AVDDH11 SDI_GPIO11 SDO_GPIO10 MMBT3904(NXP) RSVDNC_36 RSVDNC_35 RSVDNC_34 RSVDNC_33 RSVDNC_32 RSVDNC_31 RSVDNC_30 RSVDNC_29 RSVDNC_28 BODY_SHIELD R3203 SS_GPIO8 ARCRX_TX CVDD10_3 100K E R3248 L3205 IOVCC33 TDVDD10 TPVDD10 20 4.7K BLM18PG121SN1D ESD_HDMI VA3206 HDMI_EXT_EDID T0X2+ T0X2- T0X1+ T0X1- T0X0+ T0X0- T0XC+ T0XC- 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF [EP] 19 P_VDD33 Solder Preform HOT_PLUG_DETECT 18 C3272 C3202 C3264 5V_HDMI_3 5V_HDMI_4 Attach at R9531 thermal pad AR3205 22uF 0.33uF VDD[+5V] 33 4.7uF 5V_HDMI_2 10V Test2_ANA_MON2 C3226 C3253 C3222 C3224 C3227 C3254 C3255 C3256 17 1/16W 10V DDC/CEC_GND R3236 R3238 R3240 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 OPT OPT OPT OPT OPT OPT OPT OPT DDC_SDA_3 R3231 0 0 0 16 R3204 SDA DDC_SCL_3 10K HDMI_Damping0ohm HDMI_Damping0ohm HDMI_Damping0ohm 33 SCLK_GPIO9 1 75 XTALGND 15 SPI_CK_R9531 SCL R3237 R3239 R3242 GPIO5 XTALIN VA3210 VA3213 47K 47K 2 74 R9531_XTAL_IN 14 ESD_HDMI ESD_HDMI 47K THERMAL RESERVED +1.1V_VDD_D14 P_VDD11 +1.1V_VDD_D14 P_AVDD11 SD0_IN_SPDIF0_IN 3 73 XTALOUT 13 CEC_REMOTE R3236-*1 R3238-*1 101 R9531_XTAL_OUT R3240-*1 CEC 10 10 10 GPIO6 4 72 XTALVCC33 XTAL_VCC33_R9531 CK+_HDMI1 D0-_HDMI1 CK-_HDMI1 D0+_HDMI1 D1-_HDMI1 D1+_HDMI1 D2-_HDMI1 D2+_HDMI1 L3200 L3203 CK-_HDMI2 CK+_HDMI2 D0-_HDMI2 D0+_HDMI2 D1-_HDMI2 D1+_HDMI2 D2-_HDMI2 D2+_HDMI2 12 TMDS_CLK- D3206 BLM18PG121SN1D BLM18PG121SN1D HDMI_Damping10ohm HDMI_Damping10ohm HDMI_Damping10ohm RSVDL_1 APLL10 5 71 APLL10_R9531 RCLAMP0544T.TCT 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 11 4.7uF TMDS_CLK_SHIELD R0XC- RSVD_9 +5V_NORMAL 6.5VTO11.0V CK-_HDMI1_R9531 6 70 10 R3257 5.1 TMDS_CLK+ 1 8 R0XC+ TX_HPD0 4.7K R3284 CK-_HDMI3 C3263 CK+_HDMI1_R9531 7 69 9 4.7uF TMDS_DATA0- 2 7 HDMI1 HDMI2 R3263 5.1 R0X0- TX_DSCL0 4.7K R3285 8 IC3202 68 C3204 C3228 C3229 C3208 C3248 C3250 C3251 C3252 C3259 CK+_HDMI3 10V D0-_HDMI1_R9531 OPT OPT OPT OPT OPT OPT 8 R3264 5.1 OPT OPT TMDS_DATA0_SHIELD 3 6 R0X0+ TX_DSDA0 1.8K R3293 D0-_HDMI3 D0+_HDMI1_R9531 9 67 7 TMDS_DATA0+ 4 5 R3273 5.1 R0X1- RSVDNC_27 1.8K R3296 D0+_HDMI3 10 66 6 5 TMDS_DATA1- 9 OPT D1-_HDMI1_R9531 D1+_HDMI1_R9531 R3274 5.1 R3276 5.1 R0X1+ 11 R9531AN 65 RSVDNC_26 R3912 0 DDC_SDA_1 DDC_SCL_1 TMDS_DATA1_SHIELD R0X2- 12 64 RSVD_8 R3913 0 4 D3207 HDMI_3.3V P_VDD33 HDMI_3.3V P_AVDD33 D2-_HDMI1_R9531 R3277 5.1 TMDS_DATA1+ RCLAMP0544T.TCT R0X2+ 13 63 RSVD_7 4.7K R3286 3 D2+_HDMI1_R9531 R3299 5.1 TMDS_DATA2- 6.5VTO11.0V L3201 R3214 CVDD10_1 14 62 RSVD_6 4.7K R3287 2 1 8 BLM18PG121SN1D 0 CVDD10_R9531 TMDS_DATA2_SHIELD D1-_HDMI3 AVDD10_1 15 61 RSVDNC_25 AVDD33_R9531 0.33uF 0.33uF 0.33uF 0.33uF 0.33uF 2 7 DVDD10_R9531 3.3V Power Separation 0.1uF 0.1uF 4.7uF 4.7uF 1 TMDS_DATA2+ D1+_HDMI3 AVDD33_1 RSVD_5 3 6 AVDD33_R9531 16 60 D2-_HDMI3 +3.3V_NORMAL +5V_NORMAL HDMI_3.3V RSVDNC_1 17 59 RSVD_4 4.7K R3288 4 5 C3206 C3205 C3207 C3216 C3212 C3215 C3217 C3258 C3265 05008WR-H19C. D2+_HDMI3 RSVDNC_2 18 58 RSVD_3 4.7K R3290 JK3201 R3208 9 OPT RSVDNC_3 RSVDNC_24 19 57 HDMI3 10K RSVDNC_4 20 56 RSVD_2 RSVDNC_5 RSVD_1 4.7K R3291 G 21 55 HDMI_3.3V HDMI_3.3V P_AVDDH33 P_PVDD33 RSVDNC_6 22 54 CSDA 4.7K R3292 I2C_SDA2 S D RSVDNC_7 23 53 CSCL L3204 R3221 AO3438 I2C_SCL2 ADLC 5S 02 015 BLM18PG121SN1D 0 C3269 Q3204 RSVDNC_8 RSVDL_2 C3268 24 52 +5V_NORMAL 22uF C3235 0.33uF 100uF C3261 0.33uF C3230 0.33uF C3231 0.33uF 0.1uF 0.1uF 0.1uF 4.7uF C32610 0.1uF 6.3V 10V 10uF RSVDNC_9 SBVCC5V HDMI_HPD_4_MHL 10V 25 51 ADLC 5S 02 015 OPT VA3200 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C3273 C3274 C3221 C3260 C3223 C3225 C3232 5V_HDMI_4 10uF 0.1uF 10V 16V BODY_SHIELD RSVDNC_10 RSVDNC_11 RSVDNC_12 RSVDNC_13 RSVDNC_14 RSVDNC_15 CVDD10_2 AVDD10_2 AVDD33_2 RSVDNC_16 RSVDNC_17 RSVDNC_18 RSVDNC_19 RSVDNC_20 RSVDNC_21 RSVDNC_22 RSVDNC_23 RESET_N CI2CA_TPWR INT DSDA0 DSCL0 CBUS_HPD0 R0PWR5V VCC33_OUT 20 VA3211 4th layer PWRMUX_OUT 19 HOT_PLUG_DETECT 18 AR3206 VDD[+5V] 10K 33 4.7K 17 1/16W DDC pull-up R9531_RESET DDC/CEC_GND DDC_SDA_MHL C3276 C3277 16 HDMI_3.3V 10uF 0.1uF DDC_SDA_1_R9531 DDC_SCL_1_R9531 R3283 R3282 HDMI_HPD_1 SDA DDC_SCL_MHL S 10V 16V 15 +5V_NORMAL +5V_NORMAL Q3202 SCL VA3215 D3200 5V_HDMI_2 +5V_NORMAL +5V_NORMAL +3.5V_ST PWRMUX_OUT CVDD10_R9531 DVDD10_R9531 AVDD33_R9531 5V_HDMI_1 5V_HDMI_3 SI1012CR-T1-GE3 14 ESD_HDMI IP4294CZ10-TBR 5V_HDMI_4 G RESERVED VA3212 AVDD33_R9531 CEC_REMOTE D R3252 13 ESD_HDMI 10K R3254 1 10 A1 A2 A1 A2 A1 A2 A1 A2 CEC A1 A2 10 CK-_HDMI4_JACK 5V_HDMI_1 12 MMBD6100 MMBD6100 MMBD6100 MMBD6100 MMBD6100 TMDS_CLK- 2 9 CK+_HDMI4_JACK D3218 D3208 D3219 D3209 D3210 C3275 R3253 11 5.1K C C C C 3 8 C TMDS_CLK_SHIELD 1uF 10 OPT TMDS_CLK+ 4 7 D0-_HDMI4_JACK 9 5 6 AR3201 AR3200 AR3202 AR3203 TMDS_DATA0- 1/16W 1/16W 1/16W 1/16W D0+_HDMI4_JACK +1.0V_R9531 8 CVDD10_R9531 HDMI_3.3V AVDD33_R9531 else : Max 0.7A 47K 47K 47K 47K TMDS_DATA0_SHIELD 7 6 TMDS_DATA0+ D3201 IP4294CZ10-TBR DDC_SDA_1_R9531 DDC_SDA_2 DDC_SDA_3 DDC_SCL_MHL R9531 +1.0V L3210 BLM18PG121SN1D L3215 BLM18PG121SN1D TMDS_DATA1- +1.0V_R9531 HDMI_3.3V IC3204 5 1 10 DDC_SCL_1_R9531 DDC_SCL_2 DDC_SCL_3 DDC_SDA_MHL C3246 C3279 C3284 C3289 C3292 C3294 C3298 C3299 C3271 TMDS_DATA1_SHIELD D1-_HDMI4_JACK AP2132MP-2.5TRG1 [EP] 10uF 10uF 0.1uF 0.1uF 10uF 10uF 0.1uF 0.1uF 0.1uF 4 2 9 10V 10V 16V 16V 10V 10V 16V 16V 16V 1.8K R3280 TMDS_DATA1+ D1+_HDMI4_JACK +3.5V_ST 3 3 8 TMDS_DATA2- OPT R3279 1 8 R2 SPI FLASH (2MBit) +3.3V_NORMAL 4 7 THERMAL 2 PG GND R3261 TMDS_DATA2_SHIELD D2-_HDMI4_JACK 5 6 10K IC3203 10K APLL10_R9531 XTAL_VCC33_R9531 R3281 1.2K 9 1 2 7 R1 L3213 TMDS_DATA2+ D2+_HDMI4_JACK C3243 L3207 BLM18PG121SN1D W25X20CLSNIG E MMBT3906(NXP) EN ADJ BLM18PG121SN1D C3239 R3262 0.1uF 10K Q3206 0.1uF 3 6 05008WR-H19C. C3290 C3293 CS VCC B VOUT 1 8 VIN C3244 C3282 10uF 0.1uF SPI_CS_R9531 R3278 JK3202 C3240 C C 0.1uF 2A 10uF 0.1uF 10V 16V 10K R3260 4 5 10V 16V R3275 C3281 1K 16V +5V_NORMAL 33 DO[IO1] HOLD B 2 7 MHL_DET VCTRL NC SPI_DO_R9531 1/16W Q3205 C3262 0.1uF EAN61387601 ZD3202 10uF R3232 HDMI4 with MHL C3234 5% MMBT3904(NXP) E (CD_SENCE) 2.5V WP CLK 180K 0.1uF 10V DVDD10_R9531 3 6 OPT R9531_FLASH_WP SPI_CK_R9531 16V L3211 OPT BLM18PG121SN1D C3241 GND DIO[IO0] R3259 4 5 120K 1uF SPI_DI_R9531 C3257 C3278 C3280 C3288 C3245 C3266 10uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF 10V 10V 16V 16V 16V 16V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES Vout=0.6*(1+R1/R2) SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 32 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

UB98/UC9 only TX1SDA TX1SCL TX0SDA TX0SCL HDMI0_DDC_DA HDMI1_DDC_DA +3.3V_NORMAL +3.3V_MUX HDMI1_DDC_CK HDMI0_DDC_CK TI 2:1 Mux L13413 BLM18PG121SN1D +3.3V_MUX PS8407 [EP]GND +3.3V_MUX [EP]GND C3314 SDA_B SCL_B SDA_A SCL_A +1.2V_PS8401 +3.3V_PS8401 +1.2V_PS8401 ISET 22uF IC3501 SDA_B SCL_B SDA_A SCL_A IC3302 10V IC3502 TS3DV642A0RUAR R3505 +3.3V_MUX +3.3V_NORMAL +1.2V 3.3K TS3DV642A0RUAR AZ1117EH-1.2TRG1 R3318 +3.3V_MUX 3.3K 39 40 41 42 39 40 41 42 D0+A 38 1 VCC D0+A 38 1 VCC IN 3 2 OUT HDMI1_TX2P D0-A 37 2 EN C3503 C3502 THERMAL D0-A 37 2 EN From D13 HDMI0_TX2P C3301 C3300 HDMI1_TX2N D1+A SCL 0.1uF 10uF R3521 THERMAL 10uF 36 3 16V 10V 1 D1+A SCL 0.1uF RXASCL_U14 1 43 HDMI0_TX2N 36 3 HDMI1_TX1P D1-A SDA RXBSCL_U14 16V 10V 35 4 C3505 C3506 C3507 ZD3500 43 HDMI0_TX1P D1-A SDA RXASDA_U14 0.1uF 0.1uF 0.1uF ADJ/GND 2.5V 35 4 HDMI1_TX1N D2+A D0+ 16V RXBSDA_U14 34 5 HDMI_RX2+_U14_2 16V 16V HDMI0_TX1N D2+A D0+ HDMI1_TX0P OPT 34 5 HDMI_Splitter_RX2+ D2-A D0- HDMI_RX2-_U14_2 HDMI0_TX0P HDMI1_TX0N 33 6 C3512 C3513 D2-A 33 6 D0- HDMI_Splitter_RX2- HDMI_RX1+_U14_2 HDMI0_TX0N D3+A 32 7 D1+ 10uF 10uF D3+A D1+ HDMI1_TXCP 10V 10V HDMI_Splitter_RX1+ HDMI_RX1-_U14_2 [EP]GND VDDRX_2 SDA_SRC SCL_SRC VDD33_2 SDA_SNK SCL_SNK VDDTX_2 HDMI0_TXCP 32 7 D3-A D1- 31 8 HDMI_RX0+_U14_2 GND_2 HDMI0_TXCN D3-A D1- HDMI_Splitter_RX1- HDMI1_TXCN 31 8 ISET NC_2 30 9 NC_1 NC_2 NC_1 HDMI_Splitter_RX0+ HDMI_RX0-_U14_2 PD 30 9 D0+B D2+ +3.3V_NORMAL +1.2V HDMI_Splitter_RX0- 29 10 HDMI_CLK+_U14_2 +3.3V_PS8401 +1.2V_PS8401 HDMI_0_RX2+ D0+B 29 10 D2+ HDMI_Splitter_CLK+ D0-B D2- HDMI_CLK-_U14_2 +5V_NORMAL From MN864778 40 39 38 37 36 35 34 33 32 31 HDMI_1_RX2+ 28 11 HDMI_0_RX2- D0-B 28 11 D2- HDMI_Splitter_CLK- HDMI_1_RX2- B1+B 27 12 D3+ +3.3V_NORMAL HDMI_RX2+_U14_1 IN_D2P 1 30 OUT_D2P RP_HDMI_D2+ HDMI_0_RX1+ B1+B D3+ C3307 L3500 L3501 27 12 +3.3V_NORMAL B1-B D3- IN_D2N 2 29 OUT_D2N 10uF 120-ohm C3504 C3508 HDMI_0_RX1- HDMI_1_RX1+ 26 13 HDMI_RX2-_U14_1 THERMAL RP_HDMI_D2- 120-ohm 0.1uF 0.1uF R3509 B1-B D3- R3500 1K HPD_SRC 3 28 HPD_SNK R3518 1K 10V HDMI_0_RX0+ 26 13 HDMI_1_RX1- D2+B HPD 41 +3.3V_PS8401 25 14 10K OPT IN_D1P OUT_D1P R3319 D2+B 25 14 HPD HDMI_1_RX0+ HDMI_RX1+_U14_1 4 27 RP_HDMI_D1+ 10K HDMI_0_RX0- D2-B 24 15 CEC IN_D1N OUT_D1N D2-B CEC HDMI_1_RX0- HDMI_RX1-_U14_1 5 IC3500 26 RP_HDMI_D1- HDMI_0_CLK+ 24 15 D3+B SEL1 IN_D0P OUT_D0P HDMI_1_CLK+ 23 16 HDMI_RX0+_U14_1 6 PS8401A 25 RP_HDMI_D0+ HDMI_0_CLK- D3+B 23 16 SEL1 HDMI_1_CLK- D3-B 22 17 SEL2 HDMI_RX0-_U14_1 IN_D0N 7 24 OUT_D0N RP_HDMI_D0- D3-B 22 17 SEL2 I2C_CTL_EN 8 23 CFG/I2C_ADDR1 I2C_CTL_EN CFG/I2C_ADDR1 21 20 19 18 HDMI_MUX_SEL IN_CKP OUT_CKP R3501 R3506 R3508 R3512 R3514 R3516 9 22 R3519 21 20 19 18 HDMI_CLK+_U14_1 RP_HDMI_CK+ 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K HDMI_MUX_SEL IN_CKN OUT_CKN 4.7K HDMI_CLK-_U14_1 10 21 OPT OPT OPT OPT OPT RP_HDMI_CK- OPT HPD_B CEC_B HPD_A CEC_A SEL2(GPIO30) Function I2C_CTL_EN 11 12 13 14 15 16 17 18 19 20 HPD_B CEC_B HPD_A CEC_A DDCBUF Low CH A (HEVC decoder) enable VDD33_1 VDDRX_1 DCIN_EN/SCL_CTL DDCBUF/SDA_CTL GND_1 PRE EQ/I2C_ADDR0 REXT VDDRA VDDTX_1 DCIN_EN High CH B (HDMI S/W) enable EQ/I2CADDR_0 R3511 4.99K PRE 1% ISET C3500 C3501 CFG/I2C_ADDR1 0.1uF 0.1uF 16V 16V C3511 0.1uF R3503 16V R3502 R3507 R3510 R3513 R3515 R3517 22 R3520 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K I2C_SCL2 C3509 OPT OPT 0.1uF I2C_SDA2 16V R3504 +1.2V_PS8401 +1.2V_PS8401 22 OPT PRE EQ/I2CADDR_0 +3.3V_PS8401 +1.2V_PS8401 +3.3V_NORMAL +3.3V_Pericom HDMI Splitter DCIN_EN DDCBUF L3300 HDMI OUTPUT to U14 BLM18PG121SN1D IC3300 : HDMI412AD(3.0Gbps) -> select HDMI_Splitter_AD option. HDMI_CLK-_U14_1 HDX412BD(3.4Gbps) -> select HDMI_Splitter_BD option. HDMI_CLK+_U14_1 C3302 C3303 C3304 C3305 C3306 C3309 C3310 C3311 EMP2/I2C_ADR3 EMP1/I2C_ADR2 C3312 SW2/I2C_ADR1 SW1/12C_ADR0 HDMI_RX0-_U14_1 22uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10V 10V 16V 16V 16V 16V 16V 16V 16V HDMI_RX0+_U14_1 [EP]GND VDD_10 GND_9 GND_8 HDMI_RX1-_U14_1 SEL1 D2P1 D2N1 D1P1 D1N1 OE DR HDMI_RX1+_U14_1 HDMI_RX2-_U14_1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 MS 1 42 VDD_9 HDMI_RX2+_U14_1 Splitter_TEST_IN VDD_1 THERMAL D0P1 +3.3V_NORMAL 2 41 GND_1 57 D0N1 +3.3V_Pericom 3 40 D2P 4 39 GND_7 D2N 5 38 CLKP1 HDMI_Splitter_BD HDMI_Splitter_BD VDD_2 CLKN1 SEL_IN 6 IC3300-*1 37 A3/S7 A2/S6 A1/S5 A0/S4 D1P 7 36 VDD_8 PI3HDX412BD R3325 10K R3302 10K 10K 10K R3308 10K R3310 10K R3312 10K R3314 10K R3316 10K R3320 10K OE D1N 8 35 D2P2 OPT OPT OPT OPT OPT OPT D0P HDMI_Splitter_BD D2N2 9 34 R3304 R3306 D0N 10 33 GND_6 VDD_3 11 32 D1P2 CLKP 12 31 D1N2 MS CLKN 13 30 VDD_7 GND_2 D0P2 +3.3V_Pericom 14 29 SEL_IN : S1 SEL_IN +3.3V_Pericom HDMI_Splitter_BD 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OE [EP]GND TEST_IN SEL_IN GND_11 GND_10 VDD_4 SEL_OUT ROUT_SEL VDD18 EQ2/SCL_CTL SQ1/SDA_CTL GND_3 VDD_5 GND_4 VDD_6 CLKN2 CLKP2 GND_5 D0N2 A3/S7 A2/S6 A1/S5 A0/S4 VDD_8 D0+A D0-A D1+A D1-A Splitter_TEST_IN R3343 0 C13455 OE 0.1uF HDMI_Splitter_BD A3/S7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 R3342 A2/S6 MS MS 1 42 GND_9 0 VDD_1 2 THERMAL 41 D2+A HDMI_Splitter_AD A1/S5 GND_1 57 D2-A 3 40 HDMI_Splitter_CLK- A0/S4 D0+ 4 39 GND_8 HDMI_Splitter_CLK+ D0- D3+A HDMI_Splitter_AD 5 38 S3 R3323 0 HDMI_Splitter_RX0- VDD_2 6 37 D3-A IC3300 HDMI_Splitter_AD D1+ VDD_7 S2 HDMI_Splitter_AD HDMI_Splitter_AD HDMI_Splitter_RX0+ 7 PI3HDMI412ADZBE 36 R3324 0 HDMI OUTPUT to H13 D1- D0+B 10K 10K 10K 10K 10K 10K 10K 8 35 HDMI_CLK- 10K 10K HDMI_Splitter_BD HDMI_Splitter_RX1- D2+ HDMI_Splitter_AD D0-B I2C_SCL5 0 9 34 R3300 HDMI_CLK+ OPT HDMI_Splitter_RX1+ D2- 10 33 GND_7 HDMI_Splitter_BD R3307 R3309 R3311 R3313 R3315 R3317 R3321 I2C_SDA5 R3301 R3303 HDMI_RX0- R3322 0 HDMI_Splitter_RX2- VDD_3 11 32 D1+B D3+ D1-B HDMI_RX0+ HDMI_Splitter_RX2+ 12 31 R3344 D3- GND_6 0 HDMI_RX1- 13 30 GND_2 D2+B HDMI_Splitter_AD MS : MODE SEL, 1:I2C control, 0:Pin control 14 29 HDMI_RX1+ +3.3V_Pericom SEL_IN : OUTPUT port SEL HDMI_RX2- 15 16 17 18 19 20 21 22 23 24 25 26 27 28 R3345 0 HDMI_RX2+ OE : OUPUT Enable C13456 HDMI_Splitter_BD VDD_4 SEL_OUT 1K TEST_OUT NC SCL/S3 SDA/S2 GND_3 VDD_5 GND_4 VDD_6 D3-B D3+B GND_5 D2-B 0.1uF HDMI_Splitter_BD TEST_IN : 1:splitter mode, 0:demux mode 4.7uF HDMI_Splitter_BD R3305 C3313 HDMI_Splitter_BD S3 S2 VDDC15_M0 VDDC15_M1 H13 DDR VDD Decap D14 DDR VDD Decap (For EMI) 4Layer 4Layer VDDC15_D14 +1.5V_U_DDR URSA9 DDR VDD Decap (For EMI) 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF 4Layer 330pF 330pF 330pF 330pF 330pF 330pF 330pF 330pF C3308 C3316 C3318 C3320 C3322 C3324 C3326 C3328 C3330 C3331 C3315 C3317 C3319 C3321 C3323 C3325 C3327 C3329 330pF 330pF 330pF 330pF 330pF 330pF C3332 C3333 C3334 C3335 C3336 C3337 C3338 C3339 OPT OPT OPT OPT OPT OPT OPT OPT C3340 C3341 C3342 C3343 C3344 C3345 OPT OPT OPT OPT OPT OPT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-033_01-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

JK3401 +3.3V_NORMAL JSTIB15 R3404 150 VIN HP_LOUT SPDIF OUT A 1/10W JK3403 Fiber Optic 5% +3.3V_NORMAL PEJ038-3B61 VCC GND 5 B R3406 R3400 HP_OUT 10K L 4 33 GND C HP_OUT SPDIF_OUT R3409 VA3400 C3400 100 DETECT 3 4 HP_DET C3402 5.5V 0.1uF 1/16W 47pF 16V SHIELD 5% R 1 50V OPT R3405 150 ADUC 5S 02 0R5L HP_ROUT EAG61030015 1/10W 5% VA3405 5.6V COMPONENT 1 PHONE JACK +3.3V_NORMAL CVBS 1 PHONE JACK OPT +3.3V_NORMAL C3401 18pF R3402 10K R3403 R3407 330K 100 R3408 COMP1_DET 100 1/16W AV1_CVBS_DET 5% 1/16W VA3401 C3403 5% VA3402 5.6V 5.6V 0.1uF 16V JK3400 JK3402 for audio Hum noise (L) PEJ038-3B6111 PEJ038-3B611 5 M5_GND 5 M5_GND 4 M4 COMP1_Y 4 M4 COMP1/AV1/DVI_L_IN 3 M3_DETECT 3 M3_DETECT VA3403 C3405 5.6V 0.01uF 1 M1 1 M1 25V 6 M6 6 M6 EAG61030017 EAG61030016 COMP1_Pb COMP1/AV1/DVI_R_IN VA3404 C3404 5.6V 0.01uF 25V COMP1_Pr AV1_CVBS_IN THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-034-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JACK HIGH/MID 2013.12.17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Place Near Micom +3.5V_ST AR4001 33 1/16W LOGO_LIGHT_WAFER 10K R4000 OPT LOGO_LIGHT C B LOGO_LIGHT LOGO_LIGHT 1K Q4000 LOGO_LIGHT R4002 R4001 C4000 MMBT3904(NXP) E LOGO_LIGHT 10K 0.1uF 16V +3.5V_WOL L4000 BLM18PG121SN1D C4011 C4010 C4004 3300pF 0.1uF 22uF 50V 10V +3.3V_NORMAL For EMI(ready) WIFI_DM RCLAMP0502BA RCLAMP0502BA WIFI_DP D4000 C4015 C4016 5pF 5pF 50V 50V R4014 L4002 10K 120-ohm M_REMOTE_RTS C4007 P13503 SMAW200-H28S5K MAX 0.4A M_REMOTE_RX 0.1uF GND 1 2 +3.5V_WOL M_REMOTE_TX WOL/WIFI_POWER_ON WOL 3 4 DN RCLAMP0582B GND 5 6 DP D4000-*1 NC 7 8 +3.3V_NORMAL R13430 RCLAMP0582B GND 9 10 RTS C4012 C4013 C4014 100 CTS UART_RX_RF 1000pF47pF 47pF 11 12 M_REMOTE_CTS RESET 13 14 UART_TX_RF 50V 50V 50V AR4000 R13429 100 GND KEY2 15 17 16 18 KEY1 +3.5V_ST 100 M_RFModule_RESET For EMI GND IR 19 20 LOGO GND 1/16W 21 22 EYE_SCL 23 24 EYE_SDA OPT OPT NC 25 26 NC C4008 C4009 47pF 47pF NC 27 28 NC 50V 50V For EMI 29 +3.5V_ST L4001 BLM18PG121SN1D R4010 C4005 1000pF 100 50V EYE_SDA EYE_Q VA4003 ADMC 5M 02 200L OPT R4011 100 EYE_SCL EYE_Q VA4004 ADMC 5M 02 200L R4016 0 LOGO_LIGHT_WAFER OPT +3.5V_ST +3.5V_ST R4005 R4009 R4008 10K 10K 10K 5% 5% 5% R4006 NON_OLED NON_OLED 100 IR KEY1 VA4002 VA4001 C4006 5.6V 100pF 5.6V C4001 50V AMOTECH CO., LTD. AMOTECH CO., LTD. 0.1uF R4007 100 KEY2 C4002 VA4000 0.1uF 5.6V AMOTECH CO., LTD. THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H040-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS IR / KEY 2014.01.28 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

UB98/D9 only From HUB USB_Camera P4200 3510-56216 +3.3V_NORMAL CAM_SLIDE_DET 1 To SoC CAM_TRIGGER_DET 2 C4202 C4203 4.7uF 3 0.1uF 10K R4218 OPT10K R4219 CAMERA_DM 4 R4216 PSELF R4215100K 100K CAMERA_DP 5 RCLAMP0502BA [EP]GND OVCUR1 OVCUR2 D4200 PGANG RCLAMP0502BA 6 V33 SDA V5 +3.3V_NORMAL 7 28 27 26 25 24 23 22 I2S_WOOFER DM0 1 21 DVDD HUB_DM THERMAL C4208 8 R4217 1/16W DP0 2 20 OVCUR3 HUB_DP 29 AUD_SCK 0.1uF RCLAMP0502BA 10K 5% 0 R4200 DM1 OVCUR4 D4201 USB_DM3 3 19 9 +3.3V_NORMAL 0 R4201 DP1 IC4200 TEST/SCL AUD_LRCK RCLAMP0502BA USB_DP3 4 18 L4200 GL852G-31 120-ohm AVDD_1 RESET 10 5 17 /RST_HUB C4200 I2S_AMP BLM18PG121SN1D DM2 DP4 0 R4202 RCLAMP0502BA 6 16 USB_DP2 D4202 C4201 C4209 11 1uF 0 R4203 RCLAMP0502BA 0.1uF DP2 7 15 DM4 0.1uF 25V USB_DM2 10 11 12 13 14 8 9 12 RREF AVDD_2 X1 X2 DM3 DP3 AVDD_3 +3.5V_CAM 13 R4214 C4226 1% 680 4.7uF 10V CAM_PWR_ON_CMD 14 C4205 C4206 From Micom CAM_RESET 15 0.1uF 0.1uF CAM_SLEEP 16 X4200 17 12MHZ X-TAL_1 GND_2 1 4 GND_1 X-TAL_2 RCLAMP0582B RCLAMP0582B RCLAMP0582B C4207 2 3 D4200-*1 D4201-*1 D4202-*1 22pF C4204 22pF RCLAMP0582B RCLAMP0582B RCLAMP0582B Camera Power CNT CAMERA POWER ENABLE CONTROL P4201 12507WR-04L +3.5V_CAM +3.5V_ST IC4201 AP2191WG-7 +3.5V_CAM 1 IN OUT 5 1 2 C4225 GND 0.1uF 2 3 C4210 4.7uF CAM_CTL EN FLG 10V 4 3 4 5 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-042-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS USB3_HUB 2013.12.17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

OCP USB1 +5V_USB_2 USB3 (2.0) +5V_USB_3 USB2 (2.0) +5V_USB_1 MAX 1.0A MAX 1.0A +3.3V_NORMAL +5V_NORMAL 3AU04S-385-ZC-(LG). 3AU04S-385-ZC-(LG). IC4400 JK4302 JK4300 BD2242G 1 1 USB DOWN STREAM USB DOWN STREAM R4401 VIN VOUT 4.7K 1 6 2 2 USB_DM2 USB_DM3 C4401 GND ILIM RCLAMP0502BA 0.1uF 2 5 3 3 16V USB_DP2 USB_DP3 14K R4402 1% RCLAMP0502BA EN OC RCLAMP0502BA RCLAMP0502BA /USB_OCD1 3 4 C4414 C4322 ZD4300 D4300 D4302 5V C4416 C4310 4 4 22uF 10uF ZD4302 22uF 10uF 5V 10V 5 5 10V OPT USB_CTL1 10V 10V OPT R4400 10K RCLAMP0582B RCLAMP0582B D4302-*1 D4300-*1 RCLAMP0582B RCLAMP0582B USB3_3.3V R4410 R4414 R4412 R4416 OPT 4.7K OPT 4.7K OPT 4.7K OPT 4.7K R4411 USB3_EN R4413 R4415 R4417 4.7K OPT 4.7K OPT 4.7K OPT 4.7K USB3.0 redriver IC EQ setting -> EQ2: Low / DE1: Low USB3_3.3V +5V_USB_1 EN_RXD VCC_2 NC_5 OS1 DE1 EQ1 USB1 (3.0) 18 17 16 SN65LVPE502A 15 14 13 USB3_TX0P HOST_RX1- 19 12 NC_4 C4413 0.1uF MAX 1.2A USB3_TX0M ZD4301 20 11 5V IC4402 HOST_RX1+ DEVICE_TX1- C4415 C4402 22uF 10uF JK4400 C4409 OPT 21 10 0.1uF 0.1uF GND_2 DEVICE_TX1+ 10V 10V PC2R009NJA1. C4412 OPT USB3_RX0P 22 9 THERMAL HOST_TX2- GND_1 25 USB3_RX0M 23 8 VBUS C4407 HOST_TX2+ DEVICE_RX2- 1 0.1uF 24 7 NC_6 DEVICE_RX2+ R4408 D- 1 2 3 4 5 6 0 2 [EP]GND USB3_3.3V USB3_DM NC_1 NC_2 VCC_1 DE2 EQ2 NC_3 R4409 0 D+ USB3_DP 3 OPT OPT USB REDRIVER POWER ENABLE CONTROL USB3_3.3V GND R4404 R4406 4 4.7K 4.7K Non_USB3.0_REDRIVER_PWR_CTL L4400 STDA_SSRX- BLM18PG121SN1D 5 +3.3V_NORMAL IC4401 USB3_3.3V STDA_SSRX+ 4.7K OPT AP2191WG-7 6 USB3.0_REDRIVER_PWR_CTL R4405 R4407 4.7K GND_DRAIN IN OUT 7 5 1 USB3.0_REDRIVER_PWR_CTL C4417 STDA_SSTX- USB3.0_REDRIVER_PWR_CTL GND USB3_3.3V 8 0.1uF 2 USB3_3.3V STDA_SSTX+ EN FLG 9 USB3_EN 4 3 RCLAMP0502BA RCLAMP0502BA RCLAMP0502BA RCLAMP0502BA C4400 C4403 C4404 C4405 10K RCLAMP0502BA RCLAMP0502BA 10 R4403 RCLAMP0582B RCLAMP0582B RCLAMP0582B C4406 C4408 C4410 C4411 RCLAMP0582B RCLAMP0582B RCLAMP0582B 1uF 1uF 0.1uF 0.01uF D4400 D4402 1uF 1uF 0.1uF 0.01uF D4401 D4400-*1 D4401-*1 D4402-*1 SHIELD Place under DUT Near SN65LVPE502CP PIN VCC THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-044-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR USB JACK THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

+3.3V_NORMAL EU R4801 Full Scart(18 Pin Gender) 10K CLOSE TO JUNCTION EU R4802 100 SC_DET EU 1/16W C4804 5% VA4801 5.6V 0.1uF EU SC_CVBS_IN VA4807 SHIELD 5.5V EU 19 AV_DET 75 R4800 18 COM_GND EU VA4808 DTV/MNT_V_OUT 17 5.5V SYNC_IN OPT 16 SYNC_OUT 15 SYNC_GND 14 RGB_IO 13 SC_FB R_OUT VA4802 12 5.6V R_GND EU 11 G_OUT 10 G_GND 9 SC_R ID 8 VA4803 B_OUT 5.5V 7 AUDIO_L_IN EU 6 B_GND 5 SC_G AUDIO_GND 4 VA4804 AUDIO_L_OUT 5.5V 3 AUDIO_R_IN EU 2 AUDIO_R_OUT 1 SC_B VA4805 5.5V DA1R018H91E EU JK4800 EU SC_ID SC_L_IN VA4800 VA4809 5.6V 20V EU EU SC_R_IN VA4806 5.6V EU BLM18PG121SN1D L4800 DTV/MNT_L_OUT EU EU EU C4800 C4802 1000pF 4700pF 50V BLM18PG121SN1D L4801 DTV/MNT_R_OUT EU EU EU C4803 C4801 4700pF 1000pF 50V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-048-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART GENDER Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Ethernet Block LAN_JACK_POWER C5100 C5101 C5102 C5103 0.1uF 0.01uF 0.1uF 0.01uF 16V 50V 16V 50V JK5100 BS-R570098 LAN_UDE P1[CT] 1 P2[TD+] 2 EPHY_TDP P3[TD-] 3 EPHY_TDN P4[RD+] 4 EPHY_RDP P5[RD-] 5 EPHY_RDN P6[CT] VA5100 VA5101 VA5102 VA5103 6 5.5V 5.5V 5.5V 5.5V P7 7 P8 8 9 9 EMI R5100 P10[GND] 0 10 P11 11 YL_C D1 YL_A D2 GN_C D3 GN_A D4 12 SHIELD JK5100-*1 TLA-6T764 LAN_TDK R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 R8 8 R9 9 R10[GND] 10 R11 11 YL_C D1 YL_A D2 GN_C D3 GN_A D4 12 SHIELD THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-051-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LAN_VERTICAL 2012.12.17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 51 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Ethernet Block +3.5V_WOL 3.3K R5215 EPHY_ACTIVITY ET_RXER R5217 3.3K LAN_JACK_POWER Place this cap. near IC +3.5V_WOL C5208 ET_COL/SNI 0.1uF ZD5201 C5200 C5201 C5203 16V 5V 4.7uF 0.1uF 0.1uF 16V 16V OPT 10V EPHY_ACTIVITY EPHY_CRS_DV Place 0.1uF close to each power pins ET_COL/SNI ET_RXER XTAL_1 GND_1 C5206 8pF +3.5V_WOL 50V 1M R5202 R5218 2 1 25MHz X5200 R5210 0 OPT 3 4 XTAL_2 GND_2 33 +3.5V_WOL LED1/PHYAD[1] Place this cap. near IC C5207 CRS/CRS_DV DVDD10OUT RXER/FXEN 8pF AVDD33_2 CKXTAL2 CKXTAL1 50V R5212 1/16W R5219 1/16W R5205 [EP] 3.3K 1.5K C5205 COL 10K Place this Res. near IC 1% 5% 0.1uF 16V 32 31 30 29 28 27 26 25 R5204 2.49K 1% WOL/ETH_POWER_ON RSET 1 24 LED0/PHYAD[0]/PMEB THERMAL AVDD10OUT 2 33 23 MDIO EPHY_MDIO Route Single 50 Ohm, Differential 100 Ohm MDI+[0] MDC 3 22 EPHY_MDC EPHY_RDP MDI-[0] IC5200 PHYRSTB 4 21 /RST_PHY (from SOC) EPHY_RDN RTL8201F-VB-CG MDI+[1] 5 20 TXEN EPHY_TDP EPHY_EN +3.5V_WOL MDI-[1] 6 19 TXD[3] EPHY_TDN C5212 AVDD33_1 TXD[2] 0.1uF 7 18 OPT R5203 RXDV TXD[1] 8 17 EPHY_TXD1 3.3K 10 11 12 13 14 15 16 9 RXD[0] RXD[1] 33 RXD[2]/INTB RXD[3]/CLK_CTL RXC DVDD33 TXC TXD[0] +3.5V_WOL +3.5V_WOL AR5200 R5200 3.3K C5211 OPT 0.1uF C5209 R5201 16V 33 R5209 33pF 51 EPHY_TXD0 C5202 3.3K EPHY_RXD1 EPHY_RXD0 EPHY_INT Place near IC 5pF R5208 WOL POWER ENABLE CONTROL EPHY_REFCLK +3.5V_WOL +3.5V_ST IC5201 AP2191WG-7 IN OUT 5 1 C5204 0.1uF GND 2 WOL_CTL R5211 33 EN FLG 4 3 R5213 10K OPT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-052-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013-12-17 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETHERNET Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Front speaker(EC97 Only) +3.3V_NORMAL R5613 AMP_RESET_N 100 L5602 L5601 C5627 R5614 10.0uH 1/16W 1000pF BLM18PG121SN1D 4.7K SPK_L+ 50V AUD_MASTER_CLK NRS6045T100MMGK 50V +24V_AMP 22000pF R5605 C5606 5.6 +24V +24V_AMP 1/10W R5609 C5626 C5620 C5605 0.1uF 4.7K 50V [EP]GND 10uF C5614 L5600 0.1uF C5608 C5624 390pF VDD_IO GND_IO PGND1A PVDD1A PVDD1B UBW2012-121F 10V 0.1uF 50V 16V 10uF 50V CLK_I RESET BST1A OUT1A 35V C5618 0.47uF 50V AD C5615 390pF 50V C5621 R5610 R5606 5.6 0.1uF 50V 4.7K SPEAKER_L 40 39 38 37 36 35 34 33 32 31 1/10W L5605 NC_1 1 30 OUT1B 10.0uH SPK_L- NRS6045T100MMGK VDD_PLL 2 29 PGND1B C5610 THERMAL 22000pF NC_2 3 41 28 BST1B 50V C5603 1uF 10V GND 4 27 VDR1 NC_3 5 IC5600 26 NC_4 C5604 1uF 10V DVDD 6 NTP7514 25 AGND AUD_LRCH SDATA 7 24 VDR2 From DACLRCH WCK 0x54 BST2A C5612 1uF C5613 1uF AUD_LRCK 8 23 10V 10V AUD_SCK BCK 9 22 PGND2A C5611 22000pF R5602 I2C_SDA2 100 SDA 10 21 OUT2A 50V R5603 100 11 12 13 14 15 16 17 18 19 20 I2C_SCL2 C5601 C5602 33pF 33pF L5603 50V 50V 10.0uH SCL FAULT MONITOR_0 MONITOR_1 MONITOR_2 BST2B PGND2B OUT2B PVDD2B PVDD2A SPK_R+ NRS6045T100MMGK +3.3V_NORMAL +24V_AMP R5607 5.6 1/10W C5622 R5611 R5601 0.1uF 4.7K 10K C5616 C5619 50V C5625 390pF 0.47uF R5604 C5609 0.1uF 50V 50V 50V SPEAKER_R 10uF C5617 C 100 390pF 35V 50V R5600 C5600 C5623 R5612 B Q5600 C5607 AMP_MUTE 1000pF 0.1uF 4.7K MMBT3904(NXP) R5608 10K 50V 22000pF 5.6 50V L5604 E 50V 1/10W 10.0uH I2S_AMP SPK_R- NRS6045T100MMGK WOOFER_MUTE SPK_L+ 8 SPK_L- 7 SPK_R+ 6 SPK_R- 5 W_SPK_L+ 4 W_SPK_L- 3 W_SPK_R+ 2 W_SPK_R- 1 SMAW250-08 P5600 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

---

Woofer speaker(EC97 ONLY) +3.3V_NORMAL +3.3V_NORMAL R5812 AMP_RESET_N 100 R5813 4.7K L5801 C5826 L5802 1/16W 1000pF 10.0uH BLM18PG121SN1D W_SPK_L+ 50V 4.7K R5810 NRS6045T100MMGK AUD_MASTER_CLK 50V +24V_AMP_HEIGHT PGND1A 22000pF R5802 C5805 5.6 +24V +24V_AMP_HEIGHT 1/10W R5806 C5825 C5819 C5804 0.1uF 4.7K 50V [EP]GND 10uF C5813 L5800 0.1uF C5807 C5823 390pF VDD_IO GND_IO PVDD1A PVDD1B UBW2012-121F 10V 0.1uF 50V 16V 10uF 50V CLK_I RESET BST1A OUT1A 35V C5817 0.47uF 50V AD C5814 390pF 50V C5820 R5807 R5803 0.1uF 50V 4.7K WOOFER_L 5.6 40 39 38 37 36 35 34 33 32 31 1/10W L5805 NC_1 1 30 OUT1B 10.0uH W_SPK_L- NRS6045T100MMGK VDD_PLL 2 29 PGND1B C5809 THERMAL 22000pF NC_2 3 41 28 BST1B 50V C5802 1uF 10V GND 4 27 VDR1 0 I2S_4CH NC_3 5 IC5800 26 NC_4 AUD_LRCH1 C5803 R5814 1uF 10V DVDD 6 NTP7514 25 AGND AUD_LRCH 0 I2S_2CH SDATA 7 24 VDR2 From DACLRCH R5815 WCK 0x56 BST2A C5811 1uF C5812 1uF AUD_LRCK 8 23 10V 10V AUD_SCK BCK 9 22 PGND2A C5810 22000pF R5800 I2C_SDA2