LG 49/55UF770

Internal Use Only North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com LED TV SERVICE MANUAL CHASSIS : LB59H / LB59J MODEL : 49/55UF770T/770V/770Y 49/55UF770T/770Y-TD 49/55UF770V-TZ CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL69324408 (1507-REV00) Printed in Korea

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CONTENTS CONTENTS ............................................................................................... 2 SAFETY PRECAUTIONS ......................................................................... 3 SERVICING PRECAUTIONS..................................................................... 4 SPECIFICATION........................................................................................ 6 ADJUSTMENT INSTRUCTION............................................................... 10 BLOCK DIAGRAM................................................................................... 17 EXPLODED VIEW ................................................................................... 34 SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX TROUBLE SHOOTING GUIDE.................................................. APPENDIX Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only Only for training and service purposes

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SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. General Guidance Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet. An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check. power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.) from electrical shocks. and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity. damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA. replace it with the specified. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer. over 1 W), keep the resistor 10 mm away from PCB. Leakage Current Hot Check circuit Keep wires away from high voltage or high temperature parts. Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only Only for training and service purposes

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SERVICING PRECAUTIONS CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo- NOTE: If unforeseen circumstances create conflict between the sure of the assembly. following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder on page 3 of this publication, always follow the safety precau- ES devices. tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol- der removal devices not classified as “anti-static” can generate General Servicing Precautions electrical charges sufficient to damage ES devices. 1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate source before; electrical charges sufficient to damage ES devices. a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective module or any other receiver assembly. package until immediately before you are ready to install it. b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec- or other electrical connection. trically shorted together by conductive foam, aluminum foil or c. Connecting a test substitute in parallel with an electrolytic comparable conductive material). capacitor in the receiver. 7. Immediately before removing the protective material from the CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate- installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will sion hazard. be installed. 2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir- high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions. FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace- Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the 3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your assemblies. foot from a carpeted floor can generate static electricity suf- 4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.) electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri- (by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F. Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed of contacts in not required. of 60 parts tin/40 parts lead. 5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned. receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire- 6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle. electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners. are correctly installed. 5. Use the following unsoldering technique 7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature. chassis ground before connecting the test receiver positive (500 °F to 600 °F) lead. b. Heat the component lead until the solder melts. Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction- 8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid. service manual. CAUTION: Work quickly to avoid overheating the circuit CAUTION: Do not connect the test fixture ground strap to any board printed foil. heat sink in this receiver. 6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature Electrostatically Sensitive (ES) Devices (500 °F to 600 °F) Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand ily by static electricity. Such components commonly are called against the component lead until the solder melts. Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo- should be used to help reduce the incidence of component dam- nent lead and the foil. age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit 1. Immediately before handling any semiconductor component or board printed foil. semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush. natively, obtain and wear a commercially available discharg- ing wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test. Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only Only for training and service purposes

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IC Remove/Replacement 3. Solder the connections. Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures. should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique Circuit Board Foil Repair as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit Removal board causing the foil to separate from or "lift-off" the board. The 1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when- gently prying up on the lead with the soldering iron tip as the ever this condition is encountered. solder melts. 2. Draw away the melted solder with an anti-static suction-type At IC Connections solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the the IC. following procedure to install a jumper wire on the copper pattern Replacement side of the circuit board. (Use this technique only on IC connec- 1. Carefully insert the replacement IC in the circuit board. tions). 2. Carefully bend each IC lead against the circuit foil pad and solder it. 1. Carefully remove the damaged copper pattern with a sharp 3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary). (It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern. "Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection. 1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper as possible to the component body. pattern and let it overlap the previously scraped end of the 2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off ing on the circuit board. any excess jumper wire. 3. Bend into a "U" shape the replacement transistor leads. 4. Connect the replacement transistor leads to the corresponding At Other Connections leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the each connection. installation of a jumper wire on the component side of the circuit board. Power Output, Transistor Device Removal/Replacement 1. Remove the defective copper pattern with a sharp knife. 1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous 2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens. 3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern board. break and locate the nearest component that is directly con- 4. Insert new transistor in the circuit board. nected to the affected copper pattern. 5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the 6. Replace heat sink. nearest component on one side of the pattern break to the lead of the nearest component on the other side. Diode Removal/Replacement Carefully crimp and solder the connections. 1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the sible to diode body. it does not touch components or sharp edges. 2. Bend the two remaining leads perpendicular y to the circuit board. 3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board. 4. Securely crimp each connection and solder it. 5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder. Fuse and Conventional Resistor Removal/Replacement 1. Clip each fuse or resistor lead at top of the circuit board hollow stake. 2. Securely crimp the leads of replacement component around notch at stake top. Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only Only for training and service purposes

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SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application range 3. Test method This specification is applied to the LED TV used LB59H / 1) Performance: LGE TV test method followed LB59J chassis. 2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC specification 2. Requirement for Test - Wireless : Wireless HD Specification (Option) Each part is tested as below without special notice 1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C 2) Relative Humidity: 65 % ± 10 % 3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. 4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. 5) The receiver must be operated for about 20 minutes prior to the adjustment. 4. Model General Specification No. Item Specification Remarks 1 Market Asia, Oceania, Africa, Middle East(PAL/DVB Market) 1) PAL-BG/DK/I/I’ 2 Television system 2) SECAM L/L’, DK, BG, I 3) DVB-T/T2, C, S/S2 3 Channel Storage ATV / DTV - 1500EA ► DVB-T - Guard Interval(Bitrate_Mbit/s): 1/4, 1/8, 1/16, 1/32 - Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 ► DVB-T2 - Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256, - Modulation : Code Rate Analog : Upper Heterodyne QPSK : 1/2, 2/5, 2/3, 3/4, 5/6 Digital : COFDM(DVB-T) Only DVB-T Model 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 4 Receiving system Digital : COFDM(DVB-T/T2) Only DVB-T2 Model 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 Digital : QAM 256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 ► DVB-C - Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s - Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM ► DVB-S/S2 - Symbolrate DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s DVB-S (QPSK) : 2 ~ 45Msymbol/s - Viterbi DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8 DVB-S2 mode: 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10 5 Video Input RCA PAL, SECAM, NTSC 4 System : PAL, SECAM, NTSC, PAL60 6 Component Input Y/Pb/Pr Antenna, AV1, Component, HDMI1, 7 Head phone out HDMI2, HDMI3, USB1, USB2, USB3 8 HDMI Input HDMI1-DTV,HDMI2-DTV, *HDMI3-DTV PC(HDMI Ver. 1.4), Support HDCP, * HDMI3 : UF77/UF83 9 Audio Input DVI Audio, Component, AV1 10 SPDIF out SPDIF out 11 USB Input For My Media(Movie/Photo/Music List) or For SVC Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only Only for training and service purposes

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5. External Input Support Format 5.1. 2D (1) CVBS input No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed Remarks 1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) NTSC-M 2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) NTSC-M 3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz PAL-BDGHI (2) Component (Y, CB/PB, CR/PR) No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed 1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) 2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) 3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz 4 720*480p 31.47 59.94 27.00 SDTV 480P 5 720*480p 31.50 60.00 27.03 SDTV 480P 6 720*576p 31.25 50.00 27.00 SDTV 576P 50Hz 7 1280*720 44.96 59.94 74.18 HDTV 720P 8 1280*720 45.00 60.00 74.25 HDTV 720P 9 1280*720 45.00 50.00 74.25 HDTV 720P 50Hz 10 1920*1080 28.13 50.00 74.25 HDTV 1080I 50Hz, 11 1920*1080 33.72 59.94 74.18 HDTV 1080I 12 1920*1080 33.75 60.00 74.25 HDTV 1080I 13 1920*1080 56.25 50.00 148.50 HDTV 1080P 14 1920*1080 67.50 60.00 148.50 HDTV 1080P Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only Only for training and service purposes

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(3) HDMI (DTV) No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks 1 640*480 31.47 59.94 25.13 SDTV 480P 2 640*480 31.50 60.00 25.13 SDTV 480P 3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I) 4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I) Spec. out but display 5 720*576 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz 6 720*480 31.47 59.94 27.00 SDTV 480P 7 720*480 31.50 60.00 27.03 SDTV 480P 8 720*576 31.25 50.00 27.00 SDTV 576P 9 1280*720 44.96 59.94 74.18 HDTV 720P 10 1280*720 45.00 60.00 74.25 HDTV 720P 11 1280*720 37.50 50.00 74.25 HDTV 720P 12 1920*1080 28.13 50.00 74.25 HDTV 1080I 13 1920*1080 33.72 59.94 74.18 HDTV 1080I 14 1920*1080 33.75 60.00 74.25 HDTV 1080I 15 1920*1080 26.97 23.98 63.30 HDTV 1080P 16 1920*1080 27.00 24.00 63.36 HDTV 1080P 17 1920*1080 33.71 29.97 79.12 HDTV 1080P 18 1920*1080 33.75 30.00 79.20 HDTV 1080P 19 1920*1080 56.25 50.00 148.50 HDTV 1080P 20 1920*1080 67.43 59.94 148.35 HDTV 1080P 21 1920*1080 67.50 60.00 148.50 HDTV 1080P 22 3840*2160 53.95 23.98 297.00 UDTV 2160P 23 3840*2160 54.00 24.00 297.00 UDTV 2160P 24 3840*2160 56.25 25.00 297.00 UDTV 2160P 25 3840*2160 61.43 29.97 297.00 UDTV 2160P 26 3840*2160 67.50 30.00 297.00 UDTV 2160P 27 3840*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0 28 3840*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0 29 3840*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0 30 4096*2160 53.95 23.98 297.00 UDTV 2160P 31 4096*2160 54.00 24.00 297.00 UDTV 2160P 32 4096*2160 56.25 25.00 297.00 UDTV 2160P 33 4096*2160 61.43 29.97 297.00 UDTV 2160P 34 4096*2160 67.50 30.00 297.00 UDTV 2160P 35 4096*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0 36 4096*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0 37 4096*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0 Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only Only for training and service purposes

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(4) HDMI Input (PC) No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks 1 640*350 31.47 70.09 25.17 EGA 2 720*400 31.47 70.08 28.32 DOS 3 640*480 31.47 59.94 25.17 VESA(VGA) 4 800*600 37.88 60.32 40.00 VESA(SVGA) 5 1024*768 48.36 60.00 65.00 VESA(XGA) 6 1152*864 54.35 60.05 80.00 VESA 7 1360*768 47.712 60.015 84.75 VESA(WXGA) 8 1280*1024 63.98 60.02 109.00 SXGA 9 1920*1080 67.50 60.00 158.40 WUXGA(Reduced Blanking) 10 3840*2160 54.00 24.00 297.00 UDTV 2160P 11 3840*2160 56.25 25.00 297.00 UDTV 2160P 12 3840*2160 67.50 30.00 297.00 UDTV 2160P 13 4096*2160 53.95 23.98 297.00 UDTV 2160P 14 4096*2160 54.00 24.00 297.00 UDTV 2160P Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only Only for training and service purposes

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ADJUSTMENT INSTRUCTION 1. Application Range 3.2. LAN Inspection This specification sheet is applied to all of the LED TV with 3.2.1. Equipment & Condition LB59H / LB59J chassis. ▪ Each other connection to LAN Port of IP Hub and Jig 2. Designation (1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of 25 °C ± 5 °C of temperature and 65 % ± 10 % of relative 3.2.2. LAN inspection solution ▪ LAN Port connection with PCB humidity if there is no specific designation. ▪ Network setting at MENU Mode of TV (4) The input voltage of the receiver must keep AC 100-240 ▪ Setting automatic IP V~, 50/60 Hz. ▪ Setting state confirmation (5) The receiver must be operated for about 5 minutes prior to - If automatic setting is finished, you confirm IP and MAC the adjustment when module is in the circumstance of over Address. 15 °C. In case of keeping module is in the circumstance of 0 °C, it 3.2.3. WIDEVINE key Inspection should be placed in the circumstance of above 15 °C for 2 - Confirm key input data at the "IN START" MENU Mode. hours.  In case of keeping module is in the circumstance of below -20 °C, it should be placed in the circumstance of above 15 °C for 3 hours. [Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area. 3. Automatic Adjustment 3.1. MAC address D/L, CI+ key D/L(Option), Widevine key D/L, ESN D/L, HDCP20 D/L 3.3. LAN PORT INSPECTION(PING TEST) Connect: USB port Connect SET → LAN port == PC → LAN Port Communication Prot connection SET PC ▪ Com 1,2,3,4 and 115200(Baudrate) Mode check: Online Only ▪ Check the test process 3.3.1. Equipment setting : DETECT→MAC→ESN→Widevine→CI(option)→HDCP20 (1) Play the LAN Port Test PROGRAM. ▪ Play: Press Enter key (2) Input IP set up for an inspection to Test Program. ▪ Result: Ready, Test, OK or NG *IP Number : 12.12.2.2 ▪ Printer Out (MAC Address Label) 3.3.2. LAN PORT inspection(PING TEST) (1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable. Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only Only for training and service purposes

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3.4. Model name & Serial number Download 3.5. CI+ Key checking method 3.4.1. Model name & Serial number D/L (Check the Section 3.1) ▪ Press "P-ONLY" key of service remote control. Check whether the key was downloaded or not at ‘In Start’ (Baud rate : 115200 bps) menu. (Refer to below). ▪ Connect RS-232C Signal to USB Cable to USB. ▪ Write Serial number by use USB port. ▪ Must check the serial number at Instart menu. => Check the Download to CI+ Key value in LGset. 3.4.2. Method & notice 3.5.1. Check the method of CI+ Key value (1) Serial number D/L is using of scan equipment. (1) Check the method on Instart menu (2) Setting of scan equipment operated by Manufacturing (2) Check the method of RS232C Command Technology Group. 1) Into the main ass’y mode(RS232: aa 00 00) (3) Serial number D/L must be conformed when it is produced CMD 1 CMD 2 Data 0 in production line, because serial number D/L is mandatory A A 0 0 by D-book 4.0. 2) Check the key download for transmitted command * Manual Download (Model Name and Serial Number) (RS232: ci 00 10) If the TV set is downloaded by OTA or service man, sometimes CMD 1 CMD 2 Data 0 model name or serial number is initialized.(Not always) C I 1 0 It is impossible to download by bar code scan, so It need Manual download. 3) Result value 1) Press the "Instart" key of Adjustment remote control. - Normally status for download : OKx 2) Go to the menu "7.Model Number D/L" like below photo. - Abnormally status for download : NGx 3) Input the Factory model name(ex 47LB650V-ZA) or Serial number like photo. 3.5.2. Check the method of CI+ key value(RS232) 1) Into the main ass’y mode(RS232: aa 00 00) CMD 1 CMD 2 Data 0 A A 0 0 4) Check the model name Instart menu. → Factory name 2) Check the mothed of CI+ key by command displayed. (ex 47LB650V-ZA) (RS232: ci 00 20) 5) C heck the Diagnostics.(DTV country only) → Buyer CMD 1 CMD 2 Data 0 model displayed. (ex 47LB650V-ZA) C I 2 0 3) Result value i 01 OK 1d1852d21c1ed5dcx CI+ Key Value 3.6. WIFI MAC ADDRESS CHECK (1) Using RS232 Command H-freq(kHz) V-freq.(Hz) Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG] (2) Check the menu on in-start Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only Only for training and service purposes

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4. Manual Adjustment (1) HDMI Deep Color OFF # HDMI 1(C/S: E6 1D) 4.1. EDID(The  Extended Display Identification EDID Block 0, Bytes 0-127 [00H-7FH] Data)/DDC(Display Data Channel) download 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 4.1.1. Overview 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 It is a VESA regulation. A PC or a MNT will display an optimal 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 resolution through information sharing without any necessity 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C of user input. It is a realization of "Plug and Play". 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 4.1.2. Equipment 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC - Since embedded EDID data is used, EDID download JIG, 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 HDMI cable and D-sub cable are not need. EDID Block 1, Bytes 128-255 [80H-FFH] - Adjustment remote control 0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 4.1.3. Download method 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 (1) Press "ADJ" key on the Adjustment remote control, then A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 select "12.EDID D/L", By pressing "Enter" key, enter EDID B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 D/L menu. C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 For HDMI EDID D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DVI-D to HDMI or HDMI to HDMI F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D # HDMI2 (C/S: E6 0D) EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 (2) S elect "Start" button by pressing "Enter" key, HDMI1/ 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 4.1.4. EDID DATA 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 ▪ Reference 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A - HDMI1 ~ HDMI3 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC - In the data of EDID, bellows may be different by Input mode. 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 0 1 2 3 4 5 6 7 8 9 A B C D E F EDID Block 1, Bytes 128-255 [80H-FFH] 0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ 0 1 2 3 4 5 6 7 8 9 A B C D E F 0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 0x07 ⓓ 01 ⓔ1 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 0x02 ⓕ 0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 # HDMI 3(C/S : E6 FD) 0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D EDID Block 0, Bytes 0-127 [00H-7FH] 0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 ⓐ Product ID 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 ⓑ Serial No: Controlled on production line. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 ⓒ Month, Year: Controlled on production line: 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’ 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 ⓓ Model Name(Hex): LGTV 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A ⓔ Checksum(LG TV): Changeable by total EDID data. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC ⓕ Vendor Specific(HDMI) 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only Only for training and service purposes

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EDID Block 1, Bytes 128-255 [80H-FFH] 4.3. White Balance Adjustment 0 1 2 3 4 5 6 7 8 9 A B C D E F 4.3.1. Overview 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 ▪ W/B adj. Objective & How-it-works 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 (1) Objective: To reduce each Panel's W/B deviation A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 (2) How-it-works : When R/G/B gain in the OSD is at 192, it B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 means the panel is at its Full Dynamic Range. In order to D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 prevent saturation of Full Dynamic range and data, one E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 of R/G/B is fixed at 192, and the other two is lowered to F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD find the desired value. (3) Adjustment condition : normal temperature 1) Surrounding Temperature : 25 °C ± 5 °C (2) HDMI Deep Color ON 2) Warm-up time: About 5 Min # HDMI1 (C/S : A0 C7) 3) Surrounding Humidity : 20 % ~ 80 % EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 4.3.2. Equipment 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 (1) Color Analyzer: CA-210 (LED Module : CH 14) 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 (2) Adjustment Computer(During auto adj., RS-232C protocol 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 is needed) 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 (3) Adjustment Remote control 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A (4) Video Signal Generator MSPG-925F 720p/216-Gray 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC (Model: 204, Pattern: 49) 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0 → Only when internal pattern is not available • Color Analyzer Matrix should be calibrated using CS-100. EDID Block 1, Bytes 128-255 [80H-FFH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21 4.3.3. Equipment connection MAP 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06 Co lo r Analyzer A0 C0 15 07 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20 RS -232C B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 Probe C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 Co m p ut er D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E RS -232C RS -232C E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 Pat t ern Generat o r F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C7 Signal Source * If TV internal pattern is used, not needed * Checksum (HDMI 1/2) HDMI Deep Color On HDMI Deep Color Off Input FFh (Checksum) FFh (Checksum) 4.3.4. Adj. Command (Protocol) HDMI1 A0 C7 E6 1D START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP HDMI2 E6 D E6 D HDMI3 E6 FD E6 FD - LEN: Number of Data Byte to be sent - CMD: Command - VAL: FOS Data value - CS: Checksum of sent data - A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] ▪ RS-232C Command used during auto-adjustment. RS-232C COMMAND Explanation [CMD ID DATA] wb 00 00 Begin White Balance adjustment wb 00 10 Gain adjustment(internal white pattern) wb 00 1f Gain adjustment completed wb 00 20 Offset adjustment(internal white pattern) wb 00 2f Offset adjustment completed End White Balance adjustment wb 00 ff (internal pattern disappears) Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only Only for training and service purposes

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Ex) wb 00 00 → Begin white balance auto-adj. ** G-fix adjustment wb 00 10 → Gain adj. Adjust modes (Cool), Fix the G gain to 172 (default data) ja 00 ff → Adj. data and change the others (G/B Gain). jb 00 c0 Adjust two modes(Medium / Warm), Fix the one of R/G/B ... gain to 192 (default data) and decrease the others. ... ▪ If internal pattern is not available, use RF input. In EZ Adj. wb 00 1f → Gain adj. completed menu 7.White Balance, you can select one of 2 Test- *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. pattern: ON, OFF. Default is inner(ON). By selecting OFF, wb 00 ff → End white balance auto-adj. you can adjust using RF signal in 216 Gray pattern. ▪ Adj. Map ▪ Adjustment condition and cautionary items Command Data Range 1) Lighting condition in surrounding area Default Adj. item (lower case ASCII) (Hex.) Surrounding lighting should be lower 10 lux. Try to (Decimal) CMD1 CMD2 MIN MAX isolate adj. area into dark surrounding. R Gain j g 00 C0 2) Probe location G Gain j h 00 C0 : Color Analyzer(CA-210) probe should be within 10 cm B Gain j i 00 C0 and perpendicular of the module surface (80° ~ 100°) Cool R Cut 3) Aging time G Cut - After Aging Start, Keep the Power ON status during 5 B Cut Minutes. R Gain j a 00 C0 - In case of LCD, Back-light on should be checked G Gain j b 00 C0 using no signal or Full-white pattern. B Gain j c 00 C0 Medium R Cut 4.3.6. Reference (White balance Adj. coordinate and G Cut color temperature) B Cut ▪ Luminance : 206 Gray R Gain j d 00 C0 ▪ Standard color coordinate and temperature using CS-1000 G Gain j e 00 C0 (over 26 inch) Warm B Gain j f 00 C0 Coordinate Mode Temp ∆uv R Cut x y G Cut Cool 0.271 0.270 13000 K 0.0000 Medium 0.286 0.289 9300 K 0.0000 Warm 0.313 0.329 6500 K 0.0000 4.3.5. Adj. method (1) Auto adj. method ▪ Standard color coordinate and temperature using CA-210(CH 14) 1) Set TV in adj. mode using POWER ON key. Coordinate 2) Zero calibrate probe then place it on the center of the Mode Temp ∆uv Display. x y 3) Connect Cable.(RS-232C to USB) Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000 4) Select mode in adj. Program and begin adj. Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000 5) When adj. is complete (OK Sign), check adj. status pre Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000 mode. (Warm, Medium, Cool) 6) Remove probe and RS-232C cable to complete adj. 4.3.7. LED White balance table ▪ W/B Adj. must begin as start command “wb 00 00” , and ▪ Edge & ALEF LED module change color coordinate because finish as end command “wb 00 ff”, and Adj. offset if need. of aging time. ▪ Apply under the color coordinate table, for compensated (2) Manual adjustment. method aging time. 1) Set TV in Adj. mode using POWER ON. 2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10 cm of the surface. 3) Press ADJ key → EZ adjust using adj. R/C → 7. White- Balance then press the cursor to the right(key ►). (When right key(►) is pressed 216 Gray internal pattern will be displayed) 4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value. 5) Adjustment is performed in COOL, MEDIUM, WARM 3 modes of color temperature. Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only Only for training and service purposes

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▪ (Normal line) White balance table 4.6. Option selection per country Model : (normal line) LGD 4.6.1. Overview Aging Cool Medium Warm - Option selection is only done for models in AJ/JA/IL time x y x y x y (Min) 271 270 286 289 313 329 4.6.2.Method 1 0-2 282 289 297 308 324 348 (1) Press "ADJ" key on the Adjustment remote control, then select Country Group Menu. 2 3-5 281 287 296 306 323 346 (2) Depending on destination, select Country Group Code or 3 6-9 279 284 294 303 321 343 Country Group then on the lower Country option, select 4 10-19 277 280 292 299 319 339 US, CA, MX. Selection is done using +, - or ►◄ KEY. 5 20-35 275 277 290 296 317 336 6 36-49 274 274 289 293 316 333 4.7. HDMI ARC Function Inspection 7 50-79 273 272 288 291 315 331 (1) Test equipment - Optic Receiver Speaker 8 80-119 272 271 287 290 314 330 - MSHG-600 (SW: 1220 ↑) 9 Over 120 271 270 286 289 313 329 - HDMI Cable (for 1.4 version) (2) Test method ▪ AUO, INX, Sharp, CSOT, BOE (Cool is 13000 K) 1) Insert the HDMI Cable to the HDMI ARC port from the Cool Medium Warm master equipment. (HDMI 2) x y x y x y 271 270 285 293 313 329 Target 278 280 293 299 320 339 4.4. Local Dimming Function Check (1) Turn on TV. (2) A t the Local Dimming mode, module Edge Backlight moving right to left Back light of IOP module moving. (3) Confirm the Local Dimming mode. (4) Press “exit” Key. 2) Check the sound from the TV Set. 4.5. Magic Motion Remote control test - E quipment : RF Remote control for test, IR-KEY-Code Remote control for test - You must confirm the battery power of RF-Remote control before test(recommend that change the battery per every lot) - Sequence (test) 1) If you select the ‘start key(OK)’ on the Adjustment remote 3) Check the Sound from the Speaker or using AV & Optic control, you can pairing with the TV SET. TEST program (It’s connected to MSHG-600) 2) You can check the cursor on the TV Screen, when select the "OK" key on the Adjustment remote control. 3) You must remove the pairing with the TV Set by select 4.8. Ship-out mode check (In-stop) ‘Mute + OK Key’ on the Adjustment remote control. - After final inspection, press In-Stop key of the Adjustment remote control and check that the unit goes to Stand-by mode. Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only Only for training and service purposes

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5. GND and Internal Pressure check 7. USB S/W Download(Service only) 5.1. Method (1) Put the USB Stick to the USB socket. (1) GND & Internal Pressure auto-check preparation (2) Automatically detecting update file in USB Stick. - Check that Power Cord is fully inserted to the SET. (If - If your downloaded program version in USB Stick is loose, re-insert) Older, it didn't work. But your downloaded version is (2) Perform GND & Internal Pressure auto-check Newer, USB data is automatically detecting.(Download - Unit fully inserted Power cord, Antenna cable and A/V Version High & Power only mode, Set is automatically arrive to the auto-check process. Download) - Connect D-terminal to AV JACK TESTER (3) Show the message "Copying files from memory". - Auto CONTROLLER(GWS103-4) ON - Perform GND TEST - If NG, Buzzer will sound to inform the operator. - If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.) - Perform I/P test - If NG, Buzzer will sound to inform the operator. - If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process. 5.2. Checkpoint (4) Updating is starting. ▪ TEST voltage (5) Updating Completed, The TV will restart automatically. - GND: 1.5 KV / min at 100 mA - SIGNAL: 3 KV / min at 100 mA ▪ TEST time: 1 second ▪ TEST POINT - GND TEST = POWER CORD GND & SIGNAL CABLE METAL GND - Internal Pressure TEST = POWER CORD GND & LIVE & NEUTRAL ▪ LEAKAGE CURRENT: At 0.5 mArms 6. Audio No. Item Min Typ Max Unit Audio practical max 10 12 W EQ Off 1 Output, L/R (Distortion AVL Off =10% max Output) 8.10 10.8 Vrms Clear Voice Off EQ On Speaker 2 10 12 W AVL On (8 Ω Impedance) Clear Voice On Measurement condition: (6) If your TV is turned on, check your updated version and (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation Tool option. (explain the Tool option, next stage) (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms * If downloading version is more new than your TV have, TV can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn't have a DTV/ATV test on production line. * After downloading, have to adjust TOOL OPTION again. 1) Push "IN-START" key in service remote control. 2) Select "Tool Option 1" and push "OK" key. 3) Punch in the number. (Each model has their number.) 8. Tool Option selection ▪ Method: Press Adj. key on the Adjustment remote control, then select Tool option. Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only Only for training and service purposes

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Copyright © X_TAL DDR3 1866 X 32 24MHz (512MB X 2EA) 1. MAIN(LM14A) CI Slot T2/C/S2 W/O AD P_TS Air/ P_TS B C A Only for training and service purposes Cable TUNER DDR3 1866 X 32 R IF (+/-) T/C Demod (512MB X 2EA) E (T2/C/A) Analog Demod A P_TS DVB-S P_TS EEPROM(NVRAM) R TUNER DEMOD I2C 1 (H) (S2) CVBS (256Kb) (S2) SPI FLASH(BOOT) LNB (32Mbit) Chip Config LG Electronics. Inc. All rights reserved. 4b’1010 B-CAS SMARTCARD_I/F eMMC (JAPAN) B-CAS (4GB) USB3 (3.0) OCP Vx1 51P USB Mstar I2C 6 USB2 (2.0) LM14A USB1 (2.0) OCP - 17 - I2S Out MAIN Audio AMP HDMI3(MHL) I2C 4 (NTP7515) HDMI HDMI2(ARC) HDMI1 WIFI/BT Combo USB_WIFI SUB BLOCK DIAGRAM H/P ASSY AV/COMP CVBS/YPbPr IR / KEY LOGO LIGHT(Ready SCART CVBS/RGB (IN/OUT) SPDIF OUT Sub Micom OPTIC (RENESAS I2C 3 R5F100GEAFB) LAN ETHERNET (HW Port) X_TAL 32.768KHz LGE Internal Use Only

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Copyright © X_TAL 24MHz CI Slot DDR3 1866 X 32 T2/C/S2 W/O AD (512MB X 2EA) P_TS Only for training and service purposes Air/ P_TS B A Cable TUNER DDR3 1866 X 32 R IF (+/-) (512MB X 2EA) E (T2/C/A) A P_TS R DVB-S I2C 1 EEPROM(NVRAM) TUNER DEMOD 1-1. MAIN(LM14A+URSA11) CVBS (HW Port) (256Kb) (S2) (S2) S_TS for JP eMMC Chip Config LG Electronics. Inc. All rights reserved. LNB (4GB) 4b’1010 B-CAS SMARTCARD_I/F Vx1 (JAPAN) B-CAS URSA11 51P/41P USB1 (3.0) OCP USB Mstar - 18 - USB2 (2.0) LM14A DDR3 1866 X 32 USB3 (2.0) OCP (1Gb X 2EA) HDMI1(MHL) HDMI 2.0 I2S Out HDMI MAIN Audio AMP HDMI2(ARC) I2C 4 (NTP7515) HDMI3(External EDID) Woofer Audio AMP RS232C (NTP7515) H/P USB_WIFI WIFI/BT Combo AV/COMP CVBS/YPbPr SUB SCART IR / KEY ASSY CVBS/RGB LOGO LIGHT(Ready) (IN/OUT) OPTIC SPDIF OUT Sub Micom I2C 3 LAN ETHERNET (RENESAS X_TAL (HW Port) R5F100GEAFB) 32.768KHz LGE Internal Use Only

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Copyright © +3.3V_NORMAL MSTAR 2. I2C(LM14A) LM14A 1.8KΩ +3.3V_TU I2C_SDA4 Only for training and service purposes IC5600 100Ω NTP7514(Main AMP) I2C_SCL4 IC6900 33Ω 1.8KΩ LNB I2C_SDA2 TU6704 33Ω +3.3V_NORMAL I2C_SCL2 TUNER LG Electronics. Inc. All rights reserved. +3.3V_NORMAL 1.8KΩ 1.8KΩ IC3000 I2C_SCL3 (HW) - 19 - RENESAS 33Ω I2C_SDA3 (HW) MICOM I2C_SDA1 IC102 33Ω I2C_SCL1 NVRAM +3.3V_LNA_TU +3.3V_NORMAL 1.8KΩ 1.8KΩ P7201 I2C_SDA6 0Ω I2C_SDA5 LCD Panel I2C_SCL6 33Ω TU6704 I2C_SCL5 TUNER LGE Internal Use Only

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Copyright © IC5900 100Ω +3.3V_NORMAL NTP7515(Woofer AMP) MSTAR LM14A 33pF 1.8KΩ +3.3V_TU I2C SCL/SDA4(SW) Only for training and service purposes GPIO19 / [LED0] / GPIO74 IC5800 100Ω IC6900 NTP7515(Main AMP) GPIO20 / [LED1] / GPIO75 33Ω 1.8KΩ LNB 2-1. I2C(LM14A+URSA11) I2C_SCL/SDA2(HW) 33pF +3.3V_NORMAL GPIO30 / SCK4 33Ω TU6704 GPIO31 / SDA4 TUNER LG Electronics. Inc. All rights reserved. 1.8KΩ +3.3V_NORMAL I2C SCL/SDA3(HW) IC3000 GPIO28 / SCK0 / GPIO83 RENESAS 33Ω GPIO29 / SDA0 /GPIO84 1.8KΩ MICOM - 20 - I2C SCL/SDA1(HW) DDCR_CK/ SCK3 / GPIO54 +3.3V_NORMAL 33Ω IC100 DDCR_DA / SDA3 / GPIO53 NVRAM +3.3V_LNA_TU 1.8KΩ I2C_SCL/SDA6(SW) DIM2 / TX4 / GPIO112 P7201 0Ω DIM3 / RX4 / GPIO113 1.8KΩ LCD Panel I2C SCL/SDA5(HW) +3.3V_NORMAL GPIO32 / SCK5 / GPIO87 TU6704 33Ω GPIO33 / SDA5 / GPIO88 TUNER 1.8KΩ I2C SCL/SDA7(HW) TGPIO2 / SCK1 / GPIO159 URSA11 (LGE5352) 33Ω TGPIO3 / SDA1 / GPIO160 LGE Internal Use Only

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Copyright © 3. URSA11 Power +12V I2C_SCL6 I2C_SDA6 I2C_SCL7 V x1 V x1 URSA PQ HTPDAn_IN LOCKAn_IN URSA I2C_SDA7 8 lane 8 lane DC- DC Converter +1.5V_U_DDR UART2_RX DEBUG Data_Format_0 Data_Format_1 UART I2CS_SCL (BD9D321EFJ _3A ) Switch (URSA DDR) UART2_TX I2CS_SDA 51P 41P Only for training and service purposes URSA SYS DC- DC Converter +0.95V UART1_RX SCL2_+3.3V_DB (TPS53513RVER_8A) I2C_S Port ( URSA) UART SDA2_+3.3V_DB 4 Pin UART1_TX Jig Download X- Tal (24Mhz) LG Electronics. Inc. All rights reserved. XO_URSA XIN_URSA LOCKAn HTPDAn Vx1 VIDEO 8Lane Data_Format_1 - 21 - Data_Format_0 Vx1 OSD 4Lane SPI_DI SPI FLASH SPI_DO/CK/CZ - 32MB (x1) LM14A LOCKAn_OSD / LOCKAN_Video URSA11 UART1_RX UART1_TX UART2_RX UART2_TX URSA9_CONNECT I2CS_SCL I2CS_SDA A_DDR3_DQ[31:0] A_DDR3_A[15:0]/ BA[2:0]/MCLK/MCKZ T-CON POWER 5 Pin DDR3 SDRAM - 1Gbit (x16) PANEL_VCC DDR3- SDRAM 1866 186 6 - 1Gbit (x16) - 1866 LGE Internal Use Only

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Copyright © ▪ DCDC efficiency : 80% DCDC LDO 5.5mA MICOM H/P AMP 4. POWER(LM14A) 3.5V NTP7514 Only for training and service purposes 70mA IR Ass’y (0~1.8A) WIFI Combo NVRAM 3.3V NORMAL 265mA 6A LM14A IC2302 339mA LM14A 1.5V LG Electronics. Inc. All rights reserved. 1.5V DDR IC402 DDR_VTT 3A DDR3*6EA DDR_VTT IC2303 1.5V 457mA 1.1V Core 4381mA IC407 DDR_VTT 12A LM14A DDR_VTT 12V IC2500 (2.1A-2.8A) 1.8V 200mA - 22 - UHD 1A eMMC 1.1V CPU Core IC2301 6A LM14A IC2300 D.Demod_ Core 2A 700mA IC6500 500mA Tuner LNB LNB option 500mA PANEL VCC CI SLOT MHL 912mA 5V NORMAL 2000mA 24V 6A USB1 (0.1A~1.2) IC2305 1500mA USB2/3 830mA NTP7514 LGE Internal Use Only

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Copyright © Measurement condition SW: beehive-204 Video : USB4K movie DCDC LDO MICOM 0.09A Only for training and service purposes 3.5V IR Assy Wifi/MR connect 0.23A 3.3V Stand_by : 0.0067A IC200 LM14A 0.321A AVDD_DMPLL LM14A 0.617A 3.3V NORMAL / 6A 0.369A Max(HDMI) : 0.776A IC2302 URSA11 LM14A 4-1. POWER(LM14A+URSA11) 1.26A 1.8V eMMC 1.5V DDR / 3A LG Electronics. Inc. All rights reserved. DDR3*4EA 1A eMMC IC2303 IC2301 1.5V IC402 DDR_VTT DDR_VTT Tuner 2.7A 0.98V Core / 6A LM14A 12V IC2501 H/P AMP 0.63A - 23 - 1.0V CPU Core / 4A IC2502 LM14A NTP7515 4.09A 0.95V URSA Core / 8A WIFI Combo IC13402 URSA11 2.95A NVRAM URSA11 1.055A 1.5V_U_DDR / 3A IC13403 DDR3*2EA 1.5V IC13000 URSA LNB LNB option URSA DDR_VTT DDR_VTT 1.37A PANEL_VCC Max(Comp) : 1.6A 0.29A 5V NORMAL / 6A IC2305 USB1 24V Max(HDMI) : 0.32A USB2/3 0.58A 0.48A Max(HDMI) : 0.951A NTP7515 Max(HDMI) : 0.89A LGE Internal Use Only

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Copyright © TDJM-G251D +3.3V_NORMAL [+3.3V_LNA_TU] 1 [+3.3V_TUNER] 11 [3.3V_Demod_TU] 26 5. TUNER(LM14A) +3.3V_NORMAL +1.1V_Demod_Core Only for training and service purposes [1,1V_D_Demod_Core] 28 1.8KΩ CI Slot LNB_TX 10 [TONECTRL] [LNB_TX] 29 LNB PCM_5V_CTL CI 5V +5V_CI_ON LNB_OUT 2 [LNB] VCC [LNB_OUT] 31 IC6900 Power detect I2C_SCL2 7 [SCL] [I2C_SCL2_TU] 27 A8303SESTR-TB 33Ω 8 [SDA] [I2C_SDA2_TU] 30 I2C_SDA2 +5V_CI_ON F5[SCK2] LM14A 33 Ω F6 [SDA2] AE3[GPIO_PM4] CAM_CD1_N 10K Ω /CI_CD1 LG Electronics. Inc. All rights reserved. I2C_SCL5 CI_CD1 [I2C_SCL5_TU] 4 F10[SCK5] OR 33 Ω AR17[PCMCD] /CI_CD2 [I2C_SDA5_TU] 5 I2C_SDA5 G10[SDA5] GATE CI_CD2 AP13[TS2CLK] CI_MISTRT FE_DEMOD1_TS_ERROR AP12[TS2VALID] CI_MIVA_ERR [FE_DEMOD1_TS_ERROR_TU] 12 AM13[TS2SYNC] /PCM_CE1 CI_MCLKI FE_DEMOD1_TS_CLK AM13[PCMCEN] [FE_DEMOD1_1_TS_CLK] 14 PCM_CE1 FE_DEMOD1_TS_SYNC AN11[TS0CLK] [FE_DEMOD1_TS_SYNC] 15 AP9(TS0SYNC] FE_DEMOD1_TS_VAL EB_BE_NO [FE_DEMOD1_TS_VAL] 16 AN9[TS0VALID] AT15[PCMIOWR] CI_IOWR EB_BE_N1 AR15PCMIORD] CI_IORD FE_DEMOD1_TS_DATA[0] 17 - 24 - FE_DEMOD1_TS_DATA[1] 18 FE_DEMOD1_TS_DATA[2] 19 EB_ADDR[0-14] CI_ADDR[0-14] FE_DEMOD1_TS_DATA[3] 20 FE_DEMOD1_TS_DATA[0-7] AU10-AR19 CI_ADDR[0-14] AP10~AM9 FE_DEMOD1_TS_DATA[4] 21 [TS0DATA[0-7] EB_DATA[0-7] CI_DATA[0-7] FE_DEMOD1_TS_DATA[5] 22 AT13-AT18 EB_DATA[0-7] FE_DEMOD1_TS_DATA[6] 23 FE_DEMOD1_TS_DATA[7] 24 PCM_RESET AU11[PCMRST] PCM_RESET CAM_WAIT_N AT10[PCMWAIT] CAM_WAIT_N CAM_REG_N REG AR14[PCMREG] CAM_IREQ_N AU20[PCMIRQA] CAM_IREQ_N /EB_OE_N AT21[PCMOEN] CI_OE RF_SWITCH_CTL /EB_WE_N A15 [GPIO119] AR11[[PCMWEN] CI_WE [RF_SWITCH_CTL] 2 /TU_RESET1 A12 [GPIO62] TPI_CLK CI_TS_CLK [/TU_RESET1_TU] 25 AN17[TS1CLK] TS_OUT_CLK TPI_VAL CI_TS_VAL AM17[TS1VALID] TS_OUT_VAL IF_P ADC_I_INP TPI_SOP CI_TS_SYNC AP1 [VIFP] AN16[TS1SYNC] TS_OUT_SYNC [IF_P] 6 IF_N FILTER ADC_I_INN AP2 [VIFM] TPI_DATA[0-7] TPI_DATA[0-7] [IF_N] 7 AN16~AP19 TUNER_SIF 33Ω TS_OUT[0-7] AN2[SIFP] [TPI_DATA[0-7]] [TU_SIF_TU] 8 TU_CVBS FE_DEMOD1_TS_DATA [0-7] CI_MDI[0-7] AE5[CVBS0] AM14~AM15 TS_IN[0-7] [TU_CVBS_TU] 9 33Ω IF_AGC [TPO_DATA[0-7]] [IF_AGC_TU] 3 AP3[IF_AGC] LGE Internal Use Only

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Copyright © TDJM-G301D +3.3V_TUNER +2.5V_NORMAL [+3.3V_LNA_TU] 1 [+3.3V_TUNER] 11 [3.3V_Demod_TU] 26 [+2.5V_DEMOD] 38 +3.3V_TU Demod_Core Only for training and service purposes [1,1V_D_Demod_Core] 28 1.8KΩ CI Slot LNB_TX 10 [TONECTRL] [LNB_TX] 29 LNB PCM_5V_CTL LNB_OUT 2 [LNB] CI 5V +5V_CI_ON [LNB_OUT] 31 IC6900 VCC 7 [SCL] A8303SESTR-TB Power detect [I2C_SCL2_TU] 27 I2C_SCL2 33Ω 8 [SDA] [I2C_SDA2_TU] 30 I2C_SDA2 +5V_CI_ON +3.3V_LNA_TU LM14A GPIO30/SCK4/GPIO85 5-1. TUNER(LM14A+URSA11) 33 Ω GPIO31/SDA4/GPIO86 GPIO_PM[4]/GPIO14 CAM_CD1_N 10K Ω 1.8KΩ /CI_CD1 LG Electronics. Inc. All rights reserved. I2C_SCL5 CI_CD1 [I2C_SCL5_TU] 4 GPIO32/SCK5/GPIO87 OR 33 Ω PCM_CD_N/GPIO151 /CI_CD2 [I2C_SDA5_TU] 5 I2C_SDA5 GPIO33/SDA5/GPIO88 GATE CI_CD2 TS1_CLK/GPIO172 CI_MISTRT FE_DEMOD1_TS_ERROR TS1_VLD/GPIO174 CI_MIVA_ERR [FE_DEMOD1_TS_ERROR_TU] 12 TS1_SYNC/GPIO173 /PCM_CE1 CI_MCLKI FE_DEMOD1_TS_CLK PCM_CE_N/GPIO124 [FE_DEMOD1_1_TS_CLK] 14 PCM_CE1 FE_DEMOD1_TS_SYNC TS1_CLK/GPIO172 [FE_DEMOD1_TS_SYNC] 15 TS1_SYNC/GPIO173 FE_DEMOD1_TS_VAL EB_BE_NO [FE_DEMOD1_TS_VAL] 16 TS1_VLD/GPIO174 PCM_IOWR_N/GPIO130 CI_IOWR EB_BE_N1 PCM_IORD_N/GPIO128 CI_IORD FE_DEMOD1_TS_DATA[0] 17 - 25 - FE_DEMOD1_TS_DATA[1] 18 FE_DEMOD1_TS_DATA[2] 19 EB_ADDR[0-14] CI_ADDR[0-14] FE_DEMOD1_TS_DATA[3] 20 FE_DEMOD1_TS_DATA[0-7] PCM_A[0~14] CI_ADDR[0-14] GPIO [175~182] FE_DEMOD1_TS_DATA[4] 21 TS1_D[0-7] EB_DATA[0-7] CI_DATA[0-7] FE_DEMOD1_TS_DATA[5] 22 PCM_D[0~7] EB_DATA[0-7] FE_DEMOD1_TS_DATA[6] 23 FE_DEMOD1_TS_DATA[7] 24 PCM_RESET/GPIO150 PCM_RESET PCM_RESET PCM_WAIT_N/GPIO140 CAM_WAIT_N CAM_WAIT_N CAM_REG_N REG PCM_REG_N/GPIO144] CAM_IREQ_N PCM_IRQA_N/GPIO135 CAM_IREQ_N /EB_OE_N PCM_OE_N/GPIO126 CI_OE RF_SWITCH_CTL /EB_WE_N SPI1_CK/GPIO106 PCM_WE_N/GPIO134 CI_WE [RF_SWITCH_CTL] 2 /TU_RESET1 PM_SPI_CZ/GPIO0 TPI_CLK CI_TS_CLK [/TU_RESET1_TU] 25 TS0_CLK/GPIO171 TS_OUT_CLK TPI_VAL CI_TS_VAL TS0_VLD/GPIO169 TS_OUT_VAL IF_P ADC_I_INP TPI_SOP CI_TS_SYNC AL2 [VIFP] TS0_SYNC/GPIO170 TS_OUT_SYNC [IF_P] 6 IF_N FILTER ADC_I_INN AM2 [VIFM] TPI_DATA[0-7] TPI_DATA[0-7] [IF_N] 7 TUNER_SIF TS0_D[0~7] 33Ω TS_OUT[0-7] AK1[SIFP] [TU_SIF_TU] 8 TU_CVBS CI_MDI[0-7] AC6[CVBS0] TS1_D[0~7] FE_DEMOD1_TS_DATA [0-7] TS_IN[0-7] [TU_CVBS_TU] 9 33Ω IF_AGC [IF_AGC_TU] 3 AK3[IF_AGC] LGE Internal Use Only

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6. VIDEO AUDIO IN(LM14A) Copyright © LG Electronics. Inc. All rights reserved. - 26 - LGE Internal Use Only Only for training and service purposes

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6-1. VIDEO AUDIO IN(LM14A+URSA11) Copyright © LG Electronics. Inc. All rights reserved. - 27 - LGE Internal Use Only Only for training and service purposes

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Copyright © SCART SCART_L/ Rout IC6000 DTV/MNT_L/R_OUT [ LINE_OUT_0L] COMP1/ AV1/ DVI_L_IN Only for training and service purposes [ LINE_OUT_0R] AZ4580MTR LPF COMP1/ AV1/ DVI_R_IN [ LINE_IN_0L] OP AMP [ LINE_IN_0R] 7. AUDIO OUT(LM14A) Mute CTRL (TR) JK3802 JK4600 DVB only SCART SCART_MUTE AUD_MASTER_CLK LG Electronics. Inc. All rights reserved. [ I2S_OUT_MCK] SC_L_IN / SC_R_IN [ LINE_IN_2L] AUD_LRCH [ I2S_OUT_WS] [ LINE_IN_2R] AUD_LRCK [ I2S_OUT_SD] 4P WAFER AUD_SCK [ I2S_OUT_BCK] IC1200 LPF SPEAKER_L DVB only I2C_SDA4 Audio AMP JK4600 [ SDA4] NTP7515 LPF SPEAKER_R I2C_SCL4 [ SCL4] - 28 - AMP_RESET_N [ GPIO160] LM14A AMP_MUTE Tuner TUNER_SIF TR BUF [ SIFP] IC3000 MICOM SIDE_HP_MUTE SPDIF_OUT HEAD PHONE [ SPDIF_OUT] [EAR_OUT_L] HP_LOUT / HP_ROUT [EAR_OUT_R] LPF JK3401 JK3403 LGE Internal Use Only

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Copyright © SCART SCART_L/ Rout IC6000 DTV/MNT_L/R_OUT [ LINEOUT_L2] COMP1/ AV1/ DVI_L_IN AZ4580MTR LPF [ LINEOUT_R2] Only for training and service purposes COMP1/ AV1/ DVI_R_IN [ LINEIN_L0] OP AMP [ LINE_N_R0] Mute CTRL JK3802 (TR) JK4600 DVB only SCART SCART_MUTE 4P WAFER LG Electronics. Inc. All rights reserved. SC_L_IN / SC_R_IN [ LINEIN_L1] AUD_LRCK [ I2S_OUT_WS/ GPIO98] IC5800 LPF Front_L [ LINE_N_R1] AUD_LRCH I2S 7-1. AUDIO OUT(LM14A+URSA11) [ I2S_OUT_SD/ GPIO101] Front AMP AUD_SCK LPF Front_R [ I2S_OUT_BCK/ GPIO100] NTP7515 2P/ 4P WAFER JK4600 DVB only [ GPIO20/ [ LED1] / GPIO75] I2C_SDA4 I2C I2C_SCL4 IC5900 LPF Woofer_L [ GPIO19/ [ LED0] / GPIO74] - 29 - Woofer AMP NTP7515 LPF Woofer_R [ PWM3/ GPIO155] AMP_RESET_N LM14A Tuner AMP_MUTE TUNER_SIF TR BUF [ SIFP] IC3000 MICOM SIDE_HP_MUTE SPDIF_OUT HEAD PHONE [ SPDIF_OUT] [EARPHONE_OUTL] HP_LOUT / HP_ROUT [ EARPHONE_OUTR] LPF JK3800 JK3803 LGE Internal Use Only

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Copyright © DDC_SCL_1 DDC_SDA_1 TMDS Link 8bits 8. HDMI(LM14A) HDMI1 Only for training and service purposes DDC_SCL_2 DDC_SDA_2 LG Electronics. Inc. All rights reserved. LM14A TMDS Link 8bits HDMI_ARC HDMI2&ARC - 30 - CEC_REMOTE DDC_SCL_3 DDC_SDA_3 TMDS Link 8bits MHL_DET_LM15 HDMI3&MHL X-Tal(X3000) RENESAS Q600 32.768kHz MICOM(IC3000) HDMI_CEC_MICOM * TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits LGE Internal Use Only

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Copyright © [DDCDD_CK/GPIO44] DDC_SCL_3 DDC_SDA_3 [DDCDD_DA/GPIO45] TMDS Link 8bits HDMI3&External EDID Only for training and service purposes IC3301 HDMI1.4 LM14A External EDID DDC_SCL_2 8-1. HDMI(LM14A+URSA11) [DDCDB_CK/GPIO40] DDC_SDA_2 [DDCDB_DA/GPIO41] LG Electronics. Inc. All rights reserved. TMDS Link 8bits HDMI_ARC [ARC0/GPIO6] HDMI2&ARC HDMI1.4 - 31 - CEC_REMOTE DDC_SCL_1 [DDCDA_CK/GPIO38] DDC_SDA_1 [DDCDA_DA/GPIO39] TMDS Link 8bits MHL_DET_LM15 [GPIO_PM[14]/GPIO24] HDMI1&MHL HDMI2.0 X-Tal(X3000) RENESAS 32.768kHz MICOM(IC3000) Q3001 HDMI_CEC_MICOM * TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits LGE Internal Use Only

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Copyright © USB_DM1 USB1 [USB_DM] +5V_USB_1 [USB_DP] USB_DP1 [GPIO162] /USB_OCD1 [GPIO163] USB_CTL1 6A Only for training and service purposes USB_DM2 USB2 +5V_USB_2 DCDC USB2.0 [USB2_DM] [USB2_DP] USB_DP2 IC2305 [GPIO50] /USB_OCD2 [GPIO51] USB_CTL2 LG Electronics. Inc. All rights reserved. USB_DM3 [USB0_DM] USB3 [USB0_DP] USB_DP3 +5V_USB_3 LM14A SSUSB_RXP/SSUSB_RXN [USB_SSRX] [USB_SSTX] SSUSB_TXP/SSUSB_TXN OCP USB3.0 IC4500 - 32 - /USB_OCD3 [GPIO14] [GPIO18] USB_CTL3 9. USB / WIFI / M-REMOTE / UART (LM14A) WIFI_DM [USB1_DM] [USB1_DP] WIFI_DP WIFI Combo M_RFModule_RESET [GPIO57] SOC_TX [TX1] SOC_RX [RX1] RS232C_Debug(4P wafer) RENESAS MICOM(IC3000) LGE Internal Use Only

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Copyright © USB_DM3 USB3 [DM_P2] +5V_USB_3 [DP_P2] USB_DP3 [TGPIO0/GPIO157] /USB_OCD3 [TGPIO1/GPIO158] USB_CTL3 6A Only for training and service purposes USB_DM2 USB2 +5V_USB_2 DCDC USB2.0 [DM_PSS1] [DP_PSS1] USB_DP2 IC2305 [SAR0/GPIO46] /USB_OCD2 [SAR1/GPIO47] USB_CTL2 LG Electronics. Inc. All rights reserved. USB_DM1 [DM_PSS] USB1 [DP_PSS] USB_DP1 +5V_USB_1 LM14A SSUSB_RXP/SSUSB_RXN [SSUSB_RXP/N] [SSUSB_TXP/N] SSUSB_TXP/SSUSB_TXN OCP USB3.0 IC4300 - 33 - /USB_OCD1 [GPIO_PM[1]/PM_UART1/GPIO11] [GPIO_PM[5]/PM_UART1/GPIO15] USB_CTL1 WIFI_DM [DM_P0] [DP_P0] WIFI_DP WIFI Combo 9-1. USB / WIFI / M-REMOTE / UART(LM14A+URSA11) M_RFModule_RESET [GPIO_PM[10]/[SPI-CZ2N]/GPIO20] SOC_TX [GPIO3/TX1/GPIO58] SOC_RX [GPIO4/RX1] RS232C_Debug(4P wafer) RENESAS MICOM(IC3000) LGE Internal Use Only

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EXPLODED VIEW IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. 400 120 800 910 521 900 121 540 500 401 LV1 530 570 Stand screw A10 A22 820 200 Copyright © LG Electronics. Inc. All rights reserved. - 34 - LGE Internal Use Only Only for training and service purposes

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LB59H (LM14A) Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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SPI_CK_SOC COMPENSATION_DONE OLED LM14A+URSA9 SPI_DI_SOC TXVBY1_0N FAN_ON LM14A UF68/64 +3.3V_NORMAL SPI_DO_SOC FRC_FLASH_SEL_SOC TXVBY1_0P CHIP CONFIG NVRAM +3.3V_NORMAL /SPI_CS TXVBY1_1N /TU_RESET2 Rohm_NVRAM IC101-*1 FRC_FLASH_WP GST_A LM14A UF74 BR24G256FJ-3 EAN62389502 TXVBY1_1P ROHM Semiconductor KOREA CORPORATION TXOSD_3P LOCKAn_OSD GCLK_A 4.7K 4.7K 4.7K Atmel_NVRAM WOL_WAKE_UP_SOC 4.7K A0 VCC IC101 1 8 TXOSD_3N URSA9_CONNECT MCLK_A PMIC_RESET 5V_DET_HDMI_1 AT24C256C-SSHL-T C100 A1 2 7 WP Data_Format_1 OPT EO_A OPT EAN61133501 ATMEL CORPORATION 0.1uF A2 3 6 SCL TXOSD_2P DATA_FORMAT_1_SOC LM14A_ONLY LOCKOUT12 /USB_OCD3 GND 4 5 SDA TXOSD_2N Data_Format_0 R108 R110 R115 DATA_FORMAT_0_SOC USB_CTL3 R122 TXOSD_1P URSA_RESET_SoC A0 VCC HTPDAn_OSD 1 8 L/D_VSYNC_SOC TXOSD_1N HTPDAn_Video IC100 Write Protection L/D_CLK_SOC LED1 A1 WP TXOSD_0P LGE5332(LM14A) 2 7 TXOSD_0N L/D_DI_SOC SPI_DI_SOC - Low : Normal Operation IC100 - High : Write Protection EB_DATA[0-7] LED0 A2 3 A0’h 6 SCL LGE5332(LM14A) EB_DATA[0] PWM_PM I2C_SCL1 V-BY-ONE AH14 4.7K 4.7K 4.7K FE_DEMOD1_TS_DATA[0-7] 4.7K EB_DATA[1] PCM_D[0]/GPIO147 FE_DEMOD1_TS_DATA[0] GND SDA I2C_SDA1 AG13 AH13 4 5 PCM_D[1]/GPIO148 TS1_D0/GPIO182 EB_DATA[2] FE_DEMOD1_TS_DATA[1] OPT OPT 33 D9 AF32 AG12 AG11 AR101 PWM_DIM TXVBY1_0N PCM_D[2]/GPIO149 TS1_D1/GPIO181 PWM0/GPIO152 LVSYNC/[VX1_0-] EB_DATA[3] AK22 AG10 FE_DEMOD1_TS_DATA[2] F10 AF31 R109 TXVBY1_0P R111 R116 PWM_DIM2 R123 PWM1/GPIO153 LHSYNC/[VX1_0+] EB_DATA[4] PCM_D[3]/GPIO119 TS1_D2/GPIO180 FE_DEMOD1_TS_DATA[3] F8 AG32 AK21 AJ11 FAN_ON TXVBY1_1N PCM_D[4]/GPIO120 TS1_D3/GPIO179 PWM2/GPIO154 LDE/[VX1_1-] EB_DATA[5] AL21 AH10 FE_DEMOD1_TS_DATA[4] E9 AG31 TXVBY1_1P AMP_RESET_N PWM3/GPIO155 LCK/[VX1_1+] EB_DATA[6] PCM_D[5]/GPIO121 TS1_D4/GPIO178 FE_DEMOD1_TS_DATA[5] AM23 AJ13 EB_DATA[7] PCM_D[6]/GPIO122 TS1_D5/GPIO177 FE_DEMOD1_TS_DATA[6] N5 AH31 AH20 AG9 PWM_PM TXVBY1_2N EB_ADDR[0-14] PCM_D[7]/GPIO123 TS1_D6/GPIO176 PWM_PM/GPIO7 R_ODD[7]/LVB0N/[VX1_2-] AH9 FE_DEMOD1_TS_DATA[7] AH30 TXVBY1_2P R_ODD[6]/LVB0P/[VX1_2+] EB_ADDR[0] TS1_D7/GPIO175 F4 AJ31 AG14 AH11 TXVBY1_3N PCM_A[0]/GPIO146 TS1_CLK/GPIO172 FE_DEMOD1_TS_CLK CHIP_CONFIG[3:0] /USB_OCD2 SAR0/GPIO46 R_ODD[5]/LVB1N/[VX1_3-] EB_ADDR[1] AL20 AJ10 G5 AJ32 TXVBY1_3P {LED1, SPI_DI,LED0, PWM_PM} USB_CTL2 SAR1/GPIO47 R_ODD[4]/LVB1P/[VX1_3+] EB_ADDR[2] PCM_A[1]/GPIO145 TS1_VLD/GPIO174 FE_DEMOD1_TS_VAL E5 AK32 AG15 AH12 FRC_FLASH_WP TXVBY1_4N PCM_A[2]/GPIO143 TS1_SYNC/GPIO173 FE_DEMOD1_TS_SYNC Value Mode Description SAR2/GPIO48 R_ODD[3]/LVB2N/[VX1_4-] EB_ADDR[3] AH15 E4 AK31 TXVBY1_4P TPI_DATA[0-7] 4’b1000 SB51_ExtSPI 51 boot from SPI DDTS_TX SAR3/GPIO49 R_ODD[2]/LVB2P/[VX1_4+] EB_ADDR[4] PCM_A[3]/GPIO142 TPI_DATA[0] 4’b1001 HEMCU_ExtSPI ARM boot from SPI G4 AL32 AM19 AK17 TXVBY1_5N PCM_A[4]/GPIO141 TS0_D0/GPIO161 SAR5 R_ODD[1]/LVBCLKN/[VX1_5-] EB_ADDR[5] AJ17 AL18 TPI_DATA[1] 4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC AL31 TXVBY1_5P 4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND R_ODD[0]/LVBCLKP/[VX1_5+] EB_ADDR[6] PCM_A[5]/GPIO139 TS0_D1/GPIO162 TPI_DATA[2] AK30 AJ16 AK18 4’b1100 DBUS for test only TXVBY1_6N PCM_A[6]/GPIO138 TS0_D2/GPIO163 G_ODD[7]/LVB3N/[VX1_6-] EB_ADDR[7] AH17 AL15 TPI_DATA[3] 4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication W5 AL30 TXVBY1_6P SPI_CK_SOC PM_SPI_CK/GPIO1 G_ODD[6]/LVB3P/[VX1_6+] EB_ADDR[8] PCM_A[7]/GPIO137 TS0_D3 TPI_DATA[4] 4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication V4 AK29 AM20 AL16 SPI_DI_SOC TXVBY1_7N PCM_A[8]/GPIO131 TS0_D4/GPIO165 4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; PM_SPI_DI/GPIO2 G_ODD[5]/LVB4N/[VX1_7-] EB_ADDR[9] AH19 AK15 TPI_DATA[5] V5 AL29 TXVBY1_7P SPI_DO_SOC PM_SPI_DO/GPIO3 G_ODD[4]/LVB4P/[VX1_7+] EB_ADDR[10] PCM_A[9]/GPIO129 TS0_D5/GPIO166 TPI_DATA[6] Y6 AJ20 AM16 /TU_RESET1 PM_SPI_CZ/GPIO0 EB_ADDR[11] PCM_A[10]/GPIO125 TS0_D6/GPIO167 TPI_DATA[7] R167 0 Y4 AK28 TXOSD_0N AK20 AK16 /SPI_CS GPIO_PM[6]/[SPI-CZ1N]/GPIO16 G_ODD[3]/LVA0N/[OSD_0-] EB_ADDR[12] PCM_A[11]/GPIO127 TS0_D7/GPIO168 OPT Y5 AM28 AG17 AL19 TXOSD_0P PCM_A[12]/GPIO136 TS0_CLK/GPIO171 TPI_CLK GPIO_PM[10]/[SPI-CZ2N]/GPIO20 G_ODD[2]/LVA0P/[OSD_0+] EB_ADDR[13] AJ19 AM17 LM14 HW Option M_RFModule_RESET G_ODD[0]/LVA1P/[OSD_1+] AL28 AK27 TXOSD_1N TXOSD_1P EB_ADDR[14] AG18 PCM_A[13]/GPIO132 TS0_VLD/GPIO169 AL17 TPI_VAL G_ODD[1]/LVA1N/[OSD_1-] PCM_A[14]/GPIO133 TS0_SYNC/GPIO170 TPI_SOP AK26 TXOSD_2N +3.3V_NORMAL B_ODD[7]/LVA2N/[OSD_2-] AH18 AH23 AL8 AL26 TXOSD_2P DDCA_CK DDCA_CK/GPIO8 B_ODD[6]/LVA2P/[OSD_2+] SM_Vsel CAM_IREQ_N PCM_IRQA_N/GPIO135 TS3_D0/GPIO206 POL EPI AK8 AM26 AM22 AH27 DDCA_DA TXOSD_3N SM_CLK EB_OE_N PCM_OE_N/GPIO126 TS3_D1/GPIO207 GST_A GST DDCA_DA/GPIO9 B_ODD[5]/LVACLKN/[OSD_3-] AG20 AJ23 AK25 TXOSD_3P GCLK B_ODD[4]/LVACLKP/[OSD_3+] SM_RST EB_BE_N1 PCM_IORD_N/GPIO128 TS3_D2/GPIO208 GCLK_A AL25 AL22 AG27 B_ODD[3]/LVA3N/[LOCKN] LOCKAn_Video SM_IO /PCM_CE1 PCM_CE_N/GPIO124 TS3_D3/GPIO209 MCLK_A MCLK AH28 AK24 AK19 AH24 10K 10K 10K 10K 10K 10K 10K 10K EB_WE_N PCM_WE_N/GPIO134 OPT_P 10K 10K TS3_D4/GPIO210 10K 10K SOC_TX GPIO3/TX1/GPIO58 B_ODD[2]/LVA3P/[HTPDN] HTPDAn_Video SM_VCC BIT2_1 BIT10_1 BIT11_1 BIT0_1 BIT1_1 BIT3_1 BIT4_1 BIT5_1 BIT6_1 BIT7_1 BIT8_1 AG21 AH26 BIT9_1 AH29 AL24 SOC_RX GPIO4/RX1 B_ODD[1]/LVA4N/[OSD_LOCKN] LOCKAn_OSD CAM_CD1_N PCM_CD_N/GPIO151 TS3_D5/GPIO211 SOE AA4 AK23 AH16 AJ25 FRC_FLASH_SEL_SOC GPIO23/[TX3]/GPIO78 B_ODD[0]/LVA4P/[OSD_HTPDN] HTPDAn_OSD PCM_RESET PCM_RESET/GPIO150 TS3_D6/GPIO212 FB W6 AJ14 AG26 R119 R112 R125 R128 R132 R135 R138 R140 R142 R146 R105 R148 /TU_RESET2 GPIO24/[RX3]/GPIO79 CAM_REG_N PCM_REG_N/GPIO144 TS3_D7/GPIO213 EO_A E/O F14 AG19 AH25 I2C_SCL6 DIM2/TX4/GPIO112 SM_CD EB_BE_N0 PCM_IOWR_N/GPIO130 TS3_CLK/GPIO216 HCONV F12 AG16 AJ26 BIT0 I2C_SDA6 DIM3/RX4/GPIO113 CAM_WAIT_N PCM_WAIT_N/GPIO140 TS3_VLD/GPIO214 DPM AG24 BIT1 TS3_SYNC/GPIO215 LOCKOUT12 LOCK AJ27 CPU_VID1 GPIO2/GPIO57 BIT2 C7 BIT3 BIT0 EMMC_IO15/[GPIO]/GPIO189 C6 BIT1 EMMC_IO17/[GPIO]/GPIO188 BIT4 AE2 C8 AJ28 GPIO_PM[0]/GPIO10 COMP1_DET EMMC_CMD EMMC_IO9/[EMMC_CMD]/GPIO183 GPIO8/[TS4_D[0]]/GPIO63 FE_DEMOD3_TS_DATA B8 AG28 BIT2 EMMC_IO14/[GPIO]/GPIO185 GPIO5/[TS4_CLK]/GPIO60 FE_DEMOD3_TS_CLK 1K R176 BIT5 U6 A9 AJ29 GPIO_PM[3]/GPIO13 DDTS_RX EMMC_CLK EMMC_IO10/[EMMC_CLK]/GPIO186 GPIO7/[TS4_VLD]/GPIO62 FE_DEMOD3_TS_VAL P4 B7 AG29 BIT6 GPIO_PM[4]/GPIO14 PCM_5V_CTL R175 TCON_I2C_EN BIT3 EMMC_IO16/[GPIO]/GPIO187 GPIO6/[TS4_SYNC]/GPIO61 FE_DEMOD3_TS_SYNC U5 22 B9 GPIO_PM[7]/GPIO17 EMMC_RST EMMC_IO11/[EMMC_RSTN]/GPIO190 AE5 A8 BIT7 PMIC_RESET BIT4 EMMC_IO12/[GPIO]/GPIO184 GPIO_PM[8]/GPIO18 C9 AJ7 AJ5 I2C_SCL3 GPIO28/SCK0/GPIO83 GPIO_PM[9]/GPIO19 COMPENSATION_DONE EMMC_STRB EMMC_IO8/[NAND-DQS]/GPIO191 BIT8 AH8 AG6 B6 I2C_SDA3 EMMC_DATA[0-7] BIT5 EMMC_IO13/[GPIO]/GPIO217 GPIO29/SDA0/GPIO84 GPIO_PM[13]/GPIO23 URSA9_CONNECT E11 BIT9 I2C_SCL1 DDCR_CK/SCK3/GPIO54 EMMC_DATA[6] C10 E10 I2C_SDA1 DDCR_DA/SDA3/GPIO53 EMMC_DATA[7] EMMC_IO6/[EMMC_D6]/GPIO221 AJ6 B11 I2C_SCL2 GPIO30/SCK4/GPIO85 EMMC_DATA[2] EMMC_IO7/[EMMC_D7]/GPIO220 AG8 A11 I2C_SDA2 GPIO31/SDA4/GPIO86 EMMC_DATA[1] EMMC_IO2/[EMMC_D2]/GPIO219 BIT10 AH7 P5 C11 I2C_SCL5 GPIO32/SCK5/GPIO87 GPIO_PM[1]/PM_UART1/GPIO11 /USB_OCD1 EMMC_DATA[0] EMMC_IO1/[EMMC_D1]/GPIO218 AJ8 P6 A12 AL2 BIT11 I2C_SDA5 GPIO33/SDA5/GPIO88 GPIO_PM[5]/PM_UART1/GPIO15 USB_CTL1 EMMC_DATA[3] EMMC_IO0/[EMMC_D0]/GPIO194 VIFP AJ4 B12 AM2 GPIO_PM[11]/PM_UART0/GPIO21 DATA_FORMAT_0_SOC EMMC_DATA[4] EMMC_IO3/[EMMC_D3]/GPIO193 VIFM AH4 C12 GPIO_PM[12]/PM_UART0/GPIO22 DATA_FORMAT_1_SOC EMMC_DATA[5] EMMC_IO4/[EMMC_D4]/GPIO192 B13 AK1 Close to MSTAR DTV_IF EMMC_IO5/[EMMC_D5]/GPIO222 SIFP AK2 10K 10K 10K 10K 10K 10K 10K 10K 10K SIFM 10K 10K 10K L6 G7 R183 100 C103 0.1uF OPT IF_P BIT10_0 BIT11_0 BIT2_0 BIT0_0 BIT1_0 BIT7_0 BIT8_0 BIT9_0 BIT4_0 BIT3_0 BIT5_0 BIT6_0 CPU_VID0 VID0/GPIO50 TESTPIN C107 M6 AK3 100pF CORE_VID0 VID1/GPIO51 IFAGC AD5 R126 LED0 R129 R106 R133 R136 R139 R141 LED0/GPIO29 R143 R147 R149 R113 R120 AD4 LED1 LED1/GPIO30 R184 100 C104 0.1uF OPT IF_N AB5 AJ1 C109 WOL_WAKE_UP_SOC WOL_INT_OUT/[GPIO]/GPIO52 TGPIO0/GPIO157 /USB_OCD3 33pF OPT E13 AJ2 C110 SPI1_DI/GPIO107 HP_DET TGPIO1/GPIO158 USB_CTL3 33pF D12 R4 SPI1_CK/GPIO106 RF_SWITCH_CTL TGPIO2/SCK1/GPIO159 I2C_SCL7 F11 R5 SPI2_DI/GPIO109 L/D_DI_SOC TGPIO3/SDA1/GPIO160 I2C_SDA7 D11 SPI2_CK/GPIO108 L/D_CLK_SOC E12 VSYNC_LIKE/GPIO105 L/D_VSYNC_SOC C101 0.1uF R185 47 D14 AM7 TU_SIF DIM0/GPIO110 SC_DET NC_1 C102 0.1uF R186 47 E14 AL7 R188 DIM1/GPIO111 AV1_CVBS_DET NC_2 C105 300 AM8 1000pF NC_3 ANALOG SIF OPT OPT AK7 NC_4 Close to MSTAR 20150123 version AL5 NC_5 +3.3V_NORMAL BIT(0/1) DVB ATSC JP AM5 GPIO34/GPIO89 CORE_VID1 M7 L100 00 TW/COL US NC_6 PZ1608U121-2R0TF Low High 01 CN/HK KR JP 10 EU BR T-con I2C R182 C106 BIT8 16Kbit 32Kbit 0.1uF BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP Protocol 10K 11 AJJA CI BIT(6/7) B/E(FRC) R187 00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default 0 00 LM14A only BIT9 Division NON_Division 4_Division IF_AGC Low High 01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT 01 N/A C108 BIT4 Display LCD OLED 0.047uF BIT10 Interface EPI Vx1 10 LM14A+URSA11 10 T/C T T/C ATSC 25V ISDB INT 4K@60Hz BIT5 Resolution FHD UHD 11 LM14A+URSA11 11 T2 BIT11 OS(DDR) WebOS Lite WebOS ATSC PIP 4K@120Hz +3.3V_TU +3.3V_LNA_TU +3.3V_NORMAL I2C PULL UP GPIO PULL UP Mstar Debug RS232C_Debug DDTS_Debug +3.3V_NORMAL MSTAR_DEBUG_OLD P101 +3.3V_NORMAL +3.3V_NORMAL DDTS_Debug R100 1.8K R101 1.8K R102 1.8K R103 1.8K R104 1.8K R107 1.8K R114 1.8K R121 1.8K R124 1.8K R127 1.8K R130 1.8K R131 1.8K R134 1.8K R137 1.8K MSTAR_DEBUG_NEW 12505WS-04A00 P100 P102 P103 12507WS-04L 12507WS-04L 12507WS-04L 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K I2C_SDA7 10K 10K 1 OPT I2C for URSA9 (URSA9 Only) OPT I2C_SCL7 OPT OPT 1 1 R152 1 R154 R164 I2C_SDA6 R156 R157 R161 R165 R170 R166 R168 I2C for LCD Module 2 R178 R180 I2C_SCL6 I2C_SDA1 2 SOC_RX 2 I2C for NAVRAM 2 DDTS_RX I2C_SCL1 10K 10K /TU_RESET1 DDCA_CK 3 I2C_SDA3 OPT OPT I2C for Micom RF_SWITCH_CTL 3 3 I2C_SCL3 3 AMP_RESET_N 4 R179 R181 I2C_SDA4 DDCA_DA I2C for Main Amp / Woofer AMP TCON_I2C_EN I2C_SCL4 4 4 SOC_TX 4 /USB_OCD3 5 DDTS_TX I2C_SDA5 I2C for tuner USB_CTL3 I2C_SCL5 5 5 5 /USB_OCD2 I2C_SDA2 USB_CTL2 I2C for tuner&LNB M_RFModule_RESET AR100 I2C_SCL2 33 PCM_5V_CTL I2C_SDA_MICOM I2C_SDA3 I2C_SCL_MICOM I2C_SCL3 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-001_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-23 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 01 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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IC100 LGE5332(LM14A) WOL POWER ENABLE CONTROL +1.1V_VDDC_CPU +1.1V_VDDC +1.1V_VDDC 1st layer 4th layer +1.1V_Bypass Cap(CLOSE TO CHIP SIDE) J9 AC17 VDDC_1 VDDC_24 J10 AC18 BOTTOM_CAP_FOR_RIPPLE +1.1V_VDDC DVDD_DDR11 VDDC_2 VDDC_25 +3.5V_ST 0.1uF 0.1uF J11 AC19 +3.5V_WOL BOTTOM_CAP_FOR_RIPPLE 0.1uF 10uF VDDC_3 VDDC_26 IC201 4th layer J12 AC20 C263 C323 L226 VDDC_4 VDDC_27 AP2151WG-7 J13 AC21 10uF C208 0.1uF PZ1608U121-2R0TF VDDC_5 VDDC_28 10V 10uF 16V C322 PZ1608U121-2R0TF C276 C278 K9 AC22 C299 VDDC_6 VDDC_29 L203 10V K10 AD17 IN OUT K11 VDDC_7 VDDC_30 AD18 +3.3V_NORMAL 5 1 2A C324 C257 VDDC_8 VDDC_31 C242 R204 K12 AD19 0.47uF 0.47uF VDDC_9 VDDC_32 0.1uF GND 10K K13 AD20 2 6.3V 6.3V VDDC_10 VDDC_33 R203 OPT L9 AD21 Close to chip side VDDC_11 VDDC_34 1K L10 AD22 WOL_CTL 0 R202 OPT EN FLG VDDC_12 VDDC_35 4 3 L11 AE19 Close to chip side VDDC_13 VDDC_36 L12 AE20 VDDC_14 VDDC_37 R11 AE21 VDDC_15 VDDC_38 R12 AE22 VDDC_16 VDDC_39 Close to chip side R13 VDDC_17 +1.1V_VDDC T11 AE31 VDDC_18 VDD_SRAM_1 T12 AC24 1st layer 4th layer VDDC_19 VDD_SRAM_2 AVDDL_MOD11 T13 AD23 VDDC_20 VDD_SRAM_3 4th layer U11 AVDD_DMPLL VDDC_21 BOTTOM_CAP_FOR_RIPPLE U12 AE30 L202 BOTTOM_CAP_FOR_RIPPLE 0.1uF 0.1uF 0.1uF VDDC_22 CTRL_SRAMLDO PZ1608U121-2R0TF 10uF U13 1st layer 4th layer VDDC_23 C205 C261 10uF 0.1uF AVDDL_MOD11 A6 AVDD_DMPLL 10V 16V 2A C250 C230 C234 C235 EMMC_CTRL C320 W21 C238 0.1uF AVDDL_PREDRV_1 0.47uF 0.47uF 0.1uF Y21 6.3V AVDDL_PREDRV_2 6.3V AD29 V7 AVDDL_PREDRV_3 AVDD_NODIE 0.1uF AD30 DVDD_DDR11 C244 AVDDL_MOD_1 C245 W20 AVDD15_MOD AVDDL_MOD_2 Close to chip side Y20 L7 AVDDL_MOD_3 AVDDL_MHL3_1 AVDDP3P3_MHL U19 N12 C227 AVDD15_MOD_1 AVDDL_MHL3_2 Close to chip side V19 R7 AVDD15_MOD_2 AVDD3P3_MHL3_1 DVDD_DDR11 AA13 T7 AVDDL_USB3_1 AVDD3P3_MHL3_2 Close to chip side AF11 AVDD33_ADC AVDDL_USB3_2 AVDD_DMPLL U21 Y7 VDDC_CPU_1 AVDD3P3_ETH Close to chip side U22 AB7 +1.1V_VDDC_CPU VDDC_CPU_2 AVDD3P3_DADC_1 U23 AB8 VDDC_CPU_3 AVDD3P3_DADC_2 U24 AA7 +3.5V_WOL VDDC_CPU_4 AVDD3P3_ADC_1 AVDD_DMPLL U25 AA8 IC200 VDDC_CPU_5 AVDD3P3_ADC_2 V23 G9 AP2121N-3.3TRE1 V24 VDDC_CPU_6 AVDD3P3_USB_1 G10 AVDD_DMPLL +1.5V_Bypass Cap VDDC_CPU_7 AVDD3P3_USB_2 +1.5V_DDR AVDD_DDR V25 AB15 VIN 3 2 VOUT VDDC_CPU_8 AVDD3P3_USB3_1 W23 AF13 AVDD_AU33 VDDC_CPU_9 AVDD3P3_USB3_2 AVDDP3P3 1 W24 AD7 L227 VDDC_CPU_10 AVDD_AU33 GND PZ1608U121-2R0TF W25 AE7 VDDC_CPU_11 AVDD_EAR33 C246 1st layer 4th layer Y23 AF8 C243 1uF VDDC_CPU_12 AVDD3P3_DMPLL 0.1uF AVDD_DDR AVDD15_MOD Y24 AE15 10V L200 VDDC_CPU_13 VDDP_1 16V Y25 AF15 2A 0.47uF VDDC_CPU_14 VDDP_2 PZ1608U121-2R0TF 0.1uF 0.1uF 0.1uF 0.1uF AA22 0.1uF 0.1uF 0.1uF VDDC_CPU_15 L224 AA23 AA24 VDDC_CPU_16 V17 4A C207 10uF C201 10uF C247 C316 10uF C223 10uF C248 0.47uF C249 0.47uF AVDD_DMPLL 0.47uF VDDC_CPU_17 AVDD_MOD_1 10V 10V 6.3V PZ1608U121-2R0TF C314 0.1uF 10V 10V 6.3V 0.1uF AA25 V18 C209 C224 C225 C226 6.3V C203 C204 C287 VDDC_CPU_18 AVDD_MOD_2 AB24 W19 WOL_WAKE_UP VDDC_CPU_19 AVDD_LPLL_1 R205 AB25 Y19 VDDC_CPU_20 AVDD_LPLL_2 10K C307 C308 0 R169 AE16 WOL_WAKE_UP WOL_WAKE_UP_SOC MCP_VDDC_1 WOL_WAKE_UP AF16 N15 MCP_VDDC_2 AVDD_PLL_A N16 Close to chip side AVDD_PLL_B Close to chip side DVDD_NODIE VDDP_NAND_A VDDP_NAND_C L13 DVDD_NODIE DVDD_DDR11 H16 VDDP_3318_A/[3.3V/1.8V] K21 K16 C200 DVDD_DDR_1 VDDP_3318_C/[3.3V/1.8V] N21 AVDD_DDR 1uF DVDD_DDR_2 25V M21 J21 DVDD_DDR_3 AVDD_DDR_A_1 L21 K17 DVDD_DDR_4 AVDD_DDR_A_2 K18 AVDD_DDR_A_3 K19 AVDD_DDR_A_4 L17 AVDD_DDR_A_5 L19 AVDD_DDR_A_6 L20 AVDD_DDR_A_7 AVDD_DDR_B_1 J23 K22 GND JIG POINT +3.3V_Bypass Cap AVDD_DDR_B_2 K23 AVDD_DDR_B_3 M22 AVDD_DDR_B_4 N22 AVDD_DDR_B_5 4th layer JP202 JP204 JP205 JP203 N23 AVDD_DDR_B_6 +3.3V_NORMAL AVDDP3P3 P23 +3.3V_NORMAL AVDD_DDR_B_7 AVDD33_ADC 1st layer 4th layer L215 L221 PZ1608U121-2R0TF BOTTOM_CAP_FOR_RIPPLE BOTTOM_CAP_FOR_RIPPLE BOTTOM_CAP_FOR_RIPPLE L18 PZ1608U121-2R0TF 0.1uF AVDD_DDR_LDO_A 0.47uF L22 0.1uF AVDD_DDR_LDO_B C294 C295 AVDD5V_MHL 2A 1uF 1uF C251 0.47uF C252 0.47uF C222 2A C256 C217 25V 25V 6.3V 6.3V 10uF C268 10uF 10uF C274 H7 10V 10V C311 C253 10uF 10V AVDD_HDMI_5V_PA 10V R201 0 AVDD_DDR G8 GND_EFUSE 0.1uF Close to chip side C14 C229 AVDD_DDR_VBP_A_1 0.47uF C210 B14 +3.3V_NORMAL VDDP_NAND_C 5V_HDMI_1 AVDD5V_MHL AVDD_DDR_VBP_A_2 0 J17 Close to chip side Close to chip side AVDD_DDR_VBP_A_3 R207 J18 0.47uF C211 non_HDMI_LEAK AVDD_DDR_VBP_A_4 0.1uF R200 4th layer L208 10 B15 PZ1608U121-2R0TF AVDD_DDR_VBN_A_1 0.47uF C212 C15 AVDD_AU33 AVDD_DDR_VBN_A_2 C219 J19 +5V_NORMAL 4th layer AVDD_DDR_VBN_A_3 J20 0.47uF C213 2A C260 C266 0.1uF L219 HDMI_LEAK AVDD_DDR_VBN_A_4 10uF PZ1608U121-2R0TF R206 BOTTOM_CAP_FOR_RIPPLE 10K AVDDP3P3_MHL 10V AC30 C292 G AVDD_DDR_VBP_B_1 0.47uF C214 AVDD_DDR_VBP_B_2 AC31 K24 2A 0.47uF 6.3V L201 PZ1608U121-2R0TF BOTTOM_CAP_FOR_RIPPLE AVDD_DDR_VBP_B_3 0.47uF C215 S D L24 AVDD_DDR_VBP_B_4 0.1uF RUE003N02 C240 C241 0.1uF 0.47uF AD31 Q200 D VISHAY_HDMI_LEAK 6.3V AVDD_DDR_VBN_B_1 ROHM_HDMI_LEAK BOTTOM_CAP_FOR_RIPPLE AD32 C216 Q200-*1 AVDD_DDR_VBN_B_2 0.47uF VDDP_NAND_A G C221 L23 SI1012CR-T1-GE3 AVDD_DDR_VBN_B_3 Close to chip side M24 +1.8V S AVDD_DDR_VBN_B_4 0.47uF C220 L209 PZ1608U121-2R0TF Close to chip side 2A C236 C239 0.1uF 10uF 10V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-002_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-12-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2_POWER 2 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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DDR_VTT DDR_VTT AR400 AR407 M0_DDR_VREFDQ 56 56 Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ 1/16W 1/16W IC400 IC401 C424 0.1uF C453 0.1uF M0_DDR_A14 M1_DDR_A14 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M0_DDR_A8 M1_DDR_A8 M0_DDR_A11 M1_DDR_A11 EAN63053201 EAN63053201 C425 0.1uF C454 0.1uF M0_DDR_A6 M1_DDR_A6 M0_DDR_A0 N3 A0 DDR3 VREFCA M8 M0_DDR_A0 N3 A0 DDR3 VREFCA M8 AR401 AR408 P7 P7 4Gbit 56 56 M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1 1/16W 1/16W P3 P3 M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) C426 0.1uF C455 0.1uF N2 H1 N2 H1 M0_DDR_A1 M1_DDR_A1 M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ P8 P8 M0_DDR_A4 M1_DDR_A4 M0_DDR_A4 A4 M0_DDR_A4 A4 P2 P2 M0_DDR_A12 M1_DDR_A12 M0_DDR_A5 A5 M0_DDR_A5 A5 C427 0.1uF C456 0.1uF R8 L8 R400 240 R8 L8 R403 240 M0_DDR_BA1 M1_DDR_BA1 M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ R2 AVDD_DDR R2 AR402 AR409 M0_DDR_A7 A7 M0_DDR_A7 A7 AVDD_DDR T8 T8 56 56 M0_DDR_A8 A8 M0_DDR_A8 A8 1/16W 1/16W R3 B2 R3 B2 C428 0.1uF C457 0.1uF M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1 L7 D9 L7 D9 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A13 M1_DDR_A13 R7 G7 R7 G7 DDR3 1.5V bypass Cap - Place these caps near Memory DDR3 1.5V bypass Cap - Place these caps near Memory M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 N7 K2 N7 K2 M0_DDR_A9 M1_DDR_A9 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 C429 0.1uF C458 0.1uF A12/BC VDD_4 M0_DDR_A7 M1_DDR_A7 T3 K8 T3 K8 M0_DDR_A13 A13 VDD_5 M0_DDR_A13 A13 VDD_5 T7 N1 T7 N1 AR403 AR410 M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 56 56 M7 N9 M7 N9 1/16W 1/16W M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7 R1 R1 C430 0.1uF C459 0.1uF VDD_8 VDD_8 M0_DDR_A2 M1_DDR_A2 M2 R9 M2 R9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_A5 M1_DDR_A5 N8 N8 M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_A3 M1_DDR_A3 M3 M3 C431 0.1uF C460 0.1uF M0_DDR_BA2 BA2 M0_DDR_BA2 BA2 M0_DDR_A0 M1_DDR_A0 A1 A1 VDDQ_1 VDDQ_1 AR404 AR411 J7 A8 J7 A8 M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 56 56 K7 C1 K7 C1 1/16W 1/16W M0_D_CLKN CK VDDQ_3 M0_D_CLKN CK VDDQ_3 C432 0.1uF C461 0.1uF K9 C9 K9 C9 M0_DDR_BA0 M1_DDR_BA0 M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 D2 D2 M0_DDR_BA2 M1_DDR_BA2 VDDQ_5 VDDQ_5 L2 E9 L2 E9 M0_DDR_A15 M1_DDR_A15 M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 C433 0.1uF C462 0.1uF K1 F1 K1 F1 M0_DDR_A10 M1_DDR_A10 M0_DDR_ODT ODT VDDQ_7 M0_DDR_ODT ODT VDDQ_7 J3 H2 C410 0.1uF J3 H2 C440 0.1uF M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 AR405 AR412 K3 H9 C411 0.1uF K3 H9 C441 0.1uF 56 56 M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 1/16W 1/16W L3 L3 M0_DDR_WEN WE M0_DDR_WEN WE C434 0.1uF C463 0.1uF J1 J1 M0_DDR_WEN M1_DDR_WEN NC_1 NC_1 T2 J9 T2 J9 M0_DDR_CASN M1_DDR_CASN M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N RESET NC_2 IC100 L1 L1 M0_DDR_ODT M1_DDR_ODT NC_3 NC_3 C435 0.1uF C464 0.1uF LGE5332(LM14A) L9 L9 M0_DDR_RASN M1_DDR_RASN NC_4 NC_4 F3 F3 AR406 AR413 M0_DDR_DQS0 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n G3 IC400-*1 IC400-*2 G3 IC401-*1 K4B4G1646D-BCMA IC401-*2 SS_DDR3_2Gb IC401-*3 Hynix_DDR3_2Gb IC401-*4 56 56 K4B4G1646D-BCMA H5TQ4G63CFR_RDC H5TQ4G63CFR_RDC M0_DDR_DQS_N0 DQSL M0_DDR_DQS_N2 DQSL EAN63391401 K4B2G1646Q-BCMA H5TQ2G63FFR-RDC 1/16W 1/16W EAN63391401 EAN63053202 N3 M8 EAN63053202 F17 H28 N3 P7 A0 VREFCA M8 N3 P7 A0 VREFCA M8 P7 A0 A1 VREFCA N3 P7 A0 VREFCA M8 N3 EAN63667401 M8 N3 EAN63648701 M8 C436 0.1uF C465 0.1uF M0_DDR_A0 IO[3]/A-A0[AB-A0]/A-A6 IO[75]/B-A0[CD-A0]/B-A6 M1_DDR_A0 C7 A9 P3 A1 A2 P3 A1 A2 C7 A9 P3 N2 A2 H1 P3 A1 A2 P7 A0 A1 VREFCA P7 A0 A1 VREFCA M0_DDR_CKE M1_DDR_CKE C17 K31 M0_DDR_DQS1 DQSU N2 A3 VREFDQ H1 N2 A3 VREFDQ H1 M0_DDR_DQS3 P8 A3 A4 VREFDQ N2 A3 VREFDQ H1 P3 A2 P3 A2 M0_DDR_A1 IO[2]/A-A1[AB-A1]/A-A5 IO[80]/B-A1[CD-A1]/B-A5 M1_DDR_A1 VSS_1 P8 P2 A4 P8 P2 A4 DQSU VSS_1 P2 R8 A5 L8 P8 P2 A4 N2 P8 A3 VREFDQ H1 N2 P8 A3 VREFDQ H1 E17 J29 B7 B3 R8 A5 A6 ZQ L8 R8 A5 A6 ZQ L8 B7 B3 R2 A6 A7 ZQ R8 A5 A6 ZQ L8 P2 A4 A5 P2 A4 A5 M0_DDR_A2 IO[8]/A-A2[AB-A2]/A-A8 M1_DDR_A2 M0_DDR_DQS_N1 DQSU VSS_2 R2 A7 R2 A7 M0_DDR_DQS_N3 DQSU VSS_2 T8 A8 R2 A7 R8 R2 A6 ZQ L8 R8 R2 A6 ZQ L8 M0_D_CLKN M1_D_CLKN IO[83]/B-A2[CD-A2]/B-A8 E1 T8 R3 A8 B2 T8 R3 A8 B2 E1 R3 L7 A9 VDD_1 B2 D9 T8 R3 A8 B2 T8 A7 T8 A7 F18 K27 L7 A9 VDD_1 D9 L7 A9 VDD_1 D9 R7 A10/AP VDD_2 G7 L7 A9 VDD_1 D9 R3 A8 B2 R3 A8 B2 C437 0.1uF C466 0.1uF M0_DDR_A3 IO[12]/A-A3[AB-A3]/A-A4 IO[79]/B-A3[CD-A3]/B-A4 M1_DDR_A3 VSS_3 R7 A10/AP A11 VDD_2 VDD_3 G7 R7 A10/AP A11 VDD_2 VDD_3 G7 VSS_3 N7 A11 A12/BC VDD_3 VDD_4 K2 R7 A10/AP A11 VDD_2 VDD_3 G7 L7 A9 A10/AP VDD_1 VDD_2 D9 L7 A9 A10/AP VDD_1 VDD_2 D9 M0_D_CLK M1_D_CLK B18 K30 E7 G8 N7 T3 A12/BC VDD_4 K2 K8 N7 T3 A12/BC VDD_4 K2 K8 E7 G8 T3 A13 VDD_5 K8 N1 N7 T3 A12/BC VDD_4 K2 K8 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 M0_DDR_A4 M1_DDR_A4 M0_DDR_DM0 DML VSS_4 A13 VDD_5 VDD_6 N1 T7 A13 A14 VDD_5 VDD_6 N1 M0_DDR_DM2 DML VSS_4 M7 VDD_6 N9 T7 A13 A14 VDD_5 VDD_6 N1 T3 A13 VDD_5 K8 T3 A13 VDD_5 K8 IO[11]/A-A4[AB-A4]/A-BA1 IO[87]/B-A4[CD-A4]/B-BA1 D3 J2 M7 NC_5 VDD_7 N9 R1 M7 NC_5 VDD_7 N9 R1 D3 J2 NC_5 VDD_7 VDD_8 R1 M7 NC_5 VDD_7 N9 R1 M7 VDD_6 N1 N9 T7 M7 A14 VDD_6 N1 N9 E18 J28 M0_DDR_DM1 DMU M2 VDD_8 R9 M2 VDD_8 R9 M0_DDR_DM3 M2 BA0 VDD_9 R9 M2 VDD_8 R9 NC_5 VDD_7 R1 NC_5 VDD_7 R1 M0_DDR_A5 IO[14]/A-A5[AB-A5]/A-A0 IO[86]/B-A5[CD-A5]/B-A0 M1_DDR_A5 VSS_5 N8 BA0 VDD_9 N8 BA0 VDD_9 DMU VSS_5 N8 M3 BA1 N8 BA0 VDD_9 M2 BA0 VDD_8 VDD_9 R9 M2 BA0 VDD_8 VDD_9 R9 A17 K32 J8 M3 BA1 BA2 A1 M3 BA1 BA2 A1 J8 J7 BA2 VDDQ_1 A1 A8 M3 BA1 BA2 A1 N8 M3 BA1 N8 M3 BA1 M0_DDR_A6 IO[10]/A-A6[AB-A6]/A-A1 IO[90]/B-A6[CD-A6]/B-A1 M1_DDR_A6 VSS_6 J7 CK VDDQ_1 VDDQ_2 A8 J7 CK VDDQ_1 VDDQ_2 A8 VSS_6 K7 CK CK VDDQ_2 VDDQ_3 C1 J7 CK VDDQ_1 VDDQ_2 A8 BA2 VDDQ_1 A1 BA2 VDDQ_1 A1 D17 H31 E3 M1 K7 K9 CK VDDQ_3 C1 C9 K7 K9 CK VDDQ_3 C1 C9 E3 M1 K9 CKE VDDQ_4 C9 D2 K7 K9 CK VDDQ_3 C1 C9 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 M0_DDR_A7 M1_DDR_A7 M0_DDR_DQ0 DQL0 VSS_7 CKE VDDQ_4 VDDQ_5 D2 CKE VDDQ_4 VDDQ_5 D2 M0_DDR_DQ16 DQL0 VSS_7 L2 VDDQ_5 E9 CKE VDDQ_4 VDDQ_5 D2 K9 CKE VDDQ_4 C9 K9 CKE VDDQ_4 C9 IO[13]/A-A7[AB-A7]/A-A2 IO[78]/B-A7[CD-A7]/B-A2 F7 M9 L2 K1 CS VDDQ_6 E9 F1 L2 K1 CS VDDQ_6 E9 F1 F7 M9 K1 CS ODT VDDQ_6 VDDQ_7 F1 L2 K1 CS VDDQ_6 E9 F1 L2 VDDQ_5 D2 E9 L2 VDDQ_5 D2 E9 C16 J32 M0_DDR_DQ1 DQL1 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 M0_DDR_DQ17 J3 RAS VDDQ_8 H2 J3 ODT VDDQ_7 H2 K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1 M0_DDR_A8 IO[0]/A-A8[AB-A8]/A-A9 IO[77]/B-A8[CD-A8]/B-A9 M1_DDR_A8 VSS_8 K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 DQL1 VSS_8 K3 L3 CAS VDDQ_9 H9 K3 RAS VDDQ_8 H9 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 AVDD_DDR E16 G30 F2 P1 L3 CAS WE VDDQ_9 J1 L3 CAS WE VDDQ_9 J1 F2 P1 T2 WE NC_1 J1 J9 L3 CAS WE VDDQ_9 J1 K3 L3 RAS CAS VDDQ_8 VDDQ_9 H9 K3 L3 RAS CAS VDDQ_8 VDDQ_9 H9 M0_DDR_CKE M0_DDR_A9 M1_DDR_A9 M0_DDR_DQ2 DQL2 VSS_9 T2 NC_1 J9 T2 NC_1 J9 M0_DDR_DQ18 DQL2 VSS_9 RESET NC_2 L1 T2 NC_1 J9 WE J1 WE J1 IO[5]/A-A9[AB-A9]/A-A11 IO[73]/B-A9[CD-A9]/B-A11 F8 P9 RESET NC_2 NC_3 L1 RESET NC_2 NC_3 L1 F8 P9 NC_3 L9 RESET NC_2 NC_3 L1 T2 RESET NC_1 NC_2 J9 T2 RESET NC_1 NC_2 J9 B19 L30 M0_DDR_DQ3 DQL3 NC_4 L9 NC_4 L9 M0_DDR_DQ19 F3 DQSL NC_4 NC_6 T7 NC_4 L9 NC_3 L1 NC_3 L1 M0_DDR_A10 IO[9]/A-A10[AB-A10]/A-RASZ IO[93]/B-A10[CD-A10]/B-RASZ M1_DDR_A10 VSS_10 F3 G3 DQSL NC_6 T7 F3 G3 DQSL DQL3 VSS_10 G3 DQSL F3 G3 DQSL F3 NC_4 L9 T7 F3 NC_4 L9 H3 T1 1K R418 B17 J30 DQSL DQSL H3 T1 C7 DQSU VSS_1 A9 DQSL G3 DQSL DQSL NC_6 G3 DQSL DQSL M0_DDR_DQ4 AVDD_DDR OPT C7 A9 C7 A9 M0_DDR_DQ20 C7 A9 1K R405 M0_DDR_A11 IO[6]/A-A11[AB-A11]/A-A7 IO[84]/B-A11[CD-A11]/B-A7 M1_DDR_A11 DQL4 VSS_11 B7 DQSU VSS_1 B3 B7 DQSU VSS_1 B3 DQL4 VSS_11 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_1 B3 C7 DQSU VSS_1 A9 C7 DQSU VSS_1 A9 AVDD_DDR D20 L29 H8 T9 E7 DQSU VSS_2 VSS_3 E1 G8 E7 DQSU VSS_2 VSS_3 E1 G8 H8 T9 E7 D3 DML VSS_3 VSS_4 G8 J2 E7 DQSU VSS_2 VSS_3 E1 G8 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_2 B3 E1 M0_DDR_A12 IO[26]/A-A12[AB-A12]/A-BG0 M1_DDR_A12 M0_DDR_DQ5 DQL5 VSS_12 D3 DML VSS_4 J2 D3 DML VSS_4 J2 M0_DDR_DQ21 DQL5 VSS_12 DMU VSS_5 J8 D3 DML VSS_4 J2 E7 VSS_3 G8 E7 VSS_3 G8 IO[85]/B-A12[CD-A12]/B-BG0 G2 DMU VSS_5 VSS_6 J8 DMU VSS_5 VSS_6 J8 G2 E3 VSS_6 M1 DMU VSS_5 VSS_6 J8 D3 DML DMU VSS_4 VSS_5 J2 D3 DML DMU VSS_4 VSS_5 J2 F16 G31 M0_DDR_DQ6 DQL6 E3 DQL0 VSS_7 M1 E3 DQL0 VSS_7 M1 M0_DDR_DQ22 F7 DQL0 DQL1 VSS_7 VSS_8 M9 E3 DQL0 VSS_7 M1 VSS_6 J8 VSS_6 J8 M0_1_DDR_VREFDQ M0_DDR_A13 IO[4]/A-A13[AB-A13]/A-PARITY IO[74]/B-A13[CD-A13]/B-PARITY M1_DDR_A13 F7 F2 DQL1 VSS_8 M9 P1 F7 F2 DQL1 VSS_8 M9 P1 DQL6 F2 F8 DQL2 VSS_9 P1 P9 F7 F2 DQL1 VSS_8 M9 P1 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 B16 J31 H7 F8 DQL2 DQL3 VSS_9 VSS_10 P9 F8 DQL2 DQL3 VSS_9 VSS_10 P9 H7 H3 DQL3 DQL4 VSS_10 VSS_11 T1 F8 DQL2 DQL3 VSS_9 VSS_10 P9 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 M0_DDR_VREFDQ M0_DDR_RESET_N M0_DDR_A14 IO[7]/A-A14[AB-A14]/A-A13 M1_DDR_A14 M0_DDR_DQ7 DQL7 H3 DQL4 VSS_11 T1 H3 DQL4 VSS_11 T1 M0_DDR_DQ23 DQL7 H8 DQL5 VSS_12 T9 H3 DQL4 VSS_11 T1 F8 H3 DQL3 VSS_10 P9 T1 F8 H3 DQL3 VSS_10 P9 T1 IO[81]/B-A14[CD-A14]/B-A13 B1 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 B1 G2 H7 DQL6 H8 G2 DQL5 VSS_12 T9 H8 DQL4 VSS_11 T9 H8 DQL4 VSS_11 T9 E20 M28 DQL5 VSS_12 DQL5 VSS_12 R416 DQL6 DQL6 DQL6 1K 1% H7 H7 DQL7 H7 G2 G2 B1 M0_DDR_A15 VSSQ_1 DQL7 DQL7 VSSQ_1 VSSQ_1 DQL7 DQL6 DQL6 R410 1K 1% B1 B1 B1 H7 H7 IO[19]/A-A15[AB-A15]/A-A3 IO[96]/B-A15[CD-A15]/B-A3 M1_DDR_A15 D7 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 B9 D7 C3 DQU0 VSSQ_2 B9 D1 D7 DQU0 VSSQ_1 VSSQ_2 B9 DQL7 VSSQ_1 B1 DQL7 VSSQ_1 B1 1% E19 L28 M0_DDR_DQ8 DQU0 C3 DQU1 VSSQ_3 D1 C3 DQU1 VSSQ_3 D1 M0_DDR_DQ24 C8 DQU1 DQU2 VSSQ_3 VSSQ_4 D8 C3 DQU1 VSSQ_3 D1 D7 DQU0 VSSQ_2 B9 D7 DQU0 VSSQ_2 B9 10K M0_DDR_BA0 IO[24]/A-BA0[AB-BA0]/A-A10 IO[88]/B-BA0[CD-BA0]/B-A10 M1_DDR_BA0 VSSQ_2 C8 C2 DQU2 VSSQ_4 D8 E2 C8 C2 DQU2 VSSQ_4 D8 E2 DQU0 VSSQ_2 C2 A7 DQU3 VSSQ_5 E2 E8 C8 C2 DQU2 VSSQ_4 D8 E2 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C18 L31 C3 D1 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 C3 D1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 R445 M0_DDR_BA1 M1_DDR_BA1 M0_DDR_DQ9 DQU1 VSSQ_3 A2 DQU5 VSSQ_7 F9 A2 DQU5 VSSQ_7 F9 M0_DDR_DQ25 DQU1 VSSQ_3 B8 DQU6 VSSQ_8 G1 A2 DQU5 VSSQ_7 F9 A7 A2 DQU4 VSSQ_6 E8 F9 A7 A2 DQU4 VSSQ_6 E8 F9 IO[20]/A-BA1[AB-BA1]/A-CASZ IO[92]/B-BA1[CD-BA1]/B-CASZ C8 D8 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 C8 D8 A3 DQU7 VSSQ_9 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 DQU5 VSSQ_7 G1 B8 DQU5 VSSQ_7 G1 F19 K28 M0_DDR_DQ10 DQU2 DQU7 VSSQ_9 DQU7 VSSQ_9 M0_DDR_DQ26 DQU7 VSSQ_9 A3 DQU6 VSSQ_8 G9 A3 DQU6 VSSQ_8 G9 M0_DDR_BA2 IO[21]/A-BA2[AB-BA2]/A-BA0 IO[82]/B-BA2[CD-BA2]/B-BA0 M1_DDR_BA2 VSSQ_4 DQU2 VSSQ_4 DQU7 VSSQ_9 DQU7 VSSQ_9 C479 G22 N28 C2 E2 C2 E2 C472 M0_D_CLK 1% M0_DDR_RASN M1_DDR_RASN M0_DDR_DQ11 DQU3 VSSQ_5 M0_DDR_DQ27 DQU3 VSSQ_5 0.1uF 1% IO[15]/A-RASZ[AB-RASZ]/A-ODT IO[97]/B-RASZ[CD-RASZ]/B-ODT A7 E8 A7 E8 0.1uF C483 R412 F21 N27 R417 M0_DDR_DQ12 DQU4 VSSQ_6 M0_DDR_DQ28 DQU4 VSSQ_6 C474 56 C477 R411 M0_DDR_CASN IO[17]/A-CASZ[AB-CASZ]/A-WEZ IO[94]/B-CASZ[CD-CASZ]/B-WEZ M1_DDR_CASN A2 F9 A2 F9 1000pF 0.01uF E21 L27 M0_DDR_DQ13 DQU5 M0_DDR_DQ29 1000pF 50V 1% M0_DDR_WEN M1_DDR_WEN VSSQ_7 DQU5 VSSQ_7 1K IO[16]/A-WEZ[AB-WEZ]/A-A12 IO[89]/B-WEZ[CD-WEZ]/B-A12 B8 G1 B8 G1 50V 50V 1K F20 M27 M0_DDR_DQ14 DQU6 M0_DDR_DQ30 M0_DDR_ODT IO[25]/A-ODT[AB-ODT]/A-ACTZ IO[95]/B-ODT[CD-ODT]/B-ACTZ M1_DDR_ODT VSSQ_8 DQU6 VSSQ_8 C19 M31 A3 G9 A3 G9 R413 M0_DDR_CKE IO[18]/A-CKE[AB-CKE]/A-CKE M1_DDR_CKE M0_DDR_DQ15 DQU7 VSSQ_9 SS_DDR3_2Gb Hynix_DDR3_2Gb M0_DDR_DQ31 DQU7 VSSQ_9 56 IO[91]/B-CKE[CD-CKE]/B-CKE IC400-*3 K4B2G1646Q-BCMA IC400-*4 H5TQ2G63FFR-RDC F15 G32 1% M0_DDR_RESET_N IO[1]/A-RST[AB-RST]/A-RST IO[76]/B-RST[CD-RST]/B-RST M1_DDR_RESET_N N3 EAN63667401 M8 N3 EAN63648701 M8 A20 N32 P7 A0 A1 VREFCA P7 A0 A1 VREFCA M0_D_CLK IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ M1_D_CLK P3 N2 A2 H1 P3 N2 A2 H1 B20 M30 P8 P2 A3 A4 VREFDQ P8 P2 A3 A4 VREFDQ M0_D_CLKN M0_D_CLKN IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK M1_D_CLKN R8 A5 A6 ZQ L8 R8 A5 A6 ZQ L8 E15 G29 R2 T8 A7 R2 T8 A7 M0_DDR_CS1 IO[23]/A-CSB1[AB-CSB1]/A-CSB1 IO[99]/B-CSB1[CD-CSB1]/B-CSB1 M1_DDR_CS1 R3 L7 A8 A9 VDD_1 B2 D9 R3 L7 A8 A9 VDD_1 B2 D9 D15 F32 R7 A10/AP A11 VDD_2 VDD_3 G7 R7 A10/AP A11 VDD_2 VDD_3 G7 M0_DDR_CS2 IO[22]/A-CSB2[AB-CSB2]/A-CSB2 IO[98]/B-CSB2[CD-CSB2]/B-CSB2 M1_DDR_CS2 N7 T3 A12/BC VDD_4 K2 K8 N7 T3 A12/BC VDD_4 K2 K8 M7 A13 NC_5 VDD_5 VDD_6 VDD_7 N1 N9 T7 M7 A13 A14 NC_5 VDD_5 VDD_6 VDD_7 N1 N9 AVDD_DDR M1_DDR_CKE R1 R1 VDD_8 VDD_8 M2 R9 M2 R9 BA0 VDD_9 BA0 VDD_9 N8 N8 BA1 BA1 M3 M3 BA2 BA2 A1 A1 C23 T31 J7 CK VDDQ_1 VDDQ_2 A8 J7 CK VDDQ_1 VDDQ_2 A8 M0_DDR_DQ0 M1_DDR_DQ0 K7 C1 K7 C1 AVDD_DDR 1K R433 IO[47]/A-DQ[0][A-DQL0]/A-DQ[0] IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] K9 CK VDDQ_3 C9 K9 CK VDDQ_3 C9 AVDD_DDR B22 P30 CKE VDDQ_4 VDDQ_5 D2 CKE VDDQ_4 VDDQ_5 D2 M0_DDR_DQ1 IO[31]/A-DQ[1][A-DQL1]/A-DQ[1] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] M1_DDR_DQ1 L2 E9 L2 E9 +1.5V_Bypass Cap CS VDDQ_6 CS VDDQ_6 K1 F1 K1 F1 OPT 1K R422 +1.5V_Bypass Cap ODT VDDQ_7 ODT VDDQ_7 B24 T30 J3 K3 RAS VDDQ_8 H2 H9 J3 K3 RAS VDDQ_8 H2 H9 M1_1_DDR_VREFDQ M0_DDR_DQ2 IO[48]/A-DQ[2][A-DQL2]/A-DQ[2] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] M1_DDR_DQ2 L3 CAS WE VDDQ_9 L3 CAS WE VDDQ_9 C21 P31 NC_1 J1 NC_1 J1 M1_DDR_VREFDQ M0_DDR_DQ3 B25 IO[29]/A-DQ[3][A-DQL3]/A-DQ[3] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3] U30 M1_DDR_DQ3 Close to DDR Power Pin T2 F3 RESET NC_2 NC_3 NC_4 J9 L1 L9 T7 T2 F3 RESET NC_2 NC_3 NC_4 J9 L1 L9 Close to DDR Power Pin R414 1K 1% DQSL NC_6 DQSL R408 1K 1% M0_DDR_DQ4 IO[50]/A-DQ[4][A-DQL4]/A-DQ[6] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] M1_DDR_DQ4 G3 DQSL G3 DQSL M1_DDR_RESET_N C20 N31 C7 B7 DQSU VSS_1 A9 B3 C7 B7 DQSU VSS_1 A9 B3 M0_DDR_DQ5 IO[30]/A-DQ[5][A-DQL5]/A-DQ[7] IO[105]/B-DQ[5][C-DQL5]/B-DQ[7] M1_DDR_DQ5 E7 DQSU VSS_2 VSS_3 E1 G8 E7 DQSU VSS_2 VSS_3 E1 G8 C24 U31 R446 DML VSS_4 DML VSS_4 D3 J2 D3 J2 DMU VSS_5 DMU VSS_5 M0_DDR_DQ6 M1_DDR_DQ6 10K J8 J8 IO[49]/A-DQ[6][A-DQL6]/A-DQ[4] IO[122]/B-DQ[6][C-DQL6]/B-DQ[4] E3 VSS_6 M1 E3 VSS_6 M1 1% B21 N30 F7 DQL0 DQL1 VSS_7 VSS_8 M9 F7 DQL0 DQL1 VSS_7 VSS_8 M9 AVDD_DDR M0_DDR_DQ7 IO[32]/A-DQ[7][A-DQL7]/A-DQ[5] IO[103]/B-DQ[7][C-DQL7]/B-DQ[5] M1_DDR_DQ7 AVDD_DDR F2 F8 DQL2 DQL3 VSS_9 VSS_10 P1 P9 F2 F8 DQL2 DQL3 VSS_9 VSS_10 P1 P9 C22 R31 H3 H8 DQL4 VSS_11 T1 T9 H3 H8 DQL4 VSS_11 T1 T9 C516 C518 1% M0_DDR_DM0 M1_DDR_DM0 DQL5 VSS_12 DQL5 VSS_12 1% IO[33]/A-DQM[0][A-DML]/A-DQM[0] IO[106]/B-DQM[0][C-DML]/B-DQM[0] G2 H7 DQL6 G2 H7 DQL6 0.1uF 0.1uF A23 T32 DQL7 B1 DQL7 B1 C519 M1_D_CLK R415 C517 R409 VSSQ_1 VSSQ_1 M0_DDR_DQS0 IO[42]/A-DQS[0][A-DQSL]/A-DQS[0] IO[115]/B-DQS[0][C-DQSL]/B-DQS[0] M1_DDR_DQS0 D7 C3 DQU0 VSSQ_2 B9 D1 D7 C3 DQU0 VSSQ_2 B9 D1 1000pF R427 B23 R30 C8 C2 DQU1 DQU2 VSSQ_3 VSSQ_4 D8 E2 C8 C2 DQU1 DQU2 VSSQ_3 VSSQ_4 D8 E2 1000pF C497 M0_DDR_DQS_N0 IO[41]/A-DQSB[0][A-DQSLB]/A-DQSB[0] IO[114]/B-DQSB[0][C-DQSLB]/B-DQSB[0] M1_DDR_DQS_N0 A7 DQU3 VSSQ_5 E8 A7 DQU3 VSSQ_5 E8 50V 50V 56 1K 0.01uF 1K DQU4 VSSQ_6 DQU4 VSSQ_6 A2 F9 A2 F9 DQU5 VSSQ_7 DQU5 VSSQ_7 B8 A3 DQU6 DQU7 VSSQ_8 VSSQ_9 G1 G9 B8 A3 DQU6 DQU7 VSSQ_8 VSSQ_9 G1 G9 1% 50V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF D23 P27 R428 M0_DDR_DQ8 IO[35]/A-DQ[8][A-DQU0]/A-DQ[15] IO[109]/B-DQ[8][C-DQU0]/B-DQ[15] M1_DDR_DQ8 56 D26 U29 1% M0_DDR_DQ9 IO[45]/A-DQ[9][A-DQU1]/A-DQ[10] IO[116]/B-DQ[9][C-DQU1]/B-DQ[10] M1_DDR_DQ9 E22 P28 C403 C404 C405 M0_DDR_DQ10 IO[38]/A-DQ[10][A-DQU2]/A-DQ[13] IO[107]/B-DQ[10][C-DQU2]/B-DQ[13] M1_DDR_DQ10 C400 C401 C402 D27 U27 M1_D_CLKN M0_DDR_DQ11 IO[46]/A-DQ[11][A-DQU3]/A-DQM[1] IO[119]/B-DQ[11][C-DQU3]/B-DQM[1] M1_DDR_DQ11 F23 R28 M0_DDR_DQ12 IO[36]/A-DQ[12][A-DQU4]/A-DQ[9] IO[111]/B-DQ[12][C-DQU4]/B-DQ[9] M1_DDR_DQ12 E26 V28 M0_DDR_DQ13 IO[43]/A-DQ[13][A-DQU5]/A-DQ[12] IO[117]/B-DQ[13][C-DQU5]/B-DQ[12] M1_DDR_DQ13 D22 P29 M0_DDR_DQ14 IO[34]/A-DQ[14][A-DQU6]/A-DQ[11] IO[108]/B-DQ[14][C-DQU6]/B-DQ[11] M1_DDR_DQ14 E25 U28 M0_DDR_DQ15 IO[44]/A-DQ[15][A-DQU7]/A-DQ[8] IO[118]/B-DQ[15][C-DQU7]/B-DQ[8] M1_DDR_DQ15 E24 T28 M0_DDR_DM1 IO[37]/A-DQM[1][A-DMU]/A-DQ[14] IO[110]/B-DQM[1][C-DMU]/B-DQ[14] M1_DDR_DM1 D24 T27 M0_DDR_DQS1 IO[40]/A-DQS[1][A-DQSU]/A-DQS[1] IO[113]/B-DQS[1][C-DQSU]/B-DQS[1] M1_DDR_DQS1 E23 R27 M0_DDR_DQS_N1 IO[39]/A-DQSB[1][A-DQSUB]/A-DQSB[1] IO[112]/B-DQSB[1][C-DQSUB]/B-DQSB[1] M1_DDR_DQS_N1 M1_DDR_VREFDQ Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M1_1_DDR_VREFDQ C28 AA31 IC403 IC404 M0_DDR_DQ16 IO[69]/A-DQ[16][B-DQL0]/A-DQ[16] IO[145]/B-DQ[16][D-DQL0]/B-DQ[16] M1_DDR_DQ16 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC C26 W31 M0_DDR_DQ17 IO[53]/A-DQ[17][B-DQL1]/A-DQ[17] IO[126]/B-DQ[17][D-DQL1]/B-DQ[17] M1_DDR_DQ17 B29 AA30 M0_DDR_DQ18 IO[70]/A-DQ[18][B-DQL2]/A-DQ[18] IO[143]/B-DQ[18][D-DQL2]/B-DQ[18] M1_DDR_DQ18 EAN63053201 EAN63053201 A26 W32 M0_DDR_DQ19 IO[54]/A-DQ[19][B-DQL3]/A-DQ[19] IO[127]/B-DQ[19][D-DQL3]/B-DQ[19] M1_DDR_DQ19 C29 AB31 M1_DDR_A0 N3 A0 DDR3 VREFCA M8 M1_DDR_A0 N3 A0 DDR3 VREFCA M8 M0_DDR_DQ20 IO[72]/A-DQ[20][B-DQL4]/A-DQ[22] IO[142]/B-DQ[20][D-DQL4]/B-DQ[22] M1_DDR_DQ20 P7 P7 4Gbit M0_DDR_DQ21 C25 IO[52]/A-DQ[21][B-DQL5]/A-DQ[23] IO[124]/B-DQ[21][D-DQL5]/B-DQ[23] V31 M1_DDR_DQ21 M1_DDR_A1 A1 4Gbit M1_DDR_A1 A1 P3 P3 M0_DDR_DQ22 A29 IO[71]/A-DQ[22][B-DQL6]/A-DQ[20] IO[144]/B-DQ[22][D-DQL6]/B-DQ[20] AB32 M1_DDR_DQ22 M1_DDR_A2 A2 (x16) M1_DDR_A2 A2 (x16) B26 V30 N2 H1 N2 H1 M0_DDR_DQ23 M1_DDR_DQ23 M1_DDR_A3 A3 VREFDQ M1_DDR_A3 A3 VREFDQ IO[51]/A-DQ[23][B-DQL7]/A-DQ[21] IO[125]/B-DQ[23][D-DQL7]/B-DQ[21] P8 P8 B27 W30 M1_DDR_A4 A4 M1_DDR_A4 M0_DDR_DM2 IO[55]/A-DQM[2][B-DML]/A-DQM[2] IO[128]/B-DQM[2][D-DML]/B-DQM[2] M1_DDR_DM2 A4 B28 Y30 P2 P2 M0_DDR_DQS2 M1_DDR_DQS2 M1_DDR_A5 A5 M1_DDR_A5 A5 IO[64]/A-DQS[2][B-DQSL]/A-DQS[2] IO[137]/B-DQS[2][D-DQSL]/B-DQS[2] R8 L8 R404 R8 L8 R419 C27 Y31 M1_DDR_A6 240 M1_DDR_A6 240 M0_DDR_DQS_N2 IO[63]/A-DQSB[2]/[B-DQSLB]/A-DQSB[2] IO[136]/B-DQSB[2][D-DQSLB]/B-DQSB[2] M1_DDR_DQS_N2 A6 ZQ A6 ZQ R2 AVDD_DDR R2 M1_DDR_A7 A7 M1_DDR_A7 A7 DDR3 1.5V bypass Cap - Place these caps near Memory T8 T8 AVDD_DDR M1_DDR_A8 A8 M1_DDR_A8 A8 E29 Y28 R3 B2 R3 B2 M0_DDR_DQ24 M1_DDR_DQ24 M1_DDR_A9 A9 VDD_1 M1_DDR_A9 A9 VDD_1 IO[58]/A-DQ[24][B-DQU0]/A-DQ[31] IO[131]/B-DQ[24][D-DQU0]/B-DQ[31] L7 D9 L7 D9 C31 AB27 M1_DDR_A10 A10/AP VDD_2 M1_DDR_A10 M0_DDR_DQ25 IO[67]/A-DQ[25][B-DQU1]/A-DQ[26] IO[141]/B-DQ[25][D-DQU1]/B-DQ[26] M1_DDR_DQ25 A10/AP VDD_2 R7 G7 R7 G7 DDR3 1.5V bypass Cap - Place these caps near Memory E27 V27 M1_DDR_A11 A11 VDD_3 M1_DDR_A11 M0_DDR_DQ26 IO[56]/A-DQ[26][B-DQU2]/A-DQ[29] IO[130]_/B-DQ[26][D-DQU2]/B-DQ[29] M1_DDR_DQ26 A11 VDD_3 D31 AB29 N7 K2 N7 K2 M0_DDR_DQ27 M1_DDR_DQ27 M1_DDR_A12 A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4 IO[66]/A-DQ[27][B-DQU3]/A-DQM[3] IO[140]/B-DQ[27][D-DQU3]/B-DQM[3] T3 K8 T3 K8 D29 W28 M1_DDR_A13 A13 VDD_5 M1_DDR_A13 M0_DDR_DQ28 IO[59]/A-DQ[28][B-DQU4]/A-DQ[25] IO[129]/B-DQ[28][D-DQU4]/B-DQ[25] M1_DDR_DQ28 A13 VDD_5 D30 AB28 T7 N1 T7 N1 M0_DDR_DQ29 M1_DDR_DQ29 M1_DDR_A14 A14 VDD_6 M1_DDR_A14 A14 VDD_6 IO[65]/A-DQ[29][B-DQU5]/A-DQ[28] IO[139]/B-DQ[29][D-DQU5]/B-DQ[28] M7 N9 M7 N9 E28 W27 M1_DDR_A15 NC_5 VDD_7 M1_DDR_A15 M0_DDR_DQ30 IO[57]/A-DQ[30][B-DQU6]/A-DQ[27] IO[132]/B-DQ[30][D-DQU6]/B-DQ[27] M1_DDR_DQ30 NC_5 VDD_7 C30 AA27 R1 R1 M0_DDR_DQ31 IO[60]/A-DQ[31][B-DQU7]/A-DQ[24] IO[138]/B-DQ[31][D-DQU7]/B-DQ[24] M1_DDR_DQ31 VDD_8 VDD_8 B31 Y27 M2 R9 M2 R9 M0_DDR_DM3 M1_DDR_DM3 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9 IO[68]/A-DQM[3][B-DMU]/A-DQ[30] IO[133]/B-DQM[3][D-DMU]/B-DQ[30] N8 N8 A31 AA28 M1_DDR_BA1 BA1 M1_DDR_BA1 M0_DDR_DQS3 IO[62]/A-DQS[3][B-DQSU]/A-DQS[3] IO[135]/B-DQS[3][D-DQSU]/B-DQS[3] M1_DDR_DQS3 BA1 B30 Y29 M3 M3 M0_DDR_DQS_N3 M1_DDR_DQS_N3 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2 IO[61]/A-DQSB[3][B-DQSUB]/A-DQSB[3] IO[134]/B-DQSB[3][D-DQSUB]/B-DQSB[3] A1 A1 VDDQ_1 VDDQ_1 J7 A8 J7 A8 M1_D_CLK CK VDDQ_2 M1_D_CLK CK VDDQ_2 K7 C1 K7 C1 M1_D_CLKN CK VDDQ_3 M1_D_CLKN CK VDDQ_3 K9 C9 K9 C9 M1_DDR_CKE CKE VDDQ_4 M1_DDR_CKE CKE VDDQ_4 D2 D2 VDDQ_5 VDDQ_5 L2 E9 L2 E9 M1_DDR_CS1 CS VDDQ_6 M1_DDR_CS2 CS VDDQ_6 K1 F1 K1 F1 M1_DDR_ODT ODT VDDQ_7 M1_DDR_ODT ODT VDDQ_7 J3 H2 C468 0.1uF J3 H2 C490 0.1uF M1_DDR_RASN RAS VDDQ_8 M1_DDR_RASN RAS VDDQ_8 K3 H9 C469 0.1uF K3 H9 C491 0.1uF M1_DDR_CASN CAS VDDQ_9 M1_DDR_CASN CAS VDDQ_9 L3 L3 M1_DDR_WEN WE M1_DDR_WEN WE J1 J1 * DDR_VTT NC_1 NC_1 T2 J9 T2 J9 M1_DDR_RESET_N RESET NC_2 M1_DDR_RESET_N RESET NC_2 L1 L1 NC_3 NC_3 L9 L9 SS_DDR3_4Gb_25n IC404-*1 Hynix_DDR3_4Gb_25n IC404-*2 SS_DDR3_2Gb IC404-*3 Hynix_DDR3_2Gb IC404-*4 NC_4 NC_4 K4B4G1646D-BCMA H5TQ4G63CFR_RDC K4B2G1646Q-BCMA H5TQ2G63FFR-RDC F3 F3 EAN63391401 EAN63053202 EAN63667401 EAN63648701 M1_DDR_DQS0 DQSL SS_DDR3_4Gb_25n IC403-*1 Hynix_DDR3_4Gb_25n IC403-*2 SS_DDR3_2Gb Hynix_DDR3_2Gb M1_DDR_DQS2 DQSL N3 A0 VREFCA M8 N3 A0 VREFCA M8 N3 A0 VREFCA M8 N3 A0 VREFCA M8 AVDD_DDR G3 K4B4G1646D-BCMA H5TQ4G63CFR_RDC IC403-*3 K4B2G1646Q-BCMA IC403-*4 H5TQ2G63FFR-RDC G3 P7 P3 A1 A2 P7 P3 A1 A2 P7 P3 A1 A2 P7 P3 A1 A2 +3.3V_NORMAL M1_DDR_DQS_N0 DQSL EAN63391401 EAN63053202 EAN63667401 EAN63648701 M1_DDR_DQS_N2 DQSL N2 P8 A3 A4 VREFDQ H1 N2 P8 A3 A4 VREFDQ H1 N2 P8 A3 A4 VREFDQ H1 N2 P8 A3 A4 VREFDQ H1 N3 M8 N3 M8 N3 M8 N3 M8 P2 P2 P2 P2 A0 VREFCA A0 VREFCA A0 VREFCA A0 VREFCA A5 A5 A5 A5 P7 P7 P7 P7 R8 L8 R8 L8 R8 L8 R8 L8 C7 A9 P3 N2 P8 A1 A2 A3 VREFDQ H1 P3 N2 P8 A1 A2 A3 VREFDQ H1 P3 N2 P8 A1 A2 A3 VREFDQ H1 P3 N2 P8 A1 A2 A3 VREFDQ H1 C7 A9 R2 T8 R3 A6 A7 A8 ZQ B2 R2 T8 R3 A6 A7 A8 ZQ B2 R2 T8 R3 A6 A7 A8 ZQ B2 R2 T8 R3 A6 A7 A8 ZQ B2 IC402 M1_DDR_DQS1 DQSU VSS_1 P2 R8 A4 A5 L8 P2 R8 A4 A5 L8 P2 A4 A5 P2 A4 A5 M1_DDR_DQS3 DQSU VSS_1 L7 A9 A10/AP VDD_1 VDD_2 D9 L7 A9 A10/AP VDD_1 VDD_2 D9 L7 A9 A10/AP VDD_1 VDD_2 D9 L7 A9 A10/AP VDD_1 VDD_2 D9 AP2303MPTR-G1 [EP] B7 B3 R2 A6 A7 ZQ R2 A6 A7 ZQ R8 R2 A6 A7 ZQ L8 R8 R2 A6 A7 ZQ L8 B7 B3 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 M1_DDR_DQS_N1 DQSU VSS_2 T8 T8 T8 T8 M1_DDR_DQS_N3 DQSU VSS_2 T3 K8 T3 K8 T3 K8 T3 K8 CIS21J121 A8 A8 A8 A8 A13 VDD_5 A13 VDD_5 A13 VDD_5 A13 VDD_5 R3 B2 R3 B2 R3 B2 R3 B2 N1 T7 N1 N1 T7 N1 E1 L7 R7 A9 A10/AP VDD_1 VDD_2 D9 G7 L7 R7 A9 A10/AP VDD_1 VDD_2 D9 G7 L7 R7 A9 A10/AP VDD_1 VDD_2 D9 G7 L7 R7 A9 A10/AP VDD_1 VDD_2 D9 G7 E1 M7 NC_5 VDD_6 VDD_7 N9 R1 M7 A14 NC_5 VDD_6 VDD_7 N9 R1 M7 NC_5 VDD_6 VDD_7 N9 R1 M7 A14 NC_5 VDD_6 VDD_7 N9 R1 VSS_3 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 VSS_3 M2 VDD_8 R9 M2 VDD_8 R9 M2 VDD_8 R9 M2 VDD_8 R9 C544 L401 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 E7 G8 T3 A13 VDD_5 K8 N1 T3 T7 A13 VDD_5 K8 N1 T3 A13 VDD_5 K8 N1 T3 T7 A13 VDD_5 K8 N1 E7 G8 N8 M3 BA1 N8 M3 BA1 N8 M3 BA1 N8 M3 BA1 VIN NC_3 M1_DDR_DM0 DML VSS_4 M7 NC_5 VDD_6 VDD_7 N9 R1 M7 A14 NC_5 VDD_6 VDD_7 N9 R1 M7 NC_5 VDD_6 VDD_7 N9 M7 A14 NC_5 VDD_6 VDD_7 N9 M1_DDR_DM2 DML VSS_4 BA2 VDDQ_1 A1 BA2 VDDQ_1 A1 BA2 VDDQ_1 A1 BA2 VDDQ_1 A1 1 8 10uF D3 J2 M2 BA0 VDD_8 VDD_9 R9 M2 BA0 VDD_8 VDD_9 R9 M2 BA0 VDD_8 VDD_9 R1 R9 M2 BA0 VDD_8 VDD_9 R1 R9 D3 J2 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 10V M1_DDR_DM1 DMU VSS_5 N8 N8 N8 N8 M1_DDR_DM3 DMU VSS_5 K9 C9 K9 C9 K9 C9 K9 C9 C421 THERMAL BA1 BA1 BA1 BA1 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 M3 M3 M3 M3 D2 D2 D2 D2 J8 J7 BA2 VDDQ_1 A1 A8 J7 BA2 VDDQ_1 A1 A8 J7 BA2 VDDQ_1 A1 A8 J7 BA2 VDDQ_1 A1 A8 J8 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 10uF VSS_6 K7 CK CK VDDQ_2 VDDQ_3 C1 K7 CK CK VDDQ_2 VDDQ_3 C1 K7 CK CK VDDQ_2 VDDQ_3 C1 K7 CK CK VDDQ_2 VDDQ_3 C1 VSS_6 J3 ODT RAS VDDQ_7 VDDQ_8 H2 J3 ODT RAS VDDQ_7 VDDQ_8 H2 J3 ODT RAS VDDQ_7 VDDQ_8 H2 J3 ODT RAS VDDQ_7 VDDQ_8 H2 GND NC_2 9 E3 M1 K9 CKE VDDQ_4 C9 D2 K9 CKE VDDQ_4 C9 D2 K9 CKE VDDQ_4 C9 D2 K9 CKE VDDQ_4 C9 D2 E3 M1 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 10V 2 7 M1_DDR_DQ0 DQL0 VSS_7 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 L2 K1 CS VDDQ_5 VDDQ_6 E9 F1 L2 CS VDDQ_5 VDDQ_6 E9 L2 CS VDDQ_5 VDDQ_6 E9 M1_DDR_DQ16 DQL0 VSS_7 WE NC_1 J1 WE NC_1 J1 WE NC_1 J1 WE NC_1 J1 F7 M9 J3 ODT RAS VDDQ_7 VDDQ_8 H2 J3 ODT RAS VDDQ_7 VDDQ_8 H2 K1 J3 ODT RAS VDDQ_7 VDDQ_8 F1 H2 K1 J3 ODT RAS VDDQ_7 VDDQ_8 F1 H2 F7 M9 T2 RESET NC_2 NC_3 J9 L1 T2 RESET NC_2 NC_3 J9 L1 T2 RESET NC_2 NC_3 J9 L1 T2 RESET NC_2 NC_3 J9 L1 DDR_VTT M1_DDR_DQ1 DQL1 VSS_8 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 K3 L3 CAS VDDQ_9 H9 M1_DDR_DQ17 DQL1 VSS_8 F3 NC_4 L9 T7 F3 NC_4 L9 F3 NC_4 L9 T7 F3 NC_4 L9 R443 F2 P1 WE NC_1 J1 WE NC_1 J1 WE J1 WE J1 F2 P1 G3 DQSL NC_6 G3 DQSL G3 DQSL NC_6 G3 DQSL VREFEN VCNTL M1_DDR_DQ2 DQL2 VSS_9 T2 RESET NC_2 J9 L1 T2 RESET NC_2 J9 L1 T2 RESET NC_1 NC_2 J9 T2 RESET NC_1 NC_2 J9 M1_DDR_DQ18 DQL2 VSS_9 DQSL DQSL DQSL DQSL 10K F8 P9 NC_3 L9 NC_3 L9 NC_3 L1 L9 NC_3 L1 L9 F8 P9 C7 B7 DQSU VSS_1 A9 B3 C7 B7 DQSU VSS_1 A9 B3 C7 B7 DQSU VSS_1 A9 B3 C7 B7 DQSU VSS_1 A9 B3 3 6 CIS21J121 NC_4 NC_4 NC_4 NC_4 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2 F3 T7 F3 F3 T7 F3 E1 E1 E1 E1 M1_DDR_DQ3 DQL3 VSS_10 G3 DQSL DQSL NC_6 G3 DQSL DQSL G3 DQSL DQSL NC_6 G3 DQSL DQSL M1_DDR_DQ19 DQL3 VSS_10 E7 DML VSS_3 VSS_4 G8 E7 DML VSS_3 VSS_4 G8 E7 DML VSS_3 VSS_4 G8 E7 DML VSS_3 VSS_4 G8 1/16W H3 T1 C7 A9 C7 A9 H3 T1 D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 L400 C7 A9 C7 A9 J8 J8 J8 J8 DQSU VSS_1 DQSU VSS_1 DQSU VSS_1 DQSU VSS_1 VSS_6 VSS_6 VSS_6 VSS_6 M1_DDR_DQ4 DQL4 VSS_11 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_2 B3 E1 M1_DDR_DQ20 DQL4 VSS_11 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 1% VOUT NC_1 H8 T9 E7 D3 DML VSS_3 VSS_4 G8 J2 E7 D3 DML VSS_3 VSS_4 G8 J2 E7 DML VSS_3 VSS_4 G8 E7 DML VSS_3 VSS_4 G8 H8 T9 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 4 5 M1_DDR_DQ5 DQL5 VSS_12 DMU VSS_5 VSS_6 J8 DMU VSS_5 VSS_6 J8 D3 DMU VSS_5 VSS_6 J2 J8 D3 DMU VSS_5 VSS_6 J2 J8 M1_DDR_DQ21 DQL5 VSS_12 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 G2 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 G2 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 M1_DDR_DQ6 DQL6 F2 F8 DQL1 DQL2 VSS_8 VSS_9 P1 P9 F2 F8 DQL1 DQL2 VSS_8 VSS_9 P1 P9 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 M1_DDR_DQ22 DQL6 H7 DQL6 DQL7 H7 DQL6 DQL7 H7 DQL6 DQL7 H7 DQL6 DQL7 H7 H3 DQL3 DQL4 VSS_10 VSS_11 T1 H3 DQL3 DQL4 VSS_10 VSS_11 T1 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 F8 H3 DQL3 DQL4 VSS_10 VSS_11 P9 T1 H7 D7 DQU0 VSSQ_1 VSSQ_2 B1 B9 D7 DQU0 VSSQ_1 VSSQ_2 B1 B9 D7 DQU0 VSSQ_1 VSSQ_2 B1 B9 D7 DQU0 VSSQ_1 VSSQ_2 B1 B9 M1_DDR_DQ7 DQL7 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 M1_DDR_DQ23 DQL7 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 B1 H7 DQL6 DQL7 B1 H7 DQL6 DQL7 B1 H7 DQL6 DQL7 B1 H7 DQL6 DQL7 B1 B1 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 VSSQ_1 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 VSSQ_1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 D7 B9 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 D7 B9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 M1_DDR_DQ8 DQU0 VSSQ_2 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 C2 A7 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E8 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 M1_DDR_DQ24 DQU0 VSSQ_2 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 C414 C417 C535 C3 D1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A7 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 E8 F9 A7 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 E8 F9 C3 D1 M1_DDR_DQ9 DQU1 VSSQ_3 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 M1_DDR_DQ25 DQU1 VSSQ_3 10uF 10uF 10uF C8 D8 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 C8 D8 10V 10V 10V M1_DDR_DQ10 DQU2 VSSQ_4 M1_DDR_DQ26 DQU2 VSSQ_4 C543 1% 1/16W 10K R444 C2 E2 C2 E2 M1_DDR_DQ11 DQU3 VSSQ_5 M1_DDR_DQ27 DQU3 VSSQ_5 0.1uF A7 E8 A7 E8 16V M1_DDR_DQ12 DQU4 VSSQ_6 M1_DDR_DQ28 DQU4 VSSQ_6 A2 F9 A2 F9 M1_DDR_DQ13 DQU5 VSSQ_7 M1_DDR_DQ29 DQU5 VSSQ_7 B8 G1 B8 G1 M1_DDR_DQ14 DQU6 VSSQ_8 M1_DDR_DQ30 DQU6 VSSQ_8 A3 G9 A3 G9 M1_DDR_DQ15 DQU7 VSSQ_9 M1_DDR_DQ31 DQU7 VSSQ_9 +1.5V_Bypass Cap +1.5V_Bypass Cap Close to DDR Power Pin Close to DDR Power Pin AVDD_DDR AVDD_DDR 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C475 C480 C476 C444 C445 C446 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-004_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-12-30 LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A DDR 04 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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COMPENSATION_DONE_1 OLED Clock for MSD808KWD DPC_CTRL +3.3V_NORMAL MAIN Clock(24Mhz) Jtag I/F X-TAL_1 12V_ON 5pF GND_1 XIN_MAIN C600 For Main C614 R612 JTAG R614 JTAG R616 JTAG 0.1uF 2 1 R635 JTAG 24MHz X600 1M 1K 1K 1K SW600 JS2235S P600 3 4 12505WS-10A00 X-TAL_2 GND_2 JTAG 1 5pF TRST_N0 XOUT_MAIN TDI0 1 6 TDO0 2 C615 R602 R604 TDI0 0 0 3 OPT OPT TDO0 TDI0_1 2 5 TDO0_1 System Clock for Analog block(24Mhz) 4 R603 JTAG R605 TMS0 0 0 OPT OPT 5 TCK0 3 4 6 SOC_RESET 7 JTAG 1K R609 8 9 10 11 IC100 LGE5332(LM14A) IC100 LGE5332(LM14A) R624 33 0.047uF C620 T2 AF6 SC_R D0-_HDMI1 A_RX0N LINEIN_L0 COMP1/AV1/DVI_L_IN AA2 B1 T3 AE6 2.2uF C601 RIN0P TN EPHY_TDN D0+_HDMI1 A_RX0P LINEIN_R0 COMP1/AV1/DVI_R_IN R625 68 0.047uF C621 AA1 C1 U1 AF2 2.2uF C602 GIN0M TP EPHY_TDP D1-_HDMI1 A_RX1N LINEIN_L1 SC_L_IN Y3 A2 V2 AF1 2.2uF C603 R626 33 C622 GIN0P RN EPHY_RDN D1+_HDMI1 A_RX1P LINEIN_R1 SC_R_IN 0.047uF B2 V3 AG5 2.2uF C604 SC_G D2-_HDMI1 RP EPHY_RDP A_RX2N LINEIN_L2 Y1 W2 AG4 BIN0P D2+_HDMI1 A_RX2P LINEIN_R2 R628 33 0.047uF C624 R1 SC_B CK-_HDMI1 A_RXCN AA6 R2 SC_ID HSYNC0 CK+_HDMI1 A_RXCP AA5 D4 R6 SC_FB VSYNC0 GPIO19/[LED0]/GPIO74 I2C_SCL4 DDC_SCL_1 DDCDA_CK/GPIO38 T6 T5 AF3 GPIO20/[LED1]/GPIO75 I2C_SDA4 HDMI 1.4b &2.0 DDC_SDA_1 DDCDA_DA/GPIO39 MICCM0 MHL OPT Y2 AG1 HDMI_HPD_1 HOTPLUGA MICIN0 R630 33 0.047uF C627 AA3 V6 AH2 COMP1_Pr 0.047uF RIN1P CEC0/GPIO5 LINEOUT_L2 SCART_Lout R631 68 C628 AC1 URSA_RESET_SoC U4 AH3 5V_DET_HDMI_1 SCART_Rout R632 33 0.047uF C629 GIN1M HOTPLUGA_HDMI20_5V/GPIO34 LINEOUT_R2 COMP1_Y AC2 GIN1P L1 AF4 D0-_HDMI2 B_RX0N EARPHONE_OUTL HP_LOUT R634 33 0.047uF C631 AB2 M2 AF5 COMP1_Pb BIN1P D0+_HDMI2 B_RX0P EARPHONE_OUTR HP_ROUT 1000pF C632 AB3 M3 SOGIN1 D1-_HDMI2 B_RX1N C605 1uF N2 P3 D1+_HDMI2 B_RX1P ARC0/GPIO6 HDMI_ARC P2 D2-_HDMI2 B_RX2N AD3 D5 P1 RIN2P RESET SOC_RESET D2+_HDMI2 B_RX2P AD2 K2 AG3 GIN2M CK-_HDMI2 B_RXCN VAG AD1 AM4 K3 AG2 C606 L600 GIN2P XTAL_IN XIN_MAIN CK+_HDMI2 B_RXCP AVSS_VRM_ADC 1uF AK4 L4 10uF PZ1608U121-2R0TF C609 XTAL_OUT XOUT_MAIN DDC_SCL_2 DDCDB_CK/GPIO40 10V AC3 L5 BIN2P DDC_SDA_2 DDCDB_DA/GPIO41 F5 M4 IRIN/GPIO4 BIT11 HDMI_HPD_2 HOTPLUGB/GPIO31 M5 D8 5V_DET_HDMI_2 HOTPLUGB_HDMI20_5V/GPIO35 I2S_IN_BCK/GPIO94 TRST_N0 D6 JTAG 0 R606 47K +3.3V_NORMAL JTAG R615 I2S_IN_SD/GPIO95 TCK0 A4 D2 C5 JTAG 1K R608 DM_P0 WIFI_DM C_RX0N I2S_IN_WS/GPIO93 B4 D3 R610 DP_P0 WIFI_DP C_RX0P 22 C4 E2 G6 R619 68 DM_P1 C_RX1N I2S_OUT_BCK/GPIO100 AUD_SCK C613 0.047uF AD6 B3 E3 E6 R611 VCOM DP_P1 C_RX1P I2S_OUT_MCK/GPIO99 22 AL6 F2 F6 R618 DM_P2 USB_DM3 C_RX2N I2S_OUT_WS/GPIO98 AUD_LRCK R620 33 C616 0.047uF AC6 AK6 F1 E8 22 TU_CVBS USB_DP3 AUD_LRCH CVBS0 DP_P2 AC-coupling CAP C_RX2P I2S_OUT_SD/GPIO101 R621 33 C617 0.047uF AC5 AM14 C633 0.1uF C3 F9 AV1_CVBS_IN CVBS1 SSUSB_TXP SSUSB_TXP C_RXCN I2S_OUT_SD1/GPIO102 BIT10 R622 33 C618 0.047uF AB6 AL14 C634 0.1uF Place near by MST D1 E7 C607 SC_CVBS_IN CVBS2 SSUSB_TXN SSUSB_TXN C_RXCP I2S_OUT_SD2/GPIO103 DPC_CTRL AM13 H6 F7 22pF DM_PSS USB_DM1 BIT6 DDCDC_CK/GPIO42 I2S_OUT_SD3/GPIO104 12V_ON AK13 H5 DP_PSS USB_DP1 BIT7 DDCDC_DA/GPIO43 C608 C611 C612 AK12 K6 AG7 0 R644 SSUSB_RXP BIT8 MHL_DET_LM15 22pF 22pF 1000pF SSUSB_RXP HOTPLUGC/GPIO32 GPIO_PM[14]/GPIO24 50V AL13 J6 AH6 OPT SSUSB_RXN SSUSB_RXN BIT9 HOTPLUGC_HDMI20_5V/GPIO36 GPIO_PM[15]/GPIO25 COMPENSATION_DONE_1 AK9 AH5 SSUSB_TXP1 GPIO_PM[16]/GPIO26 /MHL_OCP AL10 G2 SSUSB_TXN1 D0-_HDMI3 D_RX0N AM10 G3 DM_PSS1 USB_DM2 D0+_HDMI3 D_RX0P AC4 AK10 H2 DTV/MNT_V_OUT CVBS_OUT1 DP_PSS1 USB_DP2 D1-_HDMI3 D_RX1N JTAG AM11 H3 SSUSB_RXP1 D1+_HDMI3 D_RX1P R613 AL11 J2 0 SSUSB_RXN1 D2-_HDMI3 D_RX2N J1 TDO0_1 D2+_HDMI3 D_RX2P F3 CK-_HDMI3 D_RXCN G1 CK+_HDMI3 D_RXCP J4 DDC_SCL_3 DDCDD_CK/GPIO44 K5 DDC_SDA_3 DDCDD_DA/GPIO45 H4 HDMI_HPD_3 HOTPLUGD/GPIO33 J5 5V_DET_HDMI_3 HOTPLUGD_HDMI20_5V/GPIO37 R600 JTAG 0 TMS0 B5 SPDIF_IN/GPIO96 A5 SPDIF_OUT SPDIF_OUT/GPIO97 JTAG R601 0 TDI0_1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-006_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-08 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN4_EXT_IN/OUTPUT 06 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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IC100 LGE5332(LM14A) A15 T23 GND_1 GND_171 A18 T24 GND_2 GND_172 A21 T25 GND_3 GND_173 A24 T26 GND_4 GND_174 A27 U2 GND_5 GND_175 A30 U3 GND_6 GND_176 B10 U8 GND_7 GND_177 B32 U9 GND_8 GND_178 C2 U10 GND_9 GND_179 C13 U14 GND_10 GND_180 C32 U15 GND_11 GND_181 D18 U16 GND_12 GND_182 D21 U17 GND_13 GND_183 D25 U18 GND_14 GND_184 D28 U20 GND_15 GND_185 D32 U26 GND_16 GND_186 E30 V1 GND_17 GND_187 E31 V8 GND_18 GND_188 E32 V9 GND_19 GND_189 F22 V10 GND_20 GND_190 F24 V11 GND_21 GND_191 F25 V12 GND_22 GND_192 F26 V13 GND_23 GND_193 F27 V14 GND_24 GND_194 F28 V15 GND_25 GND_195 F29 V16 GND_26 GND_196 F30 V20 GND_27 GND_197 F31 V21 GND_28 GND_198 G11 V22 GND_29 GND_199 G12 V26 GND_30 GND_200 G13 V29 GND_31 GND_201 G14 V32 GND_32 GND_202 G15 W3 GND_33 GND_203 G16 W8 GND_34 GND_204 G17 W9 GND_35 GND_205 G18 W10 GND_36 GND_206 G19 W11 GND_37 GND_207 G20 W12 GND_38 GND_208 G21 W13 GND_39 GND_209 G23 W14 GND_40 GND_210 G24 W15 GND_41 GND_211 G25 W16 GND_42 GND_212 G26 W17 GND_43 GND_213 G27 W18 GND_44 GND_214 G28 W22 GND_45 GND_215 H8 W26 GND_46 GND_216 H9 Y8 GND_47 GND_217 H10 Y9 GND_48 GND_218 H11 Y10 GND_49 GND_219 H12 Y11 GND_50 GND_220 H13 Y12 GND_51 GND_221 H14 Y13 GND_52 GND_222 H15 Y14 GND_53 GND_223 H17 Y15 GND_54 GND_224 H18 Y16 GND_55 GND_225 H19 Y17 GND_56 GND_226 H20 Y18 GND_57 GND_227 H21 Y22 GND_58 GND_228 H22 Y26 GND_59 GND_229 H23 AA9 GND_60 GND_230 H24 AA10 GND_61 GND_231 H25 AA11 GND_62 GND_232 H26 AA12 GND_63 GND_233 H27 AA14 GND_64 GND_234 H30 AA15 GND_65 GND_235 J3 AA16 GND_66 GND_236 J7 AA17 GND_67 GND_237 J8 AA18 GND_68 GND_238 J14 AA21 GND_69 GND_239 J15 AA26 GND_70 GND_240 J16 AA29 GND_71 GND_241 J22 AA32 GND_72 GND_242 J24 AB9 GND_73 GND_243 J25 AB10 GND_74 GND_244 J26 AB11 GND_75 GND_245 J27 AB12 GND_76 GND_246 K7 AB13 GND_77 GND_247 K8 AB14 GND_78 GND_248 K14 AB16 GND_79 GND_249 K15 AB17 GND_80 GND_250 K25 AB18 GND_81 GND_251 K26 AB19 GND_82 GND_252 L2 AB20 GND_83 GND_253 L3 AB21 GND_84 GND_254 L8 AB22 GND_85 GND_255 L14 AB23 GND_86 GND_256 L15 AB26 GND_87 GND_257 L16 AB30 GND_88 GND_258 L25 AC7 GND_89 GND_259 L26 AC8 GND_90 GND_260 M1 AC9 GND_91 GND_261 M8 AC10 GND_92 GND_262 M9 AC11 GND_93 GND_263 M10 AC12 GND_94 GND_264 M11 AC13 GND_95 GND_265 M12 AC16 GND_96 GND_266 M13 AC23 GND_97 GND_267 M14 AC25 GND_98 GND_268 M15 AC26 GND_99 GND_269 M16 AC27 GND_100 GND_270 M17 AC28 GND_101 GND_271 M18 AD8 GND_102 GND_272 M19 AD9 GND_103 GND_273 M20 AD10 GND_104 GND_274 M25 AD11 GND_105 GND_275 M26 AD12 GND_106 GND_276 M29 AD13 GND_107 GND_277 M32 AD14 GND_108 GND_278 N3 AD15 GND_109 GND_279 N7 AD16 GND_110 GND_280 N8 AD24 GND_111 GND_281 N9 AD25 GND_112 GND_282 N10 AD26 GND_113 GND_283 N11 AD27 GND_114 GND_284 N13 AD28 GND_115 GND_285 N14 AE3 GND_116 GND_286 N17 AE8 GND_117 GND_287 N18 AE9 GND_118 GND_288 N19 AE10 GND_119 GND_289 N20 AE11 GND_120 GND_290 N24 AE12 GND_121 GND_291 N25 AE13 GND_122 GND_292 N26 AE14 GND_123 GND_293 P8 AE17 GND_124 GND_294 P9 AE18 GND_125 GND_295 P10 AE23 GND_126 GND_296 P11 AE24 GND_127 GND_297 P12 AE25 GND_128 GND_298 P13 AE26 GND_129 GND_299 P14 AE27 GND_130 GND_300 P15 AE28 GND_131 GND_301 P16 AE29 GND_132 GND_302 P17 AF9 GND_133 GND_303 P18 AF10 GND_134 GND_304 P19 AF17 GND_135 GND_305 P20 AF18 GND_136 GND_306 P24 AF19 GND_137 GND_307 P25 AF20 GND_138 GND_308 P26 AF21 GND_139 GND_309 R3 AF22 GND_140 GND_310 R8 AF23 GND_141 GND_311 R9 AF24 GND_142 GND_312 R10 AF25 GND_143 GND_313 R14 AF26 GND_144 GND_314 R15 AF27 GND_145 GND_315 R16 AF28 GND_146 GND_316 R17 AF29 GND_147 GND_317 R18 AF30 GND_148 GND_318 R19 AG22 GND_149 GND_319 R20 AG23 GND_150 GND_320 R21 AG30 GND_151 GND_321 R22 AH21 GND_152 GND_322 R23 AH22 GND_153 GND_323 R24 AJ3 GND_154 GND_324 R25 AJ22 GND_155 GND_325 R26 AJ30 GND_156 GND_326 R29 AK5 GND_157 GND_327 R32 AK11 GND_158 GND_328 T8 AK14 GND_159 GND_329 T9 AL1 GND_160 GND_330 T10 AL3 GND_161 GND_331 T14 AL4 GND_162 GND_332 T15 AL9 GND_163 GND_333 T16 AL12 GND_164 GND_334 T17 AL23 GND_165 GND_335 T18 AL27 GND_166 GND_336 T19 AM25 GND_167 GND_337 T20 AM29 GND_168 GND_338 T21 AM31 GND_169 GND_339 T22 GND_170 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-007_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-11-13 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_GND 07 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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CI Region * Option name of this page : CI_SLOT (because of Hong Kong) CI SLOT +5V_CI_ON CI_DATA[0-7] CI TS INPUT CI_SLOT FE_DEMOD1_TS_DATA[0-7] +5V_NORMAL CI_SLOT AR903 33 C902 FE_DEMOD1_TS_DATA[7] 10uF CI_MDI[7] FE_DEMOD1_TS_DATA[6] CI_SLOT 10V CI_MDI[6] @netLa FE_DEMOD1_TS_DATA[5] R906 CI_MDI[5] FE_DEMOD1_TS_DATA[4] 10K CI_SLOT CI_MDI[4] /CI_CD1 JK900 10125901-115LF CI_SLOT CI_SLOT AR902 33 R912 FE_DEMOD1_TS_DATA[3] 35 1 CI_MDI[3] CI_SLOT 100 CI_DATA[3] FE_DEMOD1_TS_DATA[2] 36 2 CI_MDI[2] AR901 CI_DATA[4] FE_DEMOD1_TS_DATA[1] 33 37 3 CI_MDI[1] CI_DATA[5] R916 FE_DEMOD1_TS_DATA[0] TPI_DATA[4] 38 4 10K CI_MDI[0] CI_DATA[6] TPI_DATA[5] 39 5 CI_DATA[7] TPI_DATA[6] 40 6 FE_DEMOD1_TS_DATA[0-7] TPI_DATA[7] 41 7 R914 47 CI_SLOT R918 33 CI_SLOT CI_ADDR[10] /PCM_CE1 CI_MISTRT FE_DEMOD1_TS_SYNC 42 8 R919 33 CI_SLOT CI_MIVAL_ERR FE_DEMOD1_TS_VAL CI_SLOT R908 10K 43 9 R920 100 CI_SLOT CI_ADDR[11] CI_OE CI_MCLKI FE_DEMOD1_TS_CLK CI_IORD 44 10 +5V_NORMAL CI_ADDR[9] CI_IOWR 45 11 CI_ADDR[8] 46 12 R917 CI_ADDR[13] 10K CI_MDI[0] 47 13 CI_ADDR[14] CI_MDI[1] 48 14 CI_SLOT CI_MDI[2] 49 15 CI_WE 50 16 R915 100 CI_MDI[3] CI_SLOT CAM_IREQ_N 51 17 CI_SLOT GND C901 0.1uF 52 53 18 19 C903 0.1uF C904 0.1uF CI HOST I/F CI_MDI[4] CI_SLOT CI_SLOT GND CI_MDI[5] 54 20 +5V_NORMAL CI_ADDR[12] CI_MDI[6] 55 21 CLOSE TO MSTAR CI_ADDR[7] R900 56 22 GND CI_MDI[7] R909 10K CI_ADDR[6] CI_SLOT 10K CI_SLOT 57 23 CI_ADDR[5] AR906 CI_SLOT R901 47 CI_SLOT 58 24 PCM_RESET CI_ADDR[4] 33 R902 47 CI_SLOT 59 25 CAM_WAIT_N CI_ADDR[3] CI_ADDR[0] EB_ADDR[0] CLOSE TO MSTAR 60 26 REG CI_ADDR[2] CI_ADDR[1] EB_ADDR[1] R903 33 CI_SLOT 61 27 TPI_CLK CI_ADDR[1] CI_ADDR[2] EB_ADDR[2] R904 33 CI_SLOT 62 28 TPI_VAL CI_ADDR[3] EB_ADDR[3] R905 33 CI_SLOT CI_ADDR[0] TPI_SOP 63 29 CI_DATA[0] CI_SLOT 64 30 AR900 33 CI_DATA[1] 65 31 CI_ADDR[0-14] TPI_DATA[0] CI_DATA[2] 66 32 OLED_CI_SLOT CI_SLOT TPI_DATA[1] 67 33 JK900-*1 AR907 10125901-015LF TPI_DATA[2] 68 34 35 1 33 TPI_DATA[3] 36 2 37 3 CI_ADDR[4] EB_ADDR[4] G2 69 G1 38 4 R910 39 5 CI_ADDR[5] EB_ADDR[5] 40 6 100 41 7 CI_ADDR[6] EB_ADDR[6] /CI_CD2 42 8 CI_SLOT 43 9 CI_ADDR[7] EB_ADDR[7] +5V_NORMAL GND 44 10 45 11 46 47 12 13 CI_SLOT CI_SLOT GND 48 14 AR908 33 C900 49 15 50 16 2pF 51 17 CI_ADDR[8] EB_ADDR[8] R907 50V 52 18 CI_ADDR[9] EB_ADDR[9] 10K GND 53 19 54 20 CI_ADDR[10] EB_ADDR[10] CLOSE TO MSTAR CI_SLOT 55 56 21 22 CI_ADDR[11] EB_ADDR[11] 57 23 58 24 59 25 60 26 61 27 62 28 CI_SLOT 63 29 CI_MISTRT 64 30 AR909 33 CI_MIVAL_ERR 65 31 CI_ADDR[12] EB_ADDR[12] 66 32 67 33 68 34 CI_ADDR[13] EB_ADDR[13] CI_MCLKI G2 69 G1 CI_ADDR[14] EB_ADDR[14] REG CAM_REG_N CI_SLOT AR913 33 CI_OE EB_OE_N CI_WE EB_WE_N CI_IORD EB_BE_N1 CI DETECT +3.3V_NORMAL CI_IOWR EB_BE_N0 CI_SLOT IC900 74LVC1G32GW +3.3V_NORMAL B 1 5 VCC /CI_CD2 CI_SLOT A 2 /CI_CD1 AR904 33 GND 3 4 Y R911 CI_DATA[0] EB_DATA[0] 10K CI_DATA[1] EB_DATA[1] CI_DATA[2] EB_DATA[2] OR_GATE_CI_TI OR_GATE_CI_TOSHIBA CI_DATA[3] EB_DATA[3] IC900-*1 IC900-*2 SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION EB_DATA[0-7] @netLa A VCC IN_B VCC CI_SLOT 1 5 1 5 CAM_CD1_N AR905 33 B IN_A R913 CI_DATA[4] EB_DATA[4] 2 2 47 CI_DATA[5] EB_DATA[5] GND Y GND OUT_Y 3 4 3 4 CI_DATA[6] EB_DATA[6] CI_DATA[7] EB_DATA[7] CI_DATA[0-7] CI POWER ENABLE CONTROL EB_DATA[0-7] IC901 +5V_NORMAL AP2151WG-7 +5V_CI_ON IN OUT 5 1 C905 CI_SLOT 0.1uF C906 50V GND 2 1uF CI_SLOT R923 25V CI_SLOT 10K R922 100 EN FLG CI_SLOT PCM_5V_CTL 4 3 R921 10K CI_SLOT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-009_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-11-13 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 9 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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M+ MODULE R2333 33 EBK61012701 1 PWM_TOUT Module_MPLUS & NON_UF84(M+) RESET_IC_DIODES(MAIN) +12V IC2307-*1 PWM_TIN R2324 33 PANEL_POWER TYP 6000mA Power_DET APX803E29 2 +3.5V_ST 2N3906S-RTK Module_MPLUS & NON_UF84(M+) Q2300-*1 VCC RESET 3 3 2 PWM_DIM 100 MMBT3906(NXP) KEC_RL_ON_TR(MAIN) NXP_RL_ON_TR(SUB) L2321 L2322 1 R2304 MLB-201209-0120P-N2 GND EAN61829902 Non_Module_MPLUS & UF84(M+) 0TR390609DC R2301 PD_20_24V_DIODES OS MODULE LGE MODULE MLB-201209-0120P-N2 PANEL_VCC 1 10K +12V +3.5V_ST +3.5V_ST IC2308-*1 R2300 SMAW200-H28S5K[MIRROR] SMAW200-H24S5[MIRROR] R2349 Q2300 RL_ON 10K 100K APX803D29 P2301 P2300 C2327 C2331 IC2309 PD_+12V PD_+3.5V 2 C2330 AOS_PANEL_POWER_FET(MAIN) RESET_IC_ROHM(SUB) R2354 RESET 2 3 VCC 10uF 0.1uF 0.01uF AO4447A R2335 R2343 10K EBK61313102 IC2307 3 25V 50V OMEGA SEMICONDUCTOR 2.7K 0 1 +3.3V_NORMAL 16V OPT OPT 1% 5% BD48K28G GND S_1 D_4 1 8 C2361 R2314 OPT OPT OPT POWER_DET 0.1uF 1K R2329 C2335 C2367 S_2 2 7 D_3 VDD 3 2 VOUT C2315 16V 10uF 10uF 1uF 10K S_3 3 6 D_2 1 25V 25V 25V R2359 R2360 C2369 C2350 R2311 100 INV_CTL 2K 2K C2370 PD_+12V 0.1uF PWR_ON 1 2 INV_CTL G 4 5 D_1 10uF GND L2301 OPT 0.1uF R2336 16V EAN62945801 +3.5V_ST PDIM#1 PDIM#2 R2313 100 OPT 25V UBW2012-121F 3 4 PWM_DIM2 16V 1.2K PWR_DET_MERGE OPT 1% C2364 3.5V 5 6 GND R2331 0.1uF R2355 C2302 3.5V 7 8 3.5V NON_DIGITAL_POWER_B/D 1.8K 16V L2317 IC2309-*1 0.1uF GND 9 10 GND UBW2012-121F C2368 ROHM_PANEL_POWER_FET(SUB) PD_20_24V not to RESET 0 RRH140P03TB 16V 12V 12V C 10uF R2348 11 12 R2328 EBK61232301 ROHM CO.,LTD. +24V at 8kV ESD +12V 25V 100K 12V 13 14 12V 10K B Q2321 UBW2012-121F L2307 +24V PANEL_CTL OPT S_1 D_4 C2365 12V GND 2N3904S 1 8 15 16 UBW2012-121F PD_20_24V_ROHM 0.1uF PWR_DET_SEPARATE GND 24V C2371 KEC_PANEL_CTL_TR 17 18 E S_2 2 7 D_3 PD_20V PD_24V IC2308 16V C2304 L2302 10uF C PD_UHD_24V 0.1uF 24V 19 20 24V 10V S_3 D_2 R2340-*2 R2340-*1 R2340 BD48K28G L2308 C2319 3 6 5.6K 8.2K 50V UBW2012-121F 24V GND or 24V B Q2321-*1 9.1K 21 22 UBW2012-121F 0.1uF G D_1 1% 1% 1% R2356 POWER_DET_1 GND NC or GND 50V MMBT3904(NXP) 4 5 VDD VOUT 0 23 24 NXP_PANEL_CTL_TR 3 2 L2303 OS MODULE L/D_CLK GND L/D_CLK 25 26 DIGITAL_POWER_B/D E PWR_DET_SEPARATE PD_20V PD_24V 1 L/D_DI 27 28 L/D_VSYNC L2315 PD_UHD_24V C2351 L/D_DI 25 UBW2012-121F R2341-*1 R2341 GND R2341-*2 0.1uF 1.6K 1.3K 1.5K 16V 24V-->3.48V OS MODULE 1% 1% 1% 20V-->3.51V 29 PD_20_24V Digital Power B/D INCH 24 PIN 22 PIN L/D_VSYNC 12V-->3.58V . O 40 ~ 65 NC L2316 +12V ST_3.5V-->3.5V GND UBW2012-121F NON_DIGITAL_POWER_B/D X 70 ~ 79 GND 24V C2316 C2317 C2318 10uF 10uF 10uF 16V 16V 16V ’15 UHD POWER +5.0V normal & USB +12V 1% R2342150K 1% DDR +1.5V R2 R2337 16K 1% C2347 OPT 2200pF C2349 C2352 R2339 16K +1.5V_DDR +24V 50V 1% 1/16W +3.3V - eMMC 100pF 0.047uF 6.8K R2351 L2309 POWER_ON/OFF2_3 R2344 50V 25V PZ1608U121-2R0TF 10K TI_TPS54327_1.5V_DDR_DCDC C2359 C2362 C2363 +3.3V_NORMAL IC2303-*1 RSET2 RSET1 +3.3V_NORMAL 3.3V_EMMC +1.8V DVDD18_EMMC TPS54327DDAR [EP]GND 22uF 22uF 10uF [EP] AGND RLIM COMP C2324 C2357 R1 10V 10V 10V +3.3V_LED C2322 FB SS 0.1uF ROHM_BD9D321_1.5V_DDR_DCDC EN 1 8 VIN L2314 10uF 120-ohm 82pF THERMAL 1% 1/16W 51K 16V VFB VBST 50V LD2300 9 R2352 2 7 IC2303 28 27 26 25 24 23 22 L2304 L2305 R2326 VREG5 SW VIN_1 LX_3 PZ1608U121-2R0TF PZ1608U121-2R0TF BD9D321EFJ [EP] 3 6 1 21 L2313 10K THERMAL 4.7uH SS GND 4 5 VIN_2 2 29 20 LX_2 +3.3V_LED R2315 DCDC_DIODE_0DTKE00018A(KEC) EN VIN 3.3K C2308 C2307 1 8 C2340 C2341 C2344 VIN_3 3 19 LX_1 C2355 0DTKE00018A 0.1uF C2309 0.1uF C2312 16V 10uF 10uF 0.1uF IC2305 0.047uF +5V_NORMAL THERMAL 22uF 22uF 50V PGND_1 ZD2304 16V 16V 0.1uF 35V 35V 4 18 BST 25V 10V 10V R2320 R2321 FB BOOT C2336 SN1302001(TPS65286RHDR) 9 2 7 OPT PGND_2 5 17 SW_IN2 R1 18K 4.7K L2312 C2360 R2350 1/16W 1% 1% 100K 100K R2353 2.2uH PGND_3 SW_IN1 1/16W VREG SW 6 16 1uF 5% 5% DCDC_DIODE_0DR050008AA(SEMTECH) 1.0V_DCDC_TI C2325 100pF 50V 3 6 PS064T-2R2MS DCDC_DIODE V7V 7 6A 15 NFAULT1 10V 0DR050008AA ZD2304-*1 /USB_OCD2 SS GND 25V 1uF C2343 10 11 12 13 14 4 3A 5 C2339 8 9 C2332-*1 C2338 ZD2302 3300pF 22uF 22uF 2.5V R2322 10V MODE/SYNC EN SW_OUT2 SW_OUT1 SW_EN2 SW_EN1 NFAULT2 50V 22K 10V C2328 C2332 1% 1uF 2200pF +1.8V - LM15U, eMMC 10V 50V 1.0V_DCDC_ROHM Switching freq: 700K R2 & Vx1 pull-up Vout=0.6*(1+R1/R2) /USB_OCD3 C2346 +5V_USB_3 +5V_USB_2 Vout=0.765*(1+R1/R2)=1.554V USB_CTL3 USB_CTL2 R2338 10K 0.0068uF POWER_ON/OFF1 50V 5.1V:R1-51K, R2-6.8K +1.8V +3.3V_NORMAL IC2301 AZ1117EH-ADJTRG1 +2.5V IN OUT TU_JP TU_JP +2.5V_Normal DCDC_DIODE ADJ/GND R2309 IC2300 1 R2312 ZD2303 TJ4220GDP-ADJ [EP]GND 1% 1/16W 75 2.5V R2307 POWER_ON/OFF2_3 10K TU_JP TU_JP R2316 C2310 C2311 C2321 22K R2 1 8 10uF 10uF 0.1uF 1% 1% 1/16W 33 THERMAL +3.3V_NORMAL NC_1 GND R2308 10V 10V TU_JP 9 2 7 R2317 ADJ/SENSE 47K R1 EN2 1% 3 6 TU_JP C2320 VIN3 VOUT LM15 Power SEQUENCE 0.1uF 16V 4 2A 5 NC4 NC_2 TU_JP TU_JP EAN62206201 C2323 ZD2301 POWER_ON/OFF1(5V) 10uF 10V 0DR050008AA 5V 0DTKE00018A MAX A TU_JP_DCDC_DIODE(KEC) +3.3V_NORMAL ZD2301-*1 POWER_ON/OFF2_1(3.3V) +12V +3.3V_NORMAL Vout=0.6*(1+R1/R2) POWER_ON/OFF2_3(1.5V, 2.5V) L2300 BLM18PG121SN1D POWER_ON/OFF2_4(1.1V) DCDC_DIODE_0DTKE00018A(KEC) Placed on SMD-TOP C2300 C2301 C2303 +24V AUDIO AMP 10uF 10uF 0.1uF 16V 16V 16V 0DTKE00018A OPT IC2302 ZD2300 TPS54427DDA [EP]GND R2303 +24V +24V_AMP 10K EN VIN 1 8 16V L2310 THERMAL POWER_ON/OFF2_1 0.1uF 1% C2314 UBW2012-121F VFB VBST 9 2 7 PS064T-2R2MS R2302 L2306 R1 2.2uH 51K VREG5 SW 3 6 C2305 100pF 50V SS GND R2305 4 4A 5 C2326 22uF 10V C2329 22uF 10V C2333 100uF C2334 10uF 10V 15K C2306 C2313 1uF 0.015uF 10V 50V 1% DCDC_DIODE_0DR050008AA(SEMTECH) Switching freq: 700K R2 0DR050008AA ZD2300-*1 Vout=0.765*(1+R1/R2) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-0023_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A(UF77) 2015-01-08 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_PWR_1_UHD 23 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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MAX 3A LM14A CPU +1.1V_VDDC_CPU LM14A CORE +12V L2502 PZ1608U121-2R0TF +1.1V_VDDC Placed on SMD-TOP +12V DCDC_DIODE_0DTKE00018A(KEC) UF64/68 UF64/68 UF77/83/84 UF77/83/84 C2510-*1 C2512-*1 C2510 C2512 C2513 10uF 10uF 10uF 0.1uF 10uF 16V 16V 16V R1 IC2502 IC2501 L2501 25V BD86106EFJ R2521 25V OPT C2514 L2500 0DTKE00018A TPS54427DDA [EP]GND 2uH 5.6K EAN62653301 [EP] 100pF PZ1608U121-2R0TF 10K ZD2501 1% 50V R2524 EN 1 8 VIN 16V PGND SW_2 0.1uF 1 8 THERMAL C2517 THERMAL DCDC_DIODE_0DTKE00018A(KEC) POWER_ON/OFF2_4 VFB VBST Placed on SMD-TOP 9 2 7 L2503 VIN SW_1 OPT OPT OPT 9 2 7 2.2uH R2510 VREG5 SW OPT C2504 C2505 C2506 C2507 C2508 C2509 15K R1 R2 3 6 C2500 C2501 C2502 AGND 3 6 EN 0.0068uF 10uF 10uF 100uF 10uF 10uF 1% PS064T-2R2MS R2500 50V R2522 SS GND 10uF 10uF 0.1uF 6.8K 10V 10V 10V 10V C2511 4 4A 5 FB 4 6A 5 COMP 47pF 11K R2519-*1 25V 25V 25V 50V 1% C2518 C2519 0DTKE00018A 27K 22uF 22uF ZD2500 10V 10V R2523 CPU_VID_LM14_A0 1/16W 10K POWER_ON/OFF2_4 1% 1% R2-1.13V R2511 1/16W R2501 CPU_VID_LM14_A1 R2515 R2519 1/16W 56K C2503 10K 1% LM14A_A0_ONLY 22K 75K 0.1uF 1/16W R2504 1% 1% KEC_CPU_CORE_VID_FET(MAIN) KEC_CPU_CORE_VID_FET(MAIN) DCDC_DIODE_0DR050008AA(SEMTECH) 16V 15K R2512 1/16W 0DR050008AA 6.2K +3.3V_NORMAL +3.3V_NORMAL C2515 C2516 1% ZD2501-*1 R2 KEC_CPU_CORE_VID_FET R2516 1% R2520 1uF 2200pF 1.6K 75K 10V 50V 1% 1% LM14A_A0_ONLY 1/16W +3.3V_NORMAL R2505 56K R2513 D R2517 D 1% 2N7002KA 2N7002KA 10K 10K LM14A_A0_ONLY R2502 D R2514 R2518 2N7002KA Q2502 Q2503 G G 10K DCDC_DIODE_0DR050008AA(SEMTECH) CPU_VID0 CPU_VID1 0DR050008AA S S R2503 Q2500 0 5% 0 5% G ZD2500-*1 CORE_VID0 D D 0 5% S Q2502-*1 Q2503-*1 LM14A_A0_ONLY G G 2N7002K 2N7002K S S LM14_A1 DIODEDS_CPU_CORE_VID_FET(SUB) DIODEDS_CPU_CORE_VID_FET(SUB) R2-1 R2-2 LM14_A0 LM14_A1 LM14_A0 V_out V_out V_out V_out Delete this part when LM14A0 used all. Boot High High 1.06 1.163 Boot 0.98 1.15 Kernel High Low 1.01 1.013 D Kernel Q2500-*1 0.98 0.98 G Kernel Low Low 0.96 0.969 2N7002K S DIODEDS_CPU_CORE_VID_FET LM14A1 CORE_VID1 NOT USE. Vout=0.765*(1+R1/R2) Vout=0.8*(1+R1/R2) CORE_VID1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-025_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM15U_PWR_2_ALL 25 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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Renesas MICOM For Debug +3.5V_ST MICOM_DEBUG R3016 1K R3014 10K SEIKO EPSON CORPORATION MICOM_DEBUG Don’t remove R3016, P3000 12507WS-04L not making float P40 C3002 C3003 18pF 15pF 50V 50V LOGO_LIGHT MICOM_DEBUG 1 LOGO_LIGHT MICOM_RESET 2 MICOM_DEBUG EAW30067102 X3000 WIFI_EN 3 4 MICOM_RESET 32.768KHz +3.5V_ST 5 HDMI_WAUP:HDMI_INIT R3028 4.7M MHL_DET_LM15 OPT 0 R3037 MHL_DET_LM15 10K POWER_DET_1 R3032 10K R3030 MICOM_RESET_SW GND MICOM_RESET_22OHM SW3000 JTP-1127WEM 2 1 33 R3031 1% 1/16W 270K OPT C3004 P124/XT2/EXCLKS 0.47uF 0.1uF +3.5V_ST 4 3 16V R3029 P122/X2/EXCLK P41/TI07/TO07 C3001 P137/INTP0 P120/ANI19 P40/TOOL0 P123/XT1 C3000 P121/X1 0.1uF MICOM_RESET_33OHM R3029-*1 33 RESET +3.5V_ST REGC VDD VSS R3021-*1 LCD OLED R3021 LM14A Power SEQUENCE 1K 10K 5% 1/16W 48 47 46 45 44 43 42 41 40 39 38 37 POWER_ON/OFF1(5V) P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON SCART_MUTE I2C_SCL_MICOM P61/SDAA0 2 35 P00/TI00/TXD1 POWER_ON/OFF2_4 I2C_SDA_MICOM SCART_MUTE P62 3 34 P01/TO00/RXD1 3D&L_DIM_EN POWER_ON/OFF2_4 POWER_ON/OFF2_1(3.3V) P63 4 33 P130 PANEL_CTL P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP POWER_ON/OFF2_1 WOL/WIFI_POWER_ON 5 32 KEY2 POWER_ON/OFF2_3(1.5V) IR P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM KEY1 R3000 100 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2 HDMI_CEC_MICOM POWER_ON/OFF2_4(1.1V) P73/KR3/SO01 8 29 P23/ANI3 MODEL1_OPT_3 POWER_ON/OFF2_3 P72/KR2/SO21 9 28 P24/ANI4 MODEL1_OPT_0 P71/KR1/SI21/SDA21 10 27 P25/ANI5 SOC_RESET EYE_SDA SIDE_HP_MUTE P70/KR0/SCK21/SCL21 11 26 P26/ANI6 EYE_SCL MHL_EN MHL_EN P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7 MODEL1_OPT_1 13 14 15 16 17 18 19 20 21 22 23 24 AR3000 3.3K EYE_Q +3.5V_ST P50/INTP1/SI11/SDA11 P51/INTP2/SO11 P17/TI02/TO02 P16/TI01/TO01/INTP5 P15/PCLBUZ1/SCK20/SCL20 P14/RXD2/SI20/SDA20 P13/TXD2/SO20 P12/SO00/TXD0/TOOLTXD P11/SI00/RXD0/TOOLRXD/SDA00 P10/SCK00/SCL00 P146 P147/ANI18 MICOM MODEL OPTION +3.5V_ST MICOM MODEL OPTION 10K 10K 10K MICOM_OLED MICOM_LOGO MICOM_H15 R3006 R3008 R3013 0 1 MODEL_OPT_0 NON LOGO LOGO MODEL1_OPT_0 MODEL_OPT_1 LCD OLED MODEL1_OPT_1 MODEL1_OPT_3 MODEL_OPT_3 LM15U/LM14A H15 SOC_RX POWER_DET EDID_WP URSA_RESET_MICOM URSA_RESET_MICOM AMP_MUTE WOL_WAKE_UP INV_CTL MICOM_LM15U/LM14A POWER_ON/OFF1 WOL_CTL SOC_TX LED_R MICOM_NON_LOGO 10K 10K 10K MICOM_LCD R3009 R3012 R3004 For CEC R3015 10K +3.5V_ST CEC_DIODE(SUB) MICOM_LM14A EAH62792701 LED_R SOC_RESET D3000-*1 30V BAT54_TSC R3033 R3034 27K 120K LM14A : Active high reset G D3000 BAT54_SUZHO CEC_REMOTE HDMI_CEC_MICOM D S CEC_DIODE(MAIN) EAH61433701 Q3001 RUE003N02 G ROHM_CEC_FET(MAIN) Q3001-*1 EBK61731401 SI1012CR-T1-GE3 S D VISHAY_CEC_FET(SUB) EBK61731301 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-030_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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5V_HDMI_3 5V_DET_HDMI_3 R3309 1.8K ESD_HDMI R3312 R3302 VA3300 3.3K EAG63530103 EAG63530103 EAG63530103 1K R3337 R3305 HDMI_JACK_CNPLUS(MAIN) HDMI_JACK_CNPLUS(MAIN) HDMI_JACK_CNPLUS(MAIN) 33 JK3300-*1 JK3301-*1 JK3302-*1 4.7K 5501-56219 5501-56219 5501-56219 C OPT NON_HDMI_EXT_EDID Q3300 TMDS_DATA2+ B 1K 1 TMDS_DATA2+ TMDS_DATA2+ 1 1 2N3904S HDMI_HPD_3 TMDS_DATA2_SHIELD 2 TMDS_DATA2_SHIELD 2 TMDS_DATA2_SHIELD BODY_SHIELD R3300 R3303 TMDS_DATA2- TMDS_DATA2- 2 3 3 TMDS_DATA2- 3 100K R3339 TMDS_DATA1+ 4 TMDS_DATA1+ TMDS_DATA1+ E 4.7K 4 4 20 TMDS_DATA1_SHIELD 5 TMDS_DATA1_SHIELD TMDS_DATA1_SHIELD KEC_HDMI_HPD_3_TR HDMI_EXT_EDID TMDS_DATA1- 5 5 ESD_HDMI 6 TMDS_DATA1- TMDS_DATA1- VA3302 6 C TMDS_DATA0+ 7 TMDS_DATA0+ TMDS_DATA0+ 6 7 19 AR3309 TMDS_DATA0_SHIELD TMDS_DATA0_SHIELD 7 HOT_PLUG_DETECT Q3300-*1 B 33 8 8 TMDS_DATA0_SHIELD 8 TMDS_DATA0- TMDS_DATA0- 18 MMBT3904(NXP) DDC_SDA_3 9 9 TMDS_DATA0- 9 5V_HDMI_1 5V_DET_HDMI_1 TMDS_CLK+ VDD[+5V] NXP_HDMI_HPD_3_TR 10 TMDS_CLK+ 10 TMDS_CLK+ 10 TMDS_CLK_SHIELD E DDC_SCL_3 11 TMDS_CLK_SHIELD 11 TMDS_CLK_SHIELD R3324 17 TMDS_CLK- TMDS_CLK- 11 DDC/CEC_GND 12 12 TMDS_CLK- 12 CEC CEC OPT 1.8K ESD_HDMI 13 13 CEC 16 13 R3335 R3316 VA3308 SDA VA3304 VA3306 RESERVED 14 RESERVED RESERVED OPT 3.3K 14 14 1K R3336 R3319 ESD_HDMI ESD_HDMI SCL 15 SCL 15 SCL 33 15 SDA SDA 15 4.7K SCL 16 16 SDA 16 DDC/CEC_GND DDC/CEC_GND 17 17 DDC/CEC_GND 14 VDD[+5V] VDD[+5V] 17 RESERVED 18 18 VDD[+5V] 18 OPT C OPT HOT_PLUG_DETECT CEC_REMOTE 19 HOT_PLUG_DETECT 19 HOT_PLUG_DETECT BODY_SHIELD Q3305 R3318 13 19 R3315 CEC AR3300 20 100K 2N3904S B 1K 20 20 HDMI_HPD_1 12 5.1 BODY_SHIELD BODY_SHIELD 20 BODY_SHIELD TMDS_CLK- 1/16W OPT ESD_HDMI VA3312 E 11 CK-_HDMI3 TMDS_CLK_SHIELD 19 CK+_HDMI3 HOT_PLUG_DETECT 10 TMDS_CLK+ D0-_HDMI3 18 VDD[+5V] 9 D0+_HDMI3 AR3311 TMDS_DATA0- 17 33 DDC/CEC_GND 8 DDC_SDA_1 TMDS_DATA0_SHIELD 16 SDA DDC_SCL_1 7 TMDS_DATA0+ 15 SCL VA3311 6 ESD_HDMI TMDS_DATA1- 14 RESERVED VA3309 5 CEC_REMOTE ESD_HDMI TMDS_DATA1_SHIELD 13 CEC AR3307 4 AR3301 TMDS_DATA1+ 12 5.1 5.1 TMDS_CLK- 1/16W 3 1/16W TMDS_DATA2- 11 CK-_HDMI1 D1-_HDMI3 TMDS_CLK_SHIELD 2 CK+_HDMI1 TMDS_DATA2_SHIELD D1+_HDMI3 10 TMDS_CLK+ D0-_HDMI1 1 D2-_HDMI3 TMDS_DATA2+ 9 D0+_HDMI1 D2+_HDMI3 TMDS_DATA0- 8 JK3301 TMDS_DATA0_SHIELD HDMI_JACK_YEON(SUB) 7 TMDS_DATA0+ AR3308 05008WR-H19C EAG63530104 HDMI3 6 TMDS_DATA1- 5.1 1/16W +3.5V_ST C YEON HO ELECTRONICS CO., LTD EBK61012701 5 D1-_HDMI1 TMDS_DATA1_SHIELD B Q3304-*1 D1+_HDMI1 MMBT3906(NXP) R3326 4 MHL_NXP_TR(MAIN) TMDS_DATA1+ MHL D2-_HDMI1 10K E 5V_HDMI_2 3 D2+_HDMI1 TMDS_DATA2- MHL 5V_DET_HDMI_2 R3327 E R3308 2 10K Q3304 TMDS_DATA2_SHIELD MHL_KEC_TR(SUB) 1.8K 0TR390609DC ESD_HDMI 1 B R3304 OPT R3310 VA3301 TMDS_DATA2+ 2N3906S-RTK 3.3K 1K R3338 MHL C R3307 C 33 MHL R3325 4.7K R3317 0 C JK3302 B NON_MHL R3306 MHL_DET_LM15 Q3301 R3328 HDMI_JACK_YEON(SUB) 1K B 1K Q3303 R3314 NON_MHL 2N3904S HDMI_HPD_2 MHL 10K BODY_SHIELD EAG63530104 VA3310 C3303 E R3301 R3320 2N3904S 05008WR-H19C 5.6V 0.1uF 100K 300K KEC_MHL_TR 0 20 E YEON HO ELECTRONICS CO., LTD MHL 16V KEC_HDMI_HPD_2_TR OPT MHL Spec C ESD_HDMI C AR3310 VA3303 19 33 HOT_PLUG_DETECT Q3301-*1 B DDC_SDA_2 B Q3303-*1 MMBT3904(NXP) MMBT3904(NXP) 18 NXP_MHL_TR VDD[+5V] NXP_HDMI_HPD_2_TR DDC_SCL_2 E E 17 DDC/CEC_GND VA3305 VA3307 ESD_HDMI HDMI1 with MHL 16 ESD_HDMI SDA 15 SCL HDMI_ARC 14 RESERVED CEC_REMOTE 13 CEC AR3303 12 5.1 TMDS_CLK- 1/16W 11 TMDS_CLK_SHIELD CK-_HDMI2 EDID external EEPROM +5V_NORMAL 10 CK+_HDMI2 E TMDS_CLK+ 5V_HDMI_3 D0-_HDMI2 9 MMBT3904(NXP) TMDS_DATA0- D0+_HDMI2 B Q3302-*1 A1 A2 EAH61714301 8 C MMBD6100 TMDS_DATA0_SHIELD NXP_HDMI_EXT_EDID_TR D3309 7 SUZHOU_DDC_DIODE(MAIN) TMDS_DATA0+ C AR3306 6 5.1 TMDS_DATA1- 1/16W E KEC_HDMI_EXT_EDID_TR ATMEL_HDMI_EXT_EDID 5 2N3904S TMDS_DATA1_SHIELD D1-_HDMI2 ROHM_HDMI_EXT_EDID EDID_WP 4 D1+_HDMI2 IC3301 Q3302 B IC3301-*1 TMDS_DATA1+ D2-_HDMI2 BR24G02FJ-3GTE2 C AT24C02C-SSHM-T KEC_DDC_DIODE(SUB) 3 EAH61714301 TMDS_DATA2- D2+_HDMI2 D3309-*1 2 A0 VCC HDMI_EXT_EDID MMBD6100 A0 VCC TMDS_DATA2_SHIELD 1 8 A2 1 8 1 C TMDS_DATA2+ R3323 A1 WP AR3305 A1 A1 WP 2 7 4.7K 1/16W 2 7 47K JK3300 HDMI_JACK_YEON(SUB) A2 SCL A2 SCL 05008WR-H19C 3 6 3 6 EAG63530104 HDMI2 with ARC GND SDA GND SDA YEON HO ELECTRONICS CO., LTD 4 5 4 5 R3321 22 DDC_SCL_3 HDMI_EXT_EDID R3322 22 DDC_SDA_3 HDMI_EXT_EDID MHL Current Limit 5V_HDMI_1 MHL_DIODE(KEC) MHL 0DTKE00018A L3301 ZD3300-*1 IC3300 BLM31PG500SN1 5V_MHL TPS2553DBV 50-ohm DDC pull-up IN OUT D3304 ESD_5V_HDMI_1 1 6 5V_HDMI_2 5V_HDMI_1 C3301 ZD3300 MHL 30V MHL +5V_NORMAL +3.5V_ST MHL VA3313 0.1uF 5V MHL 1% OPT C3302 16V GND ILIM R3313 +5V_NORMAL 2 5 10uF +5V_NORMAL 5V_MHL 100K MHL_DIODE(SD05) 10V A1 A2 20K A1 A2 0DR050008AA A1 A2 R3311 MHL EAH61714301 EN FAULT MMBD6100 MHL_DET_LM15 3 4 EAH61714301 L3300 D3305 MMBD6100 EAH61714301 /MHL_OCP MMBD6100 C PZ1608U121-2R0TF SUZHOU_DDC_DIODE(MAIN) D3308 C C D3310 SUZHOU_DDC_DIODE(MAIN) MHL_SUZHOU_DDC_DIODE(MAIN) MHL MHL C3300 AR3302 0.1uF AR3304 1/16W /MHL_OCP 1/16W 16V 47K 47K KEC_DDC_DIODE(SUB) KEC_DDC_DIODE(SUB) MHL_KEC_DDC_DIODE(SUB) EAH61714301 DDC_SDA_2 EAH61714301 EAH61714301 D3305-*1 D3308-*1 DDC_SDA_1 D3310-*1 MMBD6100 DDC_SCL_2 MMBD6100 MMBD6100 A2 A2 DDC_SCL_1 A2 C C C A1 A1 A1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-033_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-08 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 10 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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SPDIF OUT AV/COMPONENT REAR Place JACK Side 1608 sizs For EMI/ESD AV/COMP_DAMPING_3.3ohm 3.3 R3832 @netLa AV1_CVBS_IN R3808 C3822 C3805 C3806 1/4W VA3806 150pF 27pF 100pF C3811 COMP1_Y 75 1% 5.5V OPT 50V 50V 47pF R3831 50V 0 OPT OPT Foxconn_OPTIC_JAKC(SUB) R3832-*1 0 JK3800-*1 2F01TC1-CLM97-4F AV/COMP_DAMPING_0ohm GND +3.3V_NORMAL 1 AV/COMPONENT_REAR(DV) AV/COMPONENT_REAR(PV) Fiber Optic EAG60968217 EAG60968213 JK3802-*1 JK3802 VCC 2 PPJ245N2-01 PPJ245-31 R3807 6E [RD2]E-LUG [ GN/YL]E-LUG 6A 10K VIN 3 R3803 1K 1608 sizs For EMI/ESD [RD2]O-SPRING 5A +3.3V_NORMAL 4 5E [GN/YL]O-SPRING AV1_CVBS_DET 1608 sizs For EMI/ESD Solteam_OPTIC_JACK(MAIN) AV/COMP_DAMPING_3.3ohm SHIELD [RD2]CONTACT 4A [GN/YL]CONTACT 4E VA3803 3.3 R3811 GND 5.6V COMP1_Pb 1 5B +3.3V_NORMAL Fiber Optic JST1223-001 5D [WH]O-SPRING [BL]O-SPRING SIGN380006 R3811-*1 C3810 C3812 JK3800 0 27pF 27pF R3816 C3815 VCC [RD1]CONTACT 7C VA3804 75 [RD1]E-LUG-S 10pF 2 4C 50V 50V 5.5V R3810 AV/COMP_DAMPING_0ohm OPT 50V OPT 1% 5C 10K VINPUT 5C [RD1]O-SPRING [RD1]O-SPRING SPDIF_OUT 3 R3802 4 C3800 VA3807 C3818 [RD1]E-LUG-S 4C VA3805 7C [RD1]CONTACT 1K 18pF 5.5V 0.1uF 5.5V AV/COMP_DAMPING_3.3ohm COMP1_DET FIX_POLE 1608 sizs For EMI/ESD 50V 16V 3.3 R3809 OPT [BL]O-SPRING 5D [WH]O-SPRING COMP1_Pr 5B VA3800 5.6V [GN/YL]CONTACT 4E R3809-*1 C3809 C3813 C3814 4A [RD2]CONTACT R3800 0 R3817 VA3801 27pF 27pF 75 10pF 5.6V 470K 50V 50V 50V 5E AV/COMP_DAMPING_0ohm FOR EMI 1% 5A [GN/YL]O-SPRING [RD2]O-SPRING OPT OPT [GN/YL]E-LUG 6E [RD2]E-LUG 6A 1608 sizs For EMI R3812 R3805 10K COMP1/AV1/DVI_L_IN VA3802 R3801 0 5.6V 470K C3801 C3803 C3807 R3814 560pF 100pF 1000pF 12K 50V 50V 50V OPT OPT OPT 1608 sizs For EMI R3813 R3806 10K COMP1/AV1/DVI_R_IN 0 C3802 C3804 C3808 R3815 560pF 100pF 1000pF 12K 50V 50V 50V OPT OPT OPT HP OUT JK3803 PEJ034-01 E_SPRING 3 HP_LOUT_MAIN R3821 HP_OUT OPTC3819 HP_OUT 22K AR3800 L3801 100 0.01uF R3804 PZ1608U121-2R0TF OPT 1/16W 150 HP_LOUT HP_LOUT_AMP HP_OUT 1/10W C3817 5% +3.3V_NORMAL HP_ROUT 0.22uF R_SPRING 4 25V HP_ROUT_MAIN R3820 R3822 OPT T_SPRING 5 C3820 10K 22K HP_OUT 0.01uF R3819 HP_OUT OPT 100 B_TERMINAL2 7B HP_DET 1/16W HP_OUT 5% T_TERMINAL2 6B HP_OUT L3800 R3818 PZ1608U121-2R0TF 150 Close to Main soc HP_ROUT_AMP HP_OUT C3816 1/10W 5% 0.22uF VA3808 25V 5.6V HP_OUT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-038_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM15U 2015-01-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK_COMMON_H 38 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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WIFI POWER ENABLE CONTROL +3.5V_ST +3.5V_WIFI IC4100 AP2191WG-7 IN OUT 5 1 C4100 R4119 0.1uF GND 10K 2 OPT WIFI_EN R4101 33 EN FLG 4 3 R4100 C4113 TOSHIBA_WIFI_DMDP_ESD(SUB) 10K 0.1uF EAH62735601 16V OPT P4100 SMAW200-H18S5 D4100-*1 DF3D6.8MS +3.5V_WIFI C4110 C4108 22uF GND 1 2 +3.5V_WOL 0.1uF 10V R4111 R4113 M_RFModule_RESET 100 BT_RESET 3 4 USB_DM 0 WIFI_DM C4103 R4114 +3.5V_ST 0.1uF NC 5 6 USB_DP 0 Place Near Wafer WIFI_DP R4112 WOL/WIFI_POWER_ON 100 WOL 7 8 GND C4107 C4109 5pF 5pF AR4101 EAH61515101 R4106 R4107 100 C4104 0.1uF SDA 9 10 GND D4100 50V 50V 10K 10K EYE_SDA 1% 1% RCLAMP0502BA EYE_SCL SCL 11 12 KEY1 SEMTECH_WIFI_DMDP_ESD(MAIN) AR4102 100 +3.5V_ST R4110 GND 13 14 KEY2 KEY1 10K KEY2 5% IR 15 16 +3.5V_ST +3.5V_ST IR C4105 C4111 C4112 100pF LED_R 17 18 GND C4106 1000pF 0.1uF 0.1uF 50V 50V OPT OPT LOGO_LIGHT_WAFER LED_R OPT R4109 1.8K LED_R OPT 19 GND C4102 0.1uF 16V IR +3.5V_ST IC4101 AO-R123C7G-LG R4103 1/16W R4105 1/10W IR_PROTO IR_PROTO IR_PROTO 330 5% 47 5% GND G VS V O OUT SMD bottom for ESD 10.5T OPT OPT OPT SMD_EMI4 OPT HDMI2 HDMI3 GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H HDMI1 GASKET_8.0X6.0X10.5H M4102 M4103 M4106 M4110 M4114 MDS62110225 MDS62110225 MDS62110225 HDMI1_BOT_SMD_10.5T HDMI2_BOT_SMD_10.5T HDMI3_BOT_SMD_8.5T MDS62110225 MDS62110225 HDMI3_BOT_SMD_10.5T GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X10.5H M4100 M4108 M4115 M4115-*1 MDS62110225 MDS62110225 MDS62110209 MDS62110225 SMD_EMI2 SMD_EMI1 OPT GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H M4112 M4109 M4107 MDS62110225 MDS62110225 HDMI1_BOT_SMD_8.5T HDMI2_BOT_SMD_8.5T HDMI3_BOT_SMD_9T MDS62110225 GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X9.0H M4100-*1 M4108-*1 M4115-*2 70inch_EMI MDS62110209 MDS62110209 MDS62110226 79inch_EMI GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X12.5H M4105 M4105-*1 MDS62110225 MDS62110217 USB3 USB2 USB1 70inch_EMI 79inch_EMI USB3_BOT_SMD_10.5T USB2_BOT_SMD_10.5T USB1_BOT_SMD_8.5T USB1_BOT_SMD_6.5T GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X12.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X8.5H SMR-T-6-6.5-8 M4104 M4104-*1 M4111 M4113 M4116 M4116-*2 MDS62110225 MDS62110217 MDS62110225 MDS62110225 MDS62110209 MDS62110206 LOGO_LIGHT USB3_BOT_SMD_8.5T USB2_BOT_SMD_8.5T USB1_BOT_SMD_10.5T AR4100 SMD_EMI3_10.5T SMD_EMI3_8.5T GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X10.5H 33 GASKET_8.0X6.0X8.5H Place Near Micom 1/16W GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X8.5H M4111-*1 M4113-*1 M4116-*1 M4101 M4101-*1 MDS62110209 MDS62110225 MDS62110209 LOGO_LIGHT_WAFER MDS62110225 MDS62110209 LOGO_LIGHT C B LOGO_LIGHT LOGO_LIGHT 1K Q4100 LOGO_LIGHT R4104 R4102 E C4101 LOGO_LIGHT MMBT3904(NXP) 10K 0.1uF 16V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-041_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-10-23 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR/KEY 12 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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+5V_USB FOR USB1 +5V_USB_3 USB3 OCP USB1 MAX 1.0A 1 JK4302 3AU04S-305-ZC-(LG) +5V_USB_1 USB DOWN STREAM +3.3V_NORMAL R4300 +5V_NORMAL 2.2 2 USB_DM3 IC4300 BD2242G R4301 2.2 3 USB_DP3 USB_ESD(SD05) RCLAMP0502BA 0DR050008AA R4305 VIN VOUT 4.7K 1 6 C4322 C4323 D4301 D4302 4 USB_ESD(KEC) 22uF 5V 10uF C4300 GND ILIM 0DTKE00018A 10V 10V 5 0.1uF 2 5 D4301-*1 16V 14K R4306 1% EN OC /USB_OCD1 3 4 EAH61515101 SEMTECH_USB_DMDP_ESD(MAIN) USB_CTL1 D4302-*1 R4304 DF3D6.8MS 10K EAH62735601 TOSHIBA_USB_DMDP_ESD(SUB) +5V_USB_2 USB2 MAX 1.0A 1 JK4300 3AU04S-305-ZC-(LG) USB DOWN STREAM R4302 2.2 2 USB_DM2 R4303 2.2 3 USB_DP2 SEMTECH_USB_DMDP_ESD(MAIN) RCLAMP0502BA EAH61515101 USB_ESD(SD05) 0DR050008AA D4300 C4310 4 C4311 D4303 5V 10uF 22uF 5 10V 10V USB_ESD(KEC) 0DTKE00018A D4303-*1 D4300-*1 DF3D6.8MS EAH62735601 TOSHIBA_USB_DMDP_ESD(SUB) +5V_USB_1 USB1 (3.0) USB_ESD(SD05) MAX 1.2A ZD4302 0DR050008AA 5V CNPLUS CO., LTD C4312 C4313 22uF 10uF JK4301 USB_ESD(KEC) 10V 10V 0DTKE00018A 5205-56209 ZD4302-*1 EAG63374203 USB3.0_TVS VBUS 1 D4304 D- USB_DM1 RCLAMP0544T.TCT 2 6.5VTO11.0V D+ USB_DP1 1 8 3 2 7 GND 4 3 6 STDA_SSRX- SSUSB_RXP 5 4 5 STDA_SSRX+ SSUSB_RXN 6 9 GND_DRAIN 7 USB3.0_TVS STDA_SSTX- D4305 8 RCLAMP0544T.TCT STDA_SSTX+ 9 6.5VTO11.0V 1 8 10 2 7 SHIELD 3 6 SSUSB_TXP 4 5 SSUSB_TXN 9 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-043_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-11-12 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB 43 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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+3.3V_NORMAL EU CLOSE TO JUNCTION R4601 10K EU R4602 100 SC_DET EU VA4601 C4604 5.6V 0.1uF EU SC_CVBS_IN Full Scart 1% EU 1/4W 75 R4607 VA4609 EU C4605 5.5V 47pF EU 50V EU EU R4615 AV_DET 0 22 COM_GND VA4610 DTV/MNT_V_OUT 21 5.5V SYNC_IN EU EU EU OPT 75 C4606 C4607 20 SYNC_OUT R4604 68pF 68pF 19 50V 50V SYNC_GND2 18 SYNC_GND1 EU R4614 17 22 RGB_IO 16 SC_FB R_OUT VA4602 15 5.6V RGB_GND EU EU 14 R4610 R_GND 75 13 D2B_OUT 12 VA4603 SC_R G_OUT 5.5V EU 11 EU D2B_IN R4608 75 10 G_GND 9 ID 8 VA4604 SC_G B_OUT 5.5V EU 7 AUDIO_L_IN R4611 EU 75 6 B_GND 5 AUDIO_GND 4 SC_B ICVL0518100Y500FR_ AUDIO_L_OUT VA4605 EU_ESD_SC_ID(SUB) 3 5.5V EU AUDIO_R_IN EU R4609 2 75 AUDIO_R_OUT 1 VA4600-*1 VA4600 EU 20V R4616 EU_ESD_SC_ID(MAIN) SIGN460005 15K PSC008-01 SC_ID JK4600 EU R4605 10K R4617 SC_L_IN 3.9K VA4611 R4612 5.6V EU 12K R4600 EU EU 470K EU R4606 10K SC_R_IN VA4606 5.6V R4613 EU EU 12K R4603 EU 470K EU BLM18PG121SN1D L4600 DTV/MNT_L_OUT VA4607 EU EU 5.6V C4600 C4602 EU 1000pF 4700pF 50V EU BLM18PG121SN1D L4601 DTV/MNT_R_OUT VA4608 EU EU 5.6V C4603 EU C4601 4700pF 1000pF 50V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-046_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART JACK_H 46 SCART_JACK_H Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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Ethernet Block C5000 C5001 0.1uF 0.01uF 16V 50V T-36TM9G_30150_02HF EAG35781015 EAG35781010 NEW_LAN_JACK_3SIM NEW_LAN_JACK_ESD(1st) OLD_LAN_JACK JK5000-*2 JK5000-*1 JK5000 36TM9G-30150-02HF BS-RV30330 RJ45VT-01SN002 FREEPORT RESOURCES ENTERPRISES CORP. U.D. ELECTRONIC CORP XML KOREA CO., LTD 1 1 1 1 1 1 EPHY_TDP 2 2 2 2 2 2 3 3 3 3 3 3 EPHY_TDN 4 4 4 4 4 4 EPHY_RDP 5 5 5 5 5 5 6 6 6 6 6 6 EPHY_RDN 7 7 7 7 7 7 VA5000 VA5001 VA5002 VA5003 8 8 8 5.5V 5.5V 5.5V 5.5V 8 8 8 LAN_ESD(MAIN) 9 9 9 LAN_ESD(MAIN) LAN_ESD(MAIN) LAN_ESD(MAIN) SHIELD 9 9 ICVS0518150FR_ ICVS0518150FR_ ICVS0518150FR_ ICVS0518150FR_ LAN_ESD(SUB) LAN_ESD(SUB) LAN_ESD(SUB) LAN_ESD(SUB) VA5000-*1 VA5001-*1 VA5002-*1 VA5003-*1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-050_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LAN_H 50 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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AUDIO AMP(NTP7515) SM-6045-100 GET_AMP_COIL L5802-*1 10.0uH +3.3V_NORMAL R5805 AMP_RESET_N 100 TAIYO_AMP_COIL NRS6045T100MMGK 1/16W R5806 C5806 L5802 L5801 10.0uH 4.7K 1000pF PZ1608U121-2R0TF 50V SPK_L+ 50V AUD_SCK +24V_AMP 22000pF R5807 1/10W C5807 3.3 R5811 5% C5821 C5805 0.1uF 4.7K 50V [EP]GND 0.1uF C5813 C5809 390pF VDD_IO GND_IO PGND1A PVDD1A PVDD1B 16V 10uF 50V CLK_I RESET BST1A OUT1A 35V C5819 0.47uF 50V AD C5814 390pF 50V C5822 R5812 R5808 1/10W TAIYO_AMP_COIL 0.1uF SPEAKER_L 3.3 50V 4.7K 5% NRS6045T100MMGK 40 39 38 37 36 35 34 33 32 31 L5805 NC_1 1 30 OUT1B 10.0uH SPK_L- VDD_PLL 2 29 PGND1B C5811 THERMAL 22000pF SM-6045-100 NC_2 3 41 28 BST1B 50V GET_AMP_COIL C5800 1uF L5805-*1 10V GND 4 27 VDR1 10.0uH NC_3 5 IC5800 26 NC_5 C5801 1uF 10V DVDD 6 NTP7515 25 AGND AUD_LRCH SDATA 7 24 VDR2 WCK 0x54 BST2A C5817 1uF C5818 1uF SM-6045-100 AUD_LRCK 8 23 10V 10V GET_AMP_COIL NC_4 9 22 PGND2A C5812 L5803-*1 10.0uH 22000pF AR5800 100 SDA 10 21 OUT2A 50V I2C_SDA4 11 12 13 14 15 16 17 18 19 I2C_SCL4 20 TAIYO_AMP_COIL NRS6045T100MMGK C5802 C5804 33pF 33pF L5803 50V 50V 10.0uH SCL FAULT MONITOR_0 MONITOR_1 MONITOR_2 BST2B PGND2B OUT2B PVDD2B PVDD2A SPK_R+ +3.3V_NORMAL R5809 1/10W +24V_AMP 3.3 5% C5823 R5813 R5801 0.1uF 4.7K 10K C5815 C5820 50V 390pF 0.47uF R5804 C5810 50V C5816 50V SPEAKER_R C 100 10uF 390pF 35V 50V TAIYO_AMP_COIL R5800 C5803 C5824 R5814 R5810 1/10W B Q5800 C5808 NRS6045T100MMGK AMP_MUTE 1000pF 0.1uF 4.7K 3.3 2N3904S 50V 5% 10K 22000pF L5804 50V E KEC_AMP_MUTE_TR WOOFER_MUTE 50V 10.0uH I2S_AMP SPK_R- SM-6045-100 GET_AMP_COIL L5804-*1 C 10.0uH 4P Box type B WAFER-ANGLE Q5800-*1 MMBT3904(NXP) NXP_AMP_MUTE_TR E TP5801 WOOFER_MUTE SPK_L+ 4 TP5802 I2S_AMP SPK_L- 3 SPK_R+ 2 SPK_R- 1 P5800 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-058_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-08 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR NTP_AMP 58 THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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+12V EU L6000 IC6000 AUD_OUT >> EU/CHINA_HOTEL_OPT AZ4580MTR-E1 EU C6004 EU EU 0.1uF C6000 50V DTV/MNT_L_OUT R6000 OUT1 1 8 VCC EU [SCART AUDIO MUTE] 10uF 2.2K EU OPT OPT EU R6011 C6008 C6002 R6002 R6004 33K IN1- 7 OUT2 SIGN600007 2.2K 2 DTV/MNT_R_OUT DTV/MNT_L_OUT 6800pF 470K C6003 33pF 10uF EU IN1+ EU 6 IN2- R6008 EU 33K OPT R6010 OPT 3 C6007 470K EU C6005 33pF 6800pF C R6013 VEE 5 IN2+ Q6000 B 1K 4 EU MMBT3904(NXP) EU_SCART_MUTE_ISAHAYA SCART_AMP_L_FB E EU Q6002 RT1P141C-T112 R6007 1/16W C E 100K EU SCART_AMP_R_FB SCART_MUTE OPT 5% EU R6012 1/16W R6006 R6020 100K 5.6K 0 OPT B SCART_Lout 5% EU 1/16W EU R6009 1/16W R6021 R6016 100K 330pF 220K 5% DTV/MNT_R_OUT PDTA114ET OPT C6009 R6005 0 5.6K 5% Q6002-*1 EU EU SCART_Rout C E EU R6015 1/16W 1/16W 100K 5% EU EU C OPT R6017 C6012 R6014 5% 220K 330pF Q6001 B 1K B MMBT3904(NXP) EU_SCART_MUTE_NXP CLOSE TO MSTAR E EU CLOSE TO MSTAR Near Place Scart AMP EU R6019 0 EU SCART_AMP_R_FB 1/16W 10K 5% R6003 EU R6018 0 EU SCART_AMP_L_FB 1/16W 10K 5% R6001 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-060_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART AMP Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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EARPHONE AMP HP_OUT_2.2uF(CN_DRA) HP_OUT_2.2uF(CN_DRA) IC6100 C6101-*1 TPA6138A2 2.2uF C6100-*1 2.2uF 10V 10V HP_OUT +INR +INL HP_OUT HP_OUT_1uF C6104 1 14 C6109 HP_OUT_1uF HP_OUT C6100 HP_OUT 18pF HP_OUT HP_OUT 18pF HP_OUT C6101 1uF R6100 R6106 R6104 R6101 1uF 10V 10K 43K HP_OUT -INR -INL HP_OUT 43K 10K 10V 2 13 HP_ROUT_MAIN HP_LOUT_MAIN HP_OUT R6103 HP_OUT R6102 HP_BYPASS 1% C6108 C6106 1% HP_BYPASS 43K 43K R6107 10pF 1% 1% OUTR OUTL 10pF 0 0 50V 3 12 50V R6108 HP_LOUT_AMP HP_ROUT_AMP +3.3V_NORMAL GND_1 UVP 4 11 HP_OUT MUTE GND_2 +3.3V_NORMAL 4.7K 5 10 R6105 SIDE_HP_MUTE VSS VDD 6 9 HP_OUT HP_OUT HP_OUT C6105 C6107 C6102 CN CP 1uF 0.1uF 1uF 7 8 10V 16V 10V C6103 1uF 10V HP_OUT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-061_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. HEADPHONE AMP FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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B-CAS (SMART CARD) INTERFACE +3.3V_NORMAL INT CMDVCC : STATUS +3.3V_NORMAL --------------------------------- HIGH HIGH CARD PRESENT LOW HIGH CARD not PRESENT SIGN630003 IC6300 TDA8024TT 2.7K 2.7K R6301 R6303 R6305 JAPAN JAPAN CLKDIV1 CLKDIV2 : F_CRD_CLK OPT ----------------------------- 1 0 CLKIN CLKDIV1 AUX2UC 1 28 JAPAN JAPAN JAPAN R6317 R6318 R6315 R6319 R6316 OPT OPT 1.2K 1.2K 1.2K 1.2K 1.2K CLKDIV2 AUX1UC 2 27 R6300 33 5V/3V I/OUC 3 26 SMARTCARD_PWR_SEL CAM_IREQ_N 2.7K JAPAN R6302 R6304 R6306 JAPAN OPT OPT PGND XTAL2 +5V_NORMAL 4 25 R6307 33 JAPAN S2 XTAL1 /PCM_CE1 SMARTCARD_DATA JAPAN 5 24 R6308 33 JAPAN EB_OE_N SMARTCARD_CLK L6300 R6309 33 JAPAN EB_BE_N0 SMARTCARD_DET BLM18PG121SN1D VDDP OFF R6310 33 JAPAN JAPAN 6 23 EB_BE_N1 SMARTCARD_RST JAPAN C6301 C6303 10uF 0.1uF S1 GND JAPAN 10V 16V 7 22 R6311 33 EB_WE_N SMARTCARD_VCC L6301 JAPAN +3.3V_NORMAL JAPAN VUP VDD BLM18PG121SN1D 8 21 JAPAN JAPAN JAPAN C6302 PRES RSTIN C6305 C6306 0.1uF 9 20 0.1uF 0.1uF 16V 16V 16V B-CAS SLOT PRES CMDVCC 10 19 P6300 I/O PORADJ 10057542-1311FLF(B CAS Slot) 11 18 AUX2 VCC JAPAN VCC 12 17 C1 C6307 0.33uF AUX1 RST 16V RST 13 16 C2 CGND CLK Place CLK C3 far from C2,C7,C4 and C8 CLK 14 15 C3 JAPAN C6304 RESERVED_1 0.1uF C4 16V GND C5 VPP JAPAN C6 JAPAN R6313 75 I/O C7 75 ohm in I/O is for short circuit Protection RESERVED C8 SW1 S1 +3.3V_NORMAL JAPAN JAPAN 10K R6312 R6314 1K SW2 S2 JAPAN_DIODE(SD05) JAPAN_DIODE(SD05) 0DR050008AA 0DR050008AA ZD6300 ZD6301 5V 5V JAPAN_DIODE(KEC) 0DTKE00018A ZD6300-*1 JAPAN_DIODE(KEC) 0DTKE00018A ZD6301-*1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-063_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JAPAN B-CAS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 63 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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FE_DEMOD1_TS_ERROR FE_DEMOD2_TS_ERROR FE_DEMOD3_TS_CLK 1. should be guarded by ground FE_DEMOD3_TS_SYNC 2. No via on both of them FE_DEMOD3_TS_VAL 3. Signal Width >= 12mils FE_DEMOD3_TS_ERROR close to Tuner Signal to Signal Width = 12mils FE_DEMOD3_TS_DATA +3.3V_TUNER Ground Width >= 24mils L6500 PZ1608U121-2R0TF close to TUNER 1 +3.3V_LNA_TU C6501 0.1uF TU_K/M/W_TW/BR/CO R6507 1K TU_K/M/W_TW/BR/CO TU_K/M/W_TW/BR/CO 2 RF_SWITCH_CTL_TU RF_SWITCH_CTL C6504 R6503 0.1uF 10K TU_ALL_IntDemod R6506 1K 3 IF_AGC_TU IF_AGC C6502 close to Tuner TU_ALL_IntDemod 0.1uF 16V TU_W_BR/TW TU_ALL AR6500-*1 AR6500 33 200 1/16W +3.3V_NORMAL PZ1608U121-2R0TF 4 I2C_SCL5_TU I2C_SCL5 C6505 I2C_SDA5 +3.3V_TUNER 47pF L6504 5 50V I2C_SDA5_TU +3.3V_TUNER 1608 perallel C6503 OPT because of derating 47pF 50V OPT TU_ALL_2178B TU_SIF TU_ALL_2178B TU_ALL_2178B R6513 0 R6516 R6517 R6504 200 200 10 6 IF_P_TU TU_ALL_IntDemod C6519 IF_P C6517 C6508 33pF L6502 TU_CVBS 22uF 0.1uF should be guarded by ground,Match GND VIA R6505 OPT 10V 16V 10 TU_H/M_EU/BR/TW/CO/KR E 7 IF_N_TU C6520 IF_N TU_ALL_IntDemod 33pF 0TR390609DC KEC_TU_ALL_2178B_TR(SUB) TU_H/M_EU/BR/TW/CO/KR B Q6502 2N3906S-RTK 8 TU_SIF_TU C E TU_M_KR/EU/CN // W_ALL 9 TU_CVBS_TU NXP_TU_ALL_2178B_TR(MAIN) L6501 +3.3V_TUNER B Q6502-*1 Global F/E Option Name PZ1608U121-2R0TF MMBT3906(NXP) 1. TU C EBK61012701 10 2. Tuner Name = TDJ’H’,TDj’M’... C6510 3. Country Name = KR,US,BR,EU ... 0.1uF 11 +3.3V_TU TU_M_KR/EU/CN // W_ALL T2 : Max 1.7A Example of Option name else : Max 0.7A 12 FE_DEMOD1_TS_ERROR close to Tuner TU_ALL_IntDemod = All Tuner type for Internal demod TU_M/W = apply TDSM&TDSW Type Tuner FE_DEMOD1_TS_ERROR TU_M/W_BCD_LDO(MAIN) TU_M/W_1.2V 14 FE_DEMOD1_TS_CLK FE_DEMOD1_TS_CLK IC6500 Demod_Core AP2132MP-2.5TRG1 R6519-*1 R6521-*1 TU_M/W_1.1V TU_M/W_1.1V 14’ Tuner Type for Global BCD [EP] TDJ’H’-G101D : Half NIM for EU,AJJA 15 FE_DEMOD1_TS_SYNC FE_DEMOD1_TS_SYNC 18K 10K R6521 TDJ’H’-H101F : Half NIM for US, KR TDJ’K’-T101F : Half NIM for TW FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL TU_M/W PG GND R2 16 1 8 TDJ’M’-C301D,F : FULL NIM for China THERMAL +3.3V_NORMAL C6516 10.5K R6519 TU_M/W_1.2V TDJ’M’-B101F : Brazil NIM with Isolater Type 0.1uF 16K EN ADJ 9 17 FE_DEMOD1_TS_DATA[0] 2 7 TDJ’M’-K101F : colombia NIM R1 R6500 TU_M/W 10K TDJ’M’-G101D,G105D,G151D : EU Combo&Full NIM VIN VOUT 18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[0-7] TDJ’M’-H101F,H151F : Korea PIP tuner 3 6 TDJ’W’-A151D : AJJA T2 PIP 19 FE_DEMOD1_TS_DATA[2] +5V_NORMAL VCTRL 4 2A 5 NC ESD_TU_M/W TU_M/W TU_M/W 5V ZD6501 EAN61387601 20 FE_DEMOD1_TS_DATA[3] C6500 C6518 0.1uF 10uF 16V 10V FE_DEMOD1_TS_DATA[4] TU_M/W 21 C6515 1uF FE_DEMOD1_TS_DATA[5] 25V 22 TU_M/W_HTC_LDO(SUB) 23 FE_DEMOD1_TS_DATA[6] Vout=0.6*(1+R1/R2) IC6500-*1 TJ2132GDP TAEJIN TECHNOLOGY CO., LTD. 24 FE_DEMOD1_TS_DATA[7] TU_M/W [EP]GND R6501 TU_M/W 100 /TU_RESET1 +3.3V_TUNER 25 /TU_RESET1_TU C6507 TU_M/W L6503 POK GND 16V PZ1608U121-2R0TF 1 8 0.1uF THERMAL 26 +3.3V_DEMOD_TU C6511 TU_M/W EN FB 9 2 7 0.1uF 27 I2C_SCL2_TU TU_M/W TU_K/M/W_NON_JP 0 R6502 L6505 AR6501 FE_DEMOD1_TS_CLK_1 FE_DEMOD1_TS_CLK IN OUT 33 TU_M/W TU_K/M/W_NON_JP 0 R6511 PZ1608U121-2R0TF FE_DEMOD1_TS_SYNC_1 FE_DEMOD1_TS_SYNC 3 6 Demod_Core OPT TU_K/M/W_NON_JP 0 R6512 28 D_Demod_Core C6513 I2C_SCL2 FE_DEMOD1_TS_VAL_1 FE_DEMOD1_TS_VAL TU_M/W 18pF I2C_SDA2 TU_K/M/W_NON_JP 0 R6514 BIAS SS C6506 50V FE_DEMOD1_TS_DATA0_1 FE_DEMOD1_TS_DATA[0] 4 5 0.1uF OPT 29 LNB_TX LNB_TX C6512 EAN63492001 18pF 50V 30 I2C_SDA2_TU 31 LNB_OUT LNB_OUT TU_JP 0 R6515 FE_DEMOD2_TS_CLK TU_JP 0 R6518 FE_DEMOD2_TS_SYNC TU_JP 0 R6520 34 FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_VAL TU_JP 0 R6522 FE_DEMOD2_TS_DATA 36 FE_DEMOD2_TS_SYNC FE_DEMOD2_TS_SYNC 37 FE_DEMOD2_TS_CLK FE_DEMOD2_TS_CLK L6506 +2.5V_Normal BLM18PG121SN1D Close to Tuner 38 +2.5V_DEMOD C6509 TU_JP 0.1uF 39 FE_DEMOD2_TS_VAL FE_DEMOD2_TS_VAL TU_JP 40 FE_DEMOD2_TS_DATA FE_DEMOD2_TS_DATA R6527 100 /TU_RESET2 45 /TU_RESET2_TU C6514 TU_JP 16V 0.1uF TU_JP THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-065_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_CIRCUIT Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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TU_H_US TU_H_BR TU_H_T2_KR TU_M_EU TU_W_JP TU6705 TU6701 TU6704 TU6702 TU6703 TDJH-H301F TDJK-T301F TDJM-H401F TDJM-G301D TDJW-J202F 1 2 +3.3V +3.3V +3.3V +3.3V B1[+3.3V] 1 1 1 1 1 +3.3V_LNA_TU 3 NC_1 NC NC_1 NC_1 NC_1 2 2 2 2 2 RF_SWITCH_CTL_TU 4 DIF_AGC DIF_AGC NC_2 AIF_AGC NC_2 3 3 3 3 3 IF_AGC_TU 5 SCL_RF SCL_RF SCL_RF SCL_RF SCL_RF 4 4 4 4 4 I2C_SCL5_TU 6 SDA_RF SDA_RF SDA_RF SDA_RF SDA_RF 5 5 5 5 5 I2C_SDA5_TU 7 DIF[P] DIF[P] NC_3 AIF[P] NC_3 6 6 6 6 6 IF_P_TU 8 DIF[N] DIF[N] NC_4 AIF[N] NC_4 7 7 7 7 7 IF_N_TU 9 SIF SIF SIF SIF NC_5 8 8 8 8 8 TU_SIF_TU 10 TDJH-G301D CVBS CVBS CVBS CVBS NC_6 9 9 9 9 9 TU_CVBS_TU TU6705-*1 11 TDJH-G301D NC_5 NC_2 NC_7 10 10 10 12 A1 B1 A1 B1 +3.3V_RF +3.3V_RF B2[+3.3V] 1 +3.3V A1 B1 A1 B1 11 11 11 +3.3V_TU 13 2 NC_1 47 47 ERROR ERROR NC_8 12 12 12 FE_DEMOD1_TS_ERROR TU_GND_B TU_GND_B IF_AGC 14 TU_GND_A TU_GND_A 3 GND_1 GND_1 GND_1 4 SCL_RF SHIELD SHIELD 13 13 13 5 SDA_RF MCLK MCLK 14 14 FE_DEMOD1_TS_CLK_1 IF[P] 16 6 SYNC SYNC 7 IF[N] 15 15 FE_DEMOD1_TS_SYNC_1 17 8 SIF VAILD VALID 16 16 FE_DEMOD1_TS_VAL_1 CVBS 18 9 D0 D0 17 17 FE_DEMOD1_TS_DATA0_1 19 A1 A1 B1 B1 D1 D1 18 18 FE_DEMOD1_TS_DATA[1] 47 TU_H_T2_CO TU_H_T2_TW/PA 20 TU6704-*2 TU6704-*1 D2 D2 SHIELD TDJM-K302F TDJM-K301F 19 19 FE_DEMOD1_TS_DATA[2] +3.3V +3.3V 21 1 NC_1 1 NC_1 D3 D3 2 2 20 20 FE_DEMOD1_TS_DATA[3] 3 NC_2 SCL_RF 3 NC_2 SCL_RF 22 4 SDA_RF 4 SDA_RF D4 D4 5 5 21 21 FE_DEMOD1_TS_DATA[4] 6 NC_3 NC_4 6 NC_3 NC_4 23 7 SIF 7 SIF D5 D5 8 8 22 22 FE_DEMOD1_TS_DATA[5] 9 CVBS NC_5 9 CVBS NC_5 24 10 +3.3V_RF 10 +3.3V_RF D6 D6 11 11 23 23 FE_DEMOD1_TS_DATA[6] 12 ERROR GND_1 12 ERROR GND_1 25 13 MCLK 13 MCLK D7 D7 14 14 24 24 FE_DEMOD1_TS_DATA[7] 15 SYNC VAILD 15 SYNC VAILD 26 16 D0 16 D0 RESET_DEMOD RESET_DEMOD M_RESET_DEMOD 17 17 25 25 25 /TU_RESET1_TU 18 D1 D2 18 D1 D2 27 19 D3 19 D3 +3.3V_DEMOD +3.3V_DEMOD B3[+3.3V] 20 D4 20 D4 26 26 26 +3.3V_DEMOD_TU 21 21 D5 D5 22 D6 22 D6 SCL_DEMOD SCL_DEMOD SCL_DEMOD 23 D7 23 D7 27 27 27 I2C_SCL2_TU 24 24 RESET_DEMOD RESET_DEMOD 25 +3.3V_DEMOD 25 +3.3V_DEMOD +1.2V_DEMOD +1.2V_DEMOD B4[+1.2V] 26 26 28 28 28 D_Demod_Core 27 SCL_DEMOD +1.2V_DEMOD 27 SCL_DEMOD +1.2V_DEMOD 30 28 NC_6 28 NC_6 NC_6 NC_3 NC_9 29 SDA_DEMOD 29 SDA_DEMOD 29 29 29 LNB_TX 31 30 30 A1 B1 A1 B1 SDA_DEMOD SDA_DEMOD SDA_DEMOD A1 47 B1 A1 47 B1 30 30 30 I2C_SDA2_TU 32 SHIELD SHIELD LNB LNB 31 31 LNB_OUT 33 A1 B1 GND GND_2 A1 B1 32 32 34 47 NC_10 TU_GND_A 33 TU_GND_B 35 A1 B1 M_ERROR SHIELD A1 B1 34 FE_DEMOD2_TS_ERROR 36 47 GND_3 TU_GND_A 35 TU_GND_B M_SYNC SHIELD 36 FE_DEMOD2_TS_SYNC M_MCLK 37 FE_DEMOD2_TS_CLK TU_W_JP_RDA5817 TU6703-*1 B5[+2.5V] TDJW-J301F 38 +2.5V_DEMOD 40 1 +3.3V_LNA M_VALID NC_1 39 FE_DEMOD2_TS_VAL 2 3 NC_2 41 4 SCL_RF M_DATA SDA_RF 40 FE_DEMOD2_TS_DATA 5 6 NC_3 42 7 NC_4 S_ERROR NC_5 41 FE_DEMOD3_TS_ERROR 8 9 NC_6 43 10 NC_7 S_SYNC 11 +3.3V_RF 42 FE_DEMOD3_TS_SYNC 44 NC_8 12 TDJM-B301F 13 GND_1 TDJM-C401D TU6702-*4 TU6702-*3 TU_M_AJ TU6702-*2 TU_M_CN TU6702-*1 S_MCLK TDJM-C401D TDJM-B301F TDJM-G305D TDJM-C301D 43 FE_DEMOD3_TS_CLK 45 1 +3.3V 1 +3.3V 1 +3.3V 1 B1[+3.3V] S_VALID NC_1 NC_1 NC_1 RF_SW_CTL 44 FE_DEMOD3_TS_VAL 2 3 NC_2 2 3 NC_2 2 3 NC_2 2 3 NC_1 46 4 SCL_RF 4 SCL_RF 4 SCL_RF 4 SCL_RF S_RESET_DEMOD SDA_RF SDA_RF SDA_RF SDA_RF 45 /TU_RESET2_TU 5 6 NC_3 5 6 NC_3 5 6 NC_3 5 6 NC_2 47 7 NC_4 7 NC_4 7 NC_4 7 NC_3 S_DATA SIF SIF SIF SIF 46 FE_DEMOD3_TS_DATA 8 9 CVBS 8 9 CVBS 8 9 CVBS 8 9 CVBS 48 RESET_M_DEMOD NC_5 NC_5 NC_5 NC_4 25 10 10 10 10 +3.3V_DEMOD +3.3V_RF +3.3V_RF +3.3V_RF NC_5 26 SCL_DEMOD 11 ERROR 11 ERROR 11 ERROR 11 ERROR 49 27 12 12 12 12 28 +1.2V_DEMOD 13 GND_1 13 GND_1 13 GND_1 13 GND_1 A1 B1 29 NC_9 14 MCLK 14 MCLK 14 MCLK 14 MCLK A1 B1 SDA_DEMOD SYNC SYNC SYNC SYNC 30 15 15 15 15 31 LNB 16 VAILD 16 VAILD 16 VAILD 16 VAILD 47 GND_2 D0 D0 D0 D0 32 17 17 17 17 TU_GND_A NC_10 D1 D1 D1 D1 33 18 18 18 18 TU_GND_B M_ERROR D2 D2 D2 D2 34 19 19 19 19 35 GND_3 20 D3 20 D3 20 D3 20 D3 SHIELD M_SYNC D4 D4 D4 D4 36 21 21 21 21 M_MCLK D5 D5 D5 D5 37 22 22 22 22 +2.5V_DEMOD D6 D6 D6 D6 38 23 23 23 23 M_VALID D7 D7 D7 D7 39 24 24 24 24 M_DATA RESET_DEMOD RESET_DEMOD RESET_DEMOD RESET_DEMOD 40 25 25 25 25 S_ERROR +3.3V_DEMOD +3.3V_DEMOD +3.3V_DEMOD B2[+3.3V] 41 26 26 26 26 S_SYNC SCL_DEMOD SCL_DEMOD SCL_DEMOD SCL_DEMOD 42 27 27 27 27 S_MCLK +1.2V_DEMOD +1.2V_DEMOD +1.2V_DEMOD B3[+1.1V] 43 28 28 28 28 S_VALID NC_6 NC_6 NC_6 NC_6 44 29 29 29 29 S_RESET_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD 45 30 30 30 30 S_DATA 46 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 47 47 47 47 A1 B1 47 SHIELD SHIELD SHIELD SHIELD SHIELD THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-067_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_SYMBOL_H Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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DVB-S2 LNB Part Allegro (Option:LNB) Input trace widths should be sized to conduct at least 3A Ouput trace widths should be sized to conduct at least 2A 3A +12V 2A D6904-*1 Max 1.3A LNB 40V LPH6050T-150M-R LNB_TSC LNB_SX34 L6900 D6902-*1 D6902 3.5A SS23L LNB_ONSEMI D6904 30V 40V 15uH 30V LNB_SMAB34 C6909 10uF C6903 C6905 C6906 C6907 25V 0.01uF 10uF 10uF 10uF LNB 50V 25V 25V 25V LNB LNB LNB LNB C6908 0.1uF close to Boost pin(#1) A_GND A_GND LNB 30V [EP]GND close to VIN pin(#15) Caution!! need isolated GND BOOST GNDLX R6904 NC_3 NC_2 SS23L C6910 0 A_GND LX D6901-*1 0.1uF LNB_TSC 50V 20 19 18 17 16 LNB D6901 VCP 1 15 VIN MBR230LSFT1G THERMAL A_GND LNB 2 14 GND LNB_OUT 21 30V LNB D6903 NC_1 3 13 VREG LNB_ONSEMI C6904 0.1uF LNB_SMAB34 IC6900 R6903 C6900 C6901 R6900 TDI A8303SESTR-T ISET 39K LNB 50V 40V 4 12 0.1uF 33pF 2.2K D6900 1W LNB 1/16W LNB LNB C6902 TDO 5 11 TCAP C6912 LNB LNB 0.22uF 1% LNB 25V D6903-*1 10 LNB LNB_SX34 6 7 8 9 0.1uF 40V BOOST [EP] NC_4 NC_3 PGND IRQ SCL SDA ADD TONECTRL 0.22uF LX 20 19 18 17 16 Close to Tuner A_GND NC_1 1 15 VIN +3.3V_NORMAL A_GND THERMAL Surge protectioin LNB 2 21 14 GND NC_2 3 13 VREG IC6900-*1 LNB TDI 4 DT1803 12 ISET R6907 LNB_DMBT 3.3K TDO TCAP C6911 5 11 OPT 10 6 7 8 9 IRQ SCL SDA ADD TONECTRL R6906 LNB 0 AR6900 LNB 33 EU/CIS R6905 R6908 JAPAN 0 0 I2C_SCL2 I2C_SDA2 LNB_TX THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-069_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 69 LNB THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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+3.3V_NORMAL LOCKAn_HTPDAn_3.3VPullup LOCKAn_HTPDAn_3.3VPullup R7136 +1.8V R7132 10K 10K LOCKAn LOCKAn_HTPDAn_3.3VPullup R7134 C 10K LOCKAn_HTPDAn_3.3VPullup B Q7105 R7128 2N3904S KEC_LOCKAn_HTPDAn_3.3VPullup_TR [51P Vx1 10K E HTPDAn_Video_Pull_down HTPDAn_Video LOCKAn_HTPDAn_3.3VPullup HTPDAn_OSD_Pull_down C C output wafer] R173 R174 HTPDAn_OSD R7130 100 B Q7103 2N3904S B Q7105-*1 MMBT3904(NXP) 10K 10K LOCKAn_IN KEC_LOCKAn_HTPDAn_3.3VPullup_TR NXP_LOCKAn_HTPDAn_3.3VPullup_TR E E 51pin_Wafer P7100 C SP14-11592-01-51Pin B Q7103-*1 MMBT3904(NXP) NXP_LOCKAn_HTPDAn_3.3VPullup_TR E 1 *moved from SHT1. +3.3V_NORMAL 2 TXDAP7_L 3 TXDAN7_L 4 LOCKAn_HTPDAn_3.3VPullup LOCKAn_HTPDAn_3.3VPullup R7135 5 TXDAP6_L +1.8V R7131 10K 6 TXDAN6_L 10K HTPDAn LOCKAn_HTPDAn_3.3VPullup R7133 C 7 10K LOCKAn_HTPDAn_3.3VPullup B Q7104 8 TXDAP5_L R7127 2N3904S 9 10K KEC_LOCKAn_HTPDAn_3.3VPullup_TR TXDAN5_L E LOCKAn_HTPDAn_3.3VPullup 10 C C R7129 100 B Q7102 B Q7104-*1 11 TXDAP4_L 2N3904S MMBT3904(NXP) HTPDAn_IN 12 TXDAN4_L KEC_LOCKAn_HTPDAn_3.3VPullup_TR NXP_LOCKAn_HTPDAn_3.3VPullup_TR E E 13 14 TXDAP3_L 15 C TXDAN3_L B Q7102-*1 16 MMBT3904(NXP) 17 TXDAP2_L E NXP_LOCKAn_HTPDAn_3.3VPullup_TR 18 TXDAN2_L +3.3V_NORMAL R7107-*1 10K 3D&L_DIM_EN_Micom 19 D DIODES_LGD/INX_Module_TCON_I2C_EN_FET(SUB) R7106 20 Module_MPLUS&NON_UF84(M+) 1K G Q7100-*1 TXDAP1_L 2N7002K +3.3V_NORMAL EBK42767801 21 R7125 0 TXDAN1_L 3D&L_DIM_EN S 3D&L_DIM_EN_Micom 22 R7104 L_DIM_EN_pulldown TCON_I2C_EN 10K Module_LGD_MPLUS&UF84(M+) 23 OPT R7107 TXDAP0_L 1K +3.3V_NORMAL G 24 TXDAN0_L EBK62072501 Module_LGD_INX_CSHOT_MPLUS&UF84(M+) R7105 1/16W R7121 0 25 R7115 I2C_SCL6 S D M+ MODULE : low 1K 5% 26 4.7K Q7100 LOCKAn_IN *Pin30(DATA_FORMAT) 40_INCH_INX_I2C_PULL_UP 2N7002KA 27 HIGH : 2 DIVISION KEC_LGD/INX_Module_TCON_I2C_EN_FET(MAIN) HTPDAn_IN LOW : NON DIVISION Module_LGD_SHARP_CSHOT&UF84(M+) R7119 28 R7101 10K Module_LGD_INX_CSHOT_MPLUS&UF84(M+) 33 OPT 29 AR7101 0 30 1/16W OPT TCON_I2C_EN 31 +3.3V_NORMAL *Pin31(BIT_SEL) G R7102 10K HIGH or NC : 10Bit 32 Module_LGD_INX_CSHOT_MPLUS&UF84(M+) LOW : 8Bit R7116 R7122 0 33 4.7K S I2C_SDA6 D 40_INCH_INX_I2C_PULL_UP D 34 Q7101 DIODES_LGD/INX_Module_TCON_I2C_EN_FET(SUB) 2N7002KA Q7101-*1 EBK62072501 G R7108 0 2N7002K 35 3D&L_DIM_EN EBK42767801 KEC_LGD/INX_Module_TCON_I2C_EN_FET(MAIN) OPT S 36 R7120 37 33 OPT 38 39 +3.3V_NORMAL M+ MODULE 40 *Pin36(GPLUS_MODE) 41 R7109 HIGH : High luminance 10K LOW or NC : Low Power 42 OPT LM14A : INTERNAL PULL-UP. 43 R7126 0 *Pin38 DATA_FORMAT_1_SOC CSOT, LGD60Hz,INX: N/C Module_MPLUS&UF84(M+) 44 SHARP,LGD120Hz: GND GPLUS : PWM_TIN R7103 LGD_Module_120Hz Module_LGD120Hz 45 Module_LGD120Hz_SHARP AR7100 R7110 0 46 10K 1/16W R7123 10K Data_Format_1 Data Input Format[1:0] 0 47 R7113 0 PWM_TIN 48 Module_MPLUS&NON_UF84(M+) *Mode 1 (NON Division) Data_Format_0 - Data Format 0(Pin37) = Low 49 +3.3V_NORMAL Data Format 1(Pin36) = Low 50 *Mode 3 (4 Division) - Data Format 0(Pin37) = Low PANEL_VCC 51 Data Format 1(Pin36) = High R7111 L7100 10K 52 MLB-201209-0120P-N2 OPT 51pin_12V R7100 0 C7100 C7101 PWM_TOUT 10uF 10uF Module_MPLUS&NON_UF84(M+) 25V 25V 51pin_12V 51pin_12V Module_LGD120HZ_MPLUS&NON_UF84(M+) R7112 10K THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-071_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-29 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Vx1 51P 71 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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eMMC I/F DVDD18_EMMC 3.3v power delete, 131120 R8116 R8117 1/16W 10K AR8104 1/16W 10K AR8103 10K 10K SAMSUNG ELECTRONIC CO.,LTD EAN63829501 IC8100 IC8100-*1 IC8100-*2 IC8100-*3 THGBMBG5D1KBAIL THGBMBG6D1KBAIL H26M41103HPR EMMC_DATA[0-7] KLM4G1FEPD-B031 AR8100 EMMC_DATA[0] 0 1/16W EMMC_DATA[1] A3 C8 A3 C8 A3 C7 EMMC_DATA[2] DAT0 NC_23 DAT6 DAT0 NC_23 DAT0 NC_22 A3 C7 A4 C9 A4 C9 A4 C8 DAT0 NC_22 DAT1 NC_24 DAT1 NC_24 DAT1 NC_23 A4 C8 EMMC_DATA[3] A5 C10 A5 C10 A5 C9 DAT1 NC_23 DAT2 NC_25 DAT2 NC_25 DAT2 NC_24 A5 C9 EMMC_DATA[4] B2 C11 B2 C11 B2 C10 DAT2 NC_24 DAT3 NC_26 DAT3 NC_26 DAT3 NC_25 B2 C10 EMMC_DATA[5] B3 C12 B3 C12 B3 C11 DAT3 NC_25 DAT4 NC_27 DAT4 NC_27 DAT4 NC_26 B3 C11 EMMC_DATA[6] B4 C13 B4 C13 B4 C12 DAT4 NC_26 DAT5 NC_28 DAT5 NC_28 DAT5 NC_27 B4 C12 B5 C14 B5 C14 B5 C13 DAT5 NC_27 EMMC_DATA[7] DAT6 NC_29 DAT6 NC_29 DAT6 NC_28 B5 C13 B6 D1 B6 D1 B6 C14 DAT6 NC_28 DAT7 NC_30 DAT5 DAT7 NC_30 DAT7 NC_29 B6 C14 D2 D2 D1 DAT7 NC_29 0 R8104 NC_31 NC_31 NC_30 D1 D3 D3 D2 NC_30 0 R8105 NC_32 NC_32 NC_31 D2 M6 D4 M6 D4 M6 D3 NC_31 0 R8106 CLK NC_33 CLK NC_33 CLK NC_32 M6 D3 M5 D12 M5 D12 M5 D4 CLK NC_32 0 R8107 CMD NC_34 CMD NC_34 CMD NC_33 M5 D4 D13 D13 D12 CMD NC_33 eMMC V5.0 GND NC_35 NC_35 NC_34 D12 D14 D14 D13 NC_34 NC_36 NC_36 NC_35 D13 A6 E1 A6 E1 A7 D14 NC_35 VSS_1 NC_37 VSS_1 NC_37 RFU_1 NC_36 A7 D14 A7 E2 A7 E2 E5 E1 RFU_1 NC_36 RFU_2 NC_38 RFU_2 NC_38 RFU_2 NC_37 E5 E1 C5 E3 C5 E3 G3 E2 RFU_2 NC_37 NC_21 NC_39 NC_21 NC_39 RFU_3 NC_38 G3 E2 AR8102 E5 E12 E5 E12 K6 E3 RFU_3 NC_38 RFU_4 NC_40 RFU_4 NC_40 RFU_4 NC_39 K6 E3 0 1/16W E8 E13 E8 E13 K7 E12 RFU_4 NC_39 RFU_5 NC_41 RFU_5 NC_41 RFU_5 NC_40 K7 E12 E9 E14 E9 E14 E8 E13 RFU_5 NC_40 EMMC_CLK VSF_1 NC_42 VSF_1 NC_42 VSF_1 NC_41 E8 E13 E10 F1 E10 F1 E9 E14 RFU_6 NC_41 DAT7 EMMC_CMD VSF_2 NC_43 VSF_2 NC_43 VSF_2 NC_42 E9 E14 F10 F2 F10 F2 E10 F1 RFU_7 NC_42 EMMC_RST VSF_3 NC_44 VSF_3 NC_44 VSF_3 NC_43 E10 F1 G3 F3 G3 F3 F10 F2 RFU_8 NC_43 RFU_9 NC_45 RFU_9 NC_45 VSF_4 NC_44 F10 F2 G10 F12 G10 F12 G10 F3 RFU_9 NC_44 RFU_10 NC_46 RFU_10 NC_46 VSF_5 NC_45 G10 F3 H5 F13 H5 F13 K10 F12 RFU_10 NC_45 DS NC_47 DS NC_47 VSF_6 NC_46 K10 F12 J5 F14 J5 F14 P10 F13 RFU_11 NC_46 C8107 VSS_5 NC_48 VSS_5 NC_48 VSF_7 NC_47 P10 F13 OPT 10pF K6 G1 K6 G1 H5 F14 RFU_13 NC_47 RFU_13 NC_49 RFU_13 NC_49 DS NC_48 H5 F14 50V K7 G2 K7 G2 G1 DS NC_48 RFU_14 NC_50 RFU_14 NC_50 NC_49 G1 EMMC_STRB K10 G12 K10 G12 G2 NC_49 RFU_15 NC_51 RFU_15 NC_51 NC_50 G2 P7 G13 P7 G13 G12 NC_50 R8103 RFU_16 NC_52 RFU_16 NC_52 NC_51 G12 P10 G14 P10 G14 G13 NC_51 10K RFU_17 NC_53 RFU_17 NC_53 NC_52 G13 H1 H1 G14 NC_52 NC_54 EMMC_STRB NC_54 NC_53 G14 H2 H2 H1 NC_53 NC_55 NC_55 NC_54 H1 K5 H3 K5 H3 K5 H2 NC_54 RSTN NC_56 RSTN NC_56 RSTN NC_55 K5 H2 H12 H12 H3 RSTN NC_55 C8100 DVDD18_EMMC H3 EMMC5.0_4G_TOSHIBA NC_57 NC_57 NC_56 H13 H13 H12 EMMC5.0_8G_TOSHIBA OPT 0.1uF NC_56 NC_58 NC_58 NC_57 H12 16V C6 H14 C6 H14 C6 H13 NC_57 VCCQ_1 NC_59 VCCQ_1 NC_59 VCCQ_1 NC_58 C6 H13 3.3V_EMMC M4 J1 M4 J1 M4 H14 VDD_1 NC_58 VCCQ_2 NC_60 VCCQ_2 NC_60 VCCQ_2 NC_59 M4 H14 N4 J2 N4 J2 N4 J1 VDD_2 NC_59 EMMC5.0_8G_HYNIX VCCQ_3 NC_61 VCCQ_3 NC_61 VCCQ_3 NC_60 N4 J1 P3 J3 P3 J3 P3 J2 VDD_3 NC_60 VCCQ_4 NC_62 VCCQ_4 NC_62 VCCQ_4 NC_61 P3 J2 Bottom P5 J12 P5 J12 P5 J3 VDD_4 NC_61 VCCQ_5 NC_63 VCCQ_5 NC_63 VCCQ_5 NC_62 P5 J3 DAT3 DAT4 DAT5 DAT6 EMMC_CLK_BALL EMMC_CMD_BALL EMMC_RESET_BALL OPT OPT J13 J13 J12 VDD_5 NC_62 C8108 C8109 C8105 C8106 NC_64 NC_64 NC_63 J12 0.1uF 2.2uF 0.1uF 2.2uF J14 EMMC_RESET_BALL J14 J13 NC_63 EMMC5.0_4G_SAMSUNG NC_65 NC_65 NC_64 J13 16V 10V 16V 10V E6 K1 E6 K1 E6 J14 NC_64 VCC_1 NC_66 VCC_1 NC_66 VCC_1 NC_65 E6 J14 F5 K2 F5 K2 F5 K1 VDDF_1 NC_65 VCC_2 NC_67 VCC_2 NC_67 VCC_2 NC_66 F5 K1 J10 K3 J10 K3 J10 K2 VDDF_2 NC_66 VCC_3 NC_68 VCC_3 NC_68 VCC_3 NC_67 J10 K2 K9 K12 K9 K12 K9 K3 VDDF_3 NC_67 VCC_4 NC_69 VCC_4 NC_69 VCC_4 NC_68 K9 K3 K13 K13 K12 VDDF_4 NC_68 NC_70 NC_70 NC_69 K12 EMMC_VDDI K14 K14 K13 NC_69 Bottom pattern 0.2mm NC_71 NC_71 NC_70 K13 C2 L1 C2 L1 C2 K14 NC_70 VDDI NC_72 VDDI NC_72 VDDI NC_71 C2 K14 OPT L2 L2 L1 VDDI NC_71 C8101 C8104 NC_73 NC_73 NC_72 L1 1uF 2.2uF L3 L3 L2 NC_72 NC_74 NC_74 NC_73 L2 10V 10V E7 L12 E7 L12 C4 L3 NC_73 VSS_2 NC_75 VSS_2 NC_75 VSSQ_1 NC_74 C4 L3 G5 L13 G5 L13 N2 L12 VSS_1 NC_74 VSS_3 NC_76 VSS_3 NC_76 VSSQ_2 NC_75 N2 L12 H10 L14 H10 L14 N5 L13 VSS_2 NC_75 VSS_4 NC_77 VSS_4 NC_77 VSSQ_3 NC_76 N5 L13 K8 M1 K8 M1 P4 L14 VSS_3 NC_76 VSS_6 NC_78 VSS_6 NC_78 VSSQ_4 NC_77 P4 L14 C8102 C8103 C8111 C4 M2 C4 M2 P6 M1 VSS_4 NC_77 0.1uF 2.2uF 4.7uF VSSQ_1 NC_79 VSSQ_1 NC_79 VSSQ_5 NC_78 P6 M1 N2 M3 EMMC_CLK_BALL N2 M3 A6 M2 VSS_5 NC_78 16V 10V 10V VSSQ_2 NC_80 VSSQ_2 NC_80 VSS_1 NC_79 A6 M2 OPT N5 M7 N5 M7 E7 M3 VSS_6 NC_79 VSSQ_3 NC_81 VSSQ_3 NC_81 VSS_2 NC_80 E7 M3 P4 M8 P4 M8 G5 M7 VSS_7 NC_80 VSSQ_4 NC_82 VSSQ_4 NC_82 VSS_3 NC_81 G5 M7 P6 M9 P6 M9 H10 M8 VSS_8 NC_81 VSSQ_5 NC_83 VSSQ_5 NC_83 VSS_4 NC_82 H10 M8 M10 M10 J5 M9 VSS_9 NC_82 NC_84 NC_84 VSS_5 NC_83 J5 M9 M11 M11 K8 M10 VSS_10 NC_83 NC_85 NC_85 VSS_6 NC_84 K8 M10 M12 M12 M11 VSS_11 NC_84 NC_86 NC_86 NC_85 M11 A1 M13 A1 M13 M12 NC_85 DAT3 NC_1 NC_87 NC_1 NC_87 NC_86 M12 A2 M14 A2 M14 A1 M13 NC_86 DAT4 NC_2 NC_88 NC_2 NC_88 NC_1 NC_87 A1 M13 A8 N1 A8 N1 A2 M14 NC_1 NC_87 DAT7 NC_3 NC_89 NC_3 NC_89 NC_2 NC_88 A2 M14 A9 N3 EMMC_CMD_BALL A9 N3 A8 N1 NC_2 NC_88 NC_4 NC_90 NC_4 NC_90 NC_3 NC_89 A8 N1 A10 N6 A10 N6 A9 N3 NC_3 NC_89 NC_5 NC_91 NC_5 NC_91 NC_4 NC_90 A9 N3 A11 N7 A11 N7 A10 N6 NC_4 NC_90 NC_6 NC_92 NC_6 NC_92 NC_5 NC_91 A10 N6 A12 N8 A12 N8 A11 N7 NC_5 NC_91 NC_7 NC_93 NC_7 NC_93 NC_6 NC_92 A11 N7 A13 N9 A13 N9 A12 N8 NC_6 NC_92 NC_8 NC_94 NC_8 NC_94 NC_7 NC_93 A12 N8 A14 N10 A14 N10 A13 N9 NC_7 NC_93 NC_9 NC_95 NC_9 NC_95 NC_8 NC_94 A13 N9 B1 N11 B1 N11 A14 N10 NC_8 NC_94 NC_10 NC_96 NC_10 NC_96 NC_9 NC_95 A14 N10 B7 N12 B7 N12 B1 N11 NC_9 NC_95 NC_11 NC_97 NC_11 NC_97 NC_10 NC_96 B1 N11 B8 N13 B8 N13 B7 N12 NC_10 NC_96 NC_12 NC_98 NC_12 NC_98 NC_11 NC_97 B7 N12 B9 N14 B9 N14 B8 N13 NC_11 NC_97 DAT6 NC_13 NC_99 NC_13 NC_99 NC_12 NC_98 B8 N13 B10 P1 B10 P1 B9 N14 NC_12 NC_98 NC_14 NC_100 NC_14 NC_100 NC_13 NC_99 B9 N14 B11 P2 B11 P2 B10 P1 NC_13 NC_99 NC_15 NC_101 NC_15 NC_101 NC_14 NC_100 B10 P1 B12 P8 B12 P8 B11 P2 NC_14 NC_100 Don’t Connect Power At VDDI EMMC_VDDI DVDD18_EMMC B13 B14 NC_16 NC_17 NC_102 NC_103 P9 P11 B13 B14 NC_16 NC_17 NC_102 NC_103 P9 P11 B12 B13 NC_15 NC_16 NC_101 NC_102 P7 P8 B11 B12 NC_15 NC_16 NC_101 RFU_12 P2 P7 NC_18 NC_104 NC_18 NC_104 NC_17 NC_103 B13 P8 C1 P12 C1 P12 B14 P9 NC_17 NC_102 (Just Interal LDO Capacitor) DAT5 C3 NC_19 NC_20 NC_105 NC_106 P13 C3 NC_19 NC_20 NC_105 NC_106 P13 C1 NC_18 NC_19 NC_104 NC_105 P11 B14 C1 NC_18 NC_103 P9 P11 C7 P14 C7 P14 C3 P12 NC_19 NC_104 NC_22 NC_107 NC_22 NC_107 NC_20 NC_106 C3 P12 C5 P13 NC_20 NC_105 NC_21 NC_107 C5 P13 P14 NC_21 NC_106 NC_108 P14 NC_107 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-081_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. eMMC Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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RS-232C Control INTERFACE AR11200 100 RS232C +3.5V_ST DOUT1 RIN1 OPT OPT VA11200 VA11201 ADUC 20S 02 010L ADUC 20S 02 010L RS232C 20V 20V RS232C C11204 0.1uF IC11200 MAX3232CDR C1+ VCC RS232C 1 16 C11200 0.1uF V+ GND RS232C 2 15 C11201 0.1uF C1- DOUT1 3 14 C2+ RIN1 RS232C 4 13 C11202 0.1uF C2- 5 12 ROUT1 SOC_RX RS232C V- DIN1 JK11200 RS232C 6 11 SOC_TX PEJ034-01 C11203 0.1uF DOUT2 DIN2 E_SPRING 7 10 3 EAG60841811 RIN1 TP3800 RIN2 ROUT2 8 9 DOUT1 TP3801 EAN41348201 R_SPRING 4 DOUT1 T_SPRING 5 RIN1 B_TERMINAL2 7B T_TERMINAL2 6B THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-112_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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[LM14A_ONLY] CLIP Top Side for Covershield To connect 28pin Wafer M13500 M13502 M13504 M13508 OS_MODULE 0 R13500 L/D_VSYNC EAG64250901 EAG64250901 EAG64250901 EAG64250901 L/D_VSYNC_SOC OS_MODULE 0 R13501 L/D_CLK L/D_CLK_SOC OS_MODULE 0 R13502 L/D_DI_SOC L/D_DI CLIP 1 - PUSH TYPE SMD Top Side for Covershield To connect 51P wafer 0 0.1uF C13500 TXDAN0_L R13503 LOCKAn_Video TXVBY1_0N LOCKAn 0 0.1uF C13501 TXDAP0_L R13504 HTPDAn_Video OPT OPT OPT TOP_SMD_GASKET TXVBY1_0P HTPDAn 0.1uF C13502 TXDAN1_L GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H TXVBY1_1N 19-21/R6C-FR1S1L/3T M13501 M13503 M13505 M13507 0.1uF C13503 TXDAP1_L +3.3V_NORMAL TXVBY1_1P VBY1_LOCK_LED MDS62110209 MDS62110209 MDS62110209 MDS62110209 0.1uF C13504 TXDAN2_L TXVBY1_2N LD100 0.1uF C13505 TXDAP2_L VBY1_LOCK_LED TXVBY1_2P 0.1uF C13506 TXDAN3_L TXVBY1_3N 0.1uF C13507 TXDAP3_L 8.5T TXVBY1_3P 0.1uF C13508 TXDAN4_L 3.3K R177 TXVBY1_4N 0.1uF C13509 TXDAP4_L TXVBY1_4P 0.1uF C13510 TXDAN5_L TXVBY1_5N E Q100 0.1uF C13511 TXDAP5_L TXVBY1_5P 2N3906S-RTK 0.1uF C13512 TXDAN6_L TXVBY1_6N KEC_VBY1_LOCK_LED_TR 0.1uF C13513 TXDAP6_L B TXVBY1_6P 0.1uF C13514 TXDAN7_L C TXVBY1_7N 0.1uF C13515 TXDAP7_L TXVBY1_7P THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-09-16 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_ONLY 135 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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LM14A ONLY, LM14A+URSA TUNER EMS GND SEPERATION TU_GND_B TU_GND_A TU_GND_A4_22nF TU_GND_B1_22nF C6700 C6703 TU_GND_A2_1nF TU_GND_A3_0ohm 0.022uF 0.022uF TU_GND_A6_3.3nF TU_GND_A1_0ohm C6706 TU_GND_B3_1nF TU_GND_B4_1nF C6710 R6700 630V 630V TU_EU R6701 C6707 C6708 C6709 3300pF 1000pF 0 TU_GND_B2_22ohm 0 TU_GND_A5_22ohm 1000pF 1000pF 3300pF 630V 630V R6703 R6704 630V 630V 630V 22 22 TU_GND_A1_1nF TU_GND_A2_22nF TU_GND_B2_0ohm TU_GND_B3_22nF TU_GND_B4_22nF TU_GND_A3_22nF R6701-*1 C6706-*1 C6707-*1 C6708-*1 R6700-*1 TU_GND_A4_1nF 0 0.022uF 0.022uF 1000pF 0.022uF 0.022uF R6704-*1 630V C6700-*1 630V 630V 630V 630V 1000pF 630V GND_A GND_B TU_GND_A EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP TU_GND_B EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP GND A_1 0 ohm 0 ohm 0 ohm X 0 ohm X 0 ohm GND B_1 X X X 22 nF X 22 nF X GND A_2 X X X 22 nF 22 nF 1 nF X GND B_2 X X X 22 ohm X 22 ohm X GND A_3 X 0 ohm 0 ohm X 0 ohm 22 nF 0 ohm X 22 nF GND B_3 1 nF 1 nF 1 nF 22 nF 1 nF 22 nF 1 nF GND A_4 X X X 22 nF 1 nF 22 ohm 22 ohm GND B_4 1 nF 22 nF GND A_5 X X X 22 ohm X 1 nF 1 nF 1 nF 22 nF 1 nF SMD_BOT GASKET_8.0X6.0X10.5H 70&79inch_EMI M13700 GASKET_8.0X6.0X10.5H MDS62110225 M13707 MDS62110225 SMD_BOT_OPT GASKET_8.0X6.0X10.5H SMD_BOT_EU M13701 GASKET_8.0X6.0X10.5H MDS62110225 M13703 EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP TU_BOT_SMD MDS62110225 SMD_BOT_OPT SMD1 GASKET_8.0X6.0X10.5H SMD_BOT M13702 GASKET_8.0X6.0X10.5H M13705 SMD2 MDS62110225 MDS62110225 SMD3 SMD_BOT_OPT GASKET_8.0X6.0X10.5H M13704 MDS62110225 70inch_EMI 79inch_EMI GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X12.5H M13706 M13706-*1 MDS62110225 MDS62110217 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-137_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR Tuner_GND THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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LB59J (LM14A+URSA11) Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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SPI_CK_SOC COMPENSATION_DONE OLED LM14A+URSA9 SPI_DI_SOC TXVBY1_0N FAN_ON LM14A UF68/64 +3.3V_NORMAL SPI_DO_SOC FRC_FLASH_SEL_SOC TXVBY1_0P CHIP CONFIG NVRAM +3.3V_NORMAL /SPI_CS TXVBY1_1N /TU_RESET2 Rohm_NVRAM IC101-*1 FRC_FLASH_WP GST_A LM14A UF74 BR24G256FJ-3 EAN62389502 TXVBY1_1P ROHM Semiconductor KOREA CORPORATION TXOSD_3P LOCKAn_OSD GCLK_A 4.7K 4.7K 4.7K Atmel_NVRAM WOL_WAKE_UP_SOC 4.7K A0 VCC IC101 1 8 TXOSD_3N URSA9_CONNECT MCLK_A PMIC_RESET 5V_DET_HDMI_1 AT24C256C-SSHL-T C100 A1 2 7 WP Data_Format_1 OPT EO_A OPT EAN61133501 ATMEL CORPORATION 0.1uF A2 3 6 SCL TXOSD_2P DATA_FORMAT_1_SOC LM14A_ONLY LOCKOUT12 /USB_OCD3 GND 4 5 SDA TXOSD_2N Data_Format_0 R108 R110 R115 DATA_FORMAT_0_SOC USB_CTL3 R122 TXOSD_1P URSA_RESET_SoC A0 VCC HTPDAn_OSD 1 8 L/D_VSYNC_SOC TXOSD_1N HTPDAn_Video IC100 Write Protection L/D_CLK_SOC LED1 A1 WP TXOSD_0P LGE5332(LM14A) 2 7 TXOSD_0N L/D_DI_SOC SPI_DI_SOC - Low : Normal Operation IC100 - High : Write Protection EB_DATA[0-7] LED0 A2 3 A0’h 6 SCL LGE5332(LM14A) EB_DATA[0] PWM_PM I2C_SCL1 V-BY-ONE AH14 4.7K 4.7K 4.7K FE_DEMOD1_TS_DATA[0-7] 4.7K EB_DATA[1] PCM_D[0]/GPIO147 FE_DEMOD1_TS_DATA[0] GND SDA I2C_SDA1 AG13 AH13 4 5 PCM_D[1]/GPIO148 TS1_D0/GPIO182 EB_DATA[2] FE_DEMOD1_TS_DATA[1] OPT OPT 33 D9 AF32 AG12 AG11 AR101 PWM_DIM TXVBY1_0N PCM_D[2]/GPIO149 TS1_D1/GPIO181 PWM0/GPIO152 LVSYNC/[VX1_0-] EB_DATA[3] AK22 AG10 FE_DEMOD1_TS_DATA[2] F10 AF31 R109 TXVBY1_0P R111 R116 PWM_DIM2 R123 PWM1/GPIO153 LHSYNC/[VX1_0+] EB_DATA[4] PCM_D[3]/GPIO119 TS1_D2/GPIO180 FE_DEMOD1_TS_DATA[3] F8 AG32 AK21 AJ11 FAN_ON TXVBY1_1N PCM_D[4]/GPIO120 TS1_D3/GPIO179 PWM2/GPIO154 LDE/[VX1_1-] EB_DATA[5] AL21 AH10 FE_DEMOD1_TS_DATA[4] E9 AG31 TXVBY1_1P AMP_RESET_N PWM3/GPIO155 LCK/[VX1_1+] EB_DATA[6] PCM_D[5]/GPIO121 TS1_D4/GPIO178 FE_DEMOD1_TS_DATA[5] AM23 AJ13 EB_DATA[7] PCM_D[6]/GPIO122 TS1_D5/GPIO177 FE_DEMOD1_TS_DATA[6] N5 AH31 AH20 AG9 PWM_PM TXVBY1_2N EB_ADDR[0-14] PCM_D[7]/GPIO123 TS1_D6/GPIO176 PWM_PM/GPIO7 R_ODD[7]/LVB0N/[VX1_2-] AH9 FE_DEMOD1_TS_DATA[7] AH30 TXVBY1_2P R_ODD[6]/LVB0P/[VX1_2+] EB_ADDR[0] TS1_D7/GPIO175 F4 AJ31 AG14 AH11 TXVBY1_3N PCM_A[0]/GPIO146 TS1_CLK/GPIO172 FE_DEMOD1_TS_CLK CHIP_CONFIG[3:0] /USB_OCD2 SAR0/GPIO46 R_ODD[5]/LVB1N/[VX1_3-] EB_ADDR[1] AL20 AJ10 G5 AJ32 TXVBY1_3P {LED1, SPI_DI,LED0, PWM_PM} USB_CTL2 SAR1/GPIO47 R_ODD[4]/LVB1P/[VX1_3+] EB_ADDR[2] PCM_A[1]/GPIO145 TS1_VLD/GPIO174 FE_DEMOD1_TS_VAL E5 AK32 AG15 AH12 FRC_FLASH_WP TXVBY1_4N PCM_A[2]/GPIO143 TS1_SYNC/GPIO173 FE_DEMOD1_TS_SYNC Value Mode Description SAR2/GPIO48 R_ODD[3]/LVB2N/[VX1_4-] EB_ADDR[3] AH15 E4 AK31 TXVBY1_4P TPI_DATA[0-7] 4’b1000 SB51_ExtSPI 51 boot from SPI DDTS_TX SAR3/GPIO49 R_ODD[2]/LVB2P/[VX1_4+] EB_ADDR[4] PCM_A[3]/GPIO142 TPI_DATA[0] 4’b1001 HEMCU_ExtSPI ARM boot from SPI G4 AL32 AM19 AK17 TXVBY1_5N PCM_A[4]/GPIO141 TS0_D0/GPIO161 SAR5 R_ODD[1]/LVBCLKN/[VX1_5-] EB_ADDR[5] AJ17 AL18 TPI_DATA[1] 4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC AL31 TXVBY1_5P 4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND R_ODD[0]/LVBCLKP/[VX1_5+] EB_ADDR[6] PCM_A[5]/GPIO139 TS0_D1/GPIO162 TPI_DATA[2] AK30 AJ16 AK18 4’b1100 DBUS for test only TXVBY1_6N PCM_A[6]/GPIO138 TS0_D2/GPIO163 G_ODD[7]/LVB3N/[VX1_6-] EB_ADDR[7] AH17 AL15 TPI_DATA[3] 4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication W5 AL30 TXVBY1_6P SPI_CK_SOC PM_SPI_CK/GPIO1 G_ODD[6]/LVB3P/[VX1_6+] EB_ADDR[8] PCM_A[7]/GPIO137 TS0_D3 TPI_DATA[4] 4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication V4 AK29 AM20 AL16 SPI_DI_SOC TXVBY1_7N PCM_A[8]/GPIO131 TS0_D4/GPIO165 4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; PM_SPI_DI/GPIO2 G_ODD[5]/LVB4N/[VX1_7-] EB_ADDR[9] AH19 AK15 TPI_DATA[5] V5 AL29 TXVBY1_7P SPI_DO_SOC PM_SPI_DO/GPIO3 G_ODD[4]/LVB4P/[VX1_7+] EB_ADDR[10] PCM_A[9]/GPIO129 TS0_D5/GPIO166 TPI_DATA[6] Y6 AJ20 AM16 /TU_RESET1 PM_SPI_CZ/GPIO0 EB_ADDR[11] PCM_A[10]/GPIO125 TS0_D6/GPIO167 TPI_DATA[7] R167 0 Y4 AK28 TXOSD_0N AK20 AK16 /SPI_CS GPIO_PM[6]/[SPI-CZ1N]/GPIO16 G_ODD[3]/LVA0N/[OSD_0-] EB_ADDR[12] PCM_A[11]/GPIO127 TS0_D7/GPIO168 OPT Y5 AM28 AG17 AL19 TXOSD_0P PCM_A[12]/GPIO136 TS0_CLK/GPIO171 TPI_CLK GPIO_PM[10]/[SPI-CZ2N]/GPIO20 G_ODD[2]/LVA0P/[OSD_0+] EB_ADDR[13] AJ19 AM17 LM14 HW Option M_RFModule_RESET G_ODD[0]/LVA1P/[OSD_1+] AL28 AK27 TXOSD_1N TXOSD_1P EB_ADDR[14] AG18 PCM_A[13]/GPIO132 TS0_VLD/GPIO169 AL17 TPI_VAL G_ODD[1]/LVA1N/[OSD_1-] PCM_A[14]/GPIO133 TS0_SYNC/GPIO170 TPI_SOP AK26 TXOSD_2N +3.3V_NORMAL B_ODD[7]/LVA2N/[OSD_2-] AH18 AH23 AL8 AL26 TXOSD_2P DDCA_CK DDCA_CK/GPIO8 B_ODD[6]/LVA2P/[OSD_2+] SM_Vsel CAM_IREQ_N PCM_IRQA_N/GPIO135 TS3_D0/GPIO206 POL EPI AK8 AM26 AM22 AH27 DDCA_DA TXOSD_3N SM_CLK EB_OE_N PCM_OE_N/GPIO126 TS3_D1/GPIO207 GST_A GST DDCA_DA/GPIO9 B_ODD[5]/LVACLKN/[OSD_3-] AG20 AJ23 AK25 TXOSD_3P GCLK B_ODD[4]/LVACLKP/[OSD_3+] SM_RST EB_BE_N1 PCM_IORD_N/GPIO128 TS3_D2/GPIO208 GCLK_A AL25 AL22 AG27 B_ODD[3]/LVA3N/[LOCKN] LOCKAn_Video SM_IO /PCM_CE1 PCM_CE_N/GPIO124 TS3_D3/GPIO209 MCLK_A MCLK AH28 AK24 AK19 AH24 10K 10K 10K 10K 10K 10K 10K 10K EB_WE_N PCM_WE_N/GPIO134 OPT_P 10K 10K TS3_D4/GPIO210 10K 10K SOC_TX GPIO3/TX1/GPIO58 B_ODD[2]/LVA3P/[HTPDN] HTPDAn_Video SM_VCC BIT2_1 BIT10_1 BIT11_1 BIT0_1 BIT1_1 BIT3_1 BIT4_1 BIT5_1 BIT6_1 BIT7_1 BIT8_1 AG21 AH26 BIT9_1 AH29 AL24 SOC_RX GPIO4/RX1 B_ODD[1]/LVA4N/[OSD_LOCKN] LOCKAn_OSD CAM_CD1_N PCM_CD_N/GPIO151 TS3_D5/GPIO211 SOE AA4 AK23 AH16 AJ25 FRC_FLASH_SEL_SOC GPIO23/[TX3]/GPIO78 B_ODD[0]/LVA4P/[OSD_HTPDN] HTPDAn_OSD PCM_RESET PCM_RESET/GPIO150 TS3_D6/GPIO212 FB W6 AJ14 AG26 R119 R112 R125 R128 R132 R135 R138 R140 R142 R146 R105 R148 /TU_RESET2 GPIO24/[RX3]/GPIO79 CAM_REG_N PCM_REG_N/GPIO144 TS3_D7/GPIO213 EO_A E/O F14 AG19 AH25 I2C_SCL6 DIM2/TX4/GPIO112 SM_CD EB_BE_N0 PCM_IOWR_N/GPIO130 TS3_CLK/GPIO216 HCONV F12 AG16 AJ26 BIT0 I2C_SDA6 DIM3/RX4/GPIO113 CAM_WAIT_N PCM_WAIT_N/GPIO140 TS3_VLD/GPIO214 DPM AG24 BIT1 TS3_SYNC/GPIO215 LOCKOUT12 LOCK AJ27 CPU_VID1 GPIO2/GPIO57 BIT2 C7 BIT3 BIT0 EMMC_IO15/[GPIO]/GPIO189 C6 BIT1 EMMC_IO17/[GPIO]/GPIO188 BIT4 AE2 C8 AJ28 GPIO_PM[0]/GPIO10 COMP1_DET EMMC_CMD EMMC_IO9/[EMMC_CMD]/GPIO183 GPIO8/[TS4_D[0]]/GPIO63 FE_DEMOD3_TS_DATA B8 AG28 BIT2 EMMC_IO14/[GPIO]/GPIO185 GPIO5/[TS4_CLK]/GPIO60 FE_DEMOD3_TS_CLK 1K R176 BIT5 U6 A9 AJ29 GPIO_PM[3]/GPIO13 DDTS_RX EMMC_CLK EMMC_IO10/[EMMC_CLK]/GPIO186 GPIO7/[TS4_VLD]/GPIO62 FE_DEMOD3_TS_VAL P4 B7 AG29 BIT6 GPIO_PM[4]/GPIO14 PCM_5V_CTL R175 TCON_I2C_EN BIT3 EMMC_IO16/[GPIO]/GPIO187 GPIO6/[TS4_SYNC]/GPIO61 FE_DEMOD3_TS_SYNC U5 22 B9 GPIO_PM[7]/GPIO17 EMMC_RST EMMC_IO11/[EMMC_RSTN]/GPIO190 AE5 A8 BIT7 PMIC_RESET BIT4 EMMC_IO12/[GPIO]/GPIO184 GPIO_PM[8]/GPIO18 C9 AJ7 AJ5 I2C_SCL3 GPIO28/SCK0/GPIO83 GPIO_PM[9]/GPIO19 COMPENSATION_DONE EMMC_STRB EMMC_IO8/[NAND-DQS]/GPIO191 BIT8 AH8 AG6 B6 I2C_SDA3 EMMC_DATA[0-7] BIT5 EMMC_IO13/[GPIO]/GPIO217 GPIO29/SDA0/GPIO84 GPIO_PM[13]/GPIO23 URSA9_CONNECT E11 BIT9 I2C_SCL1 DDCR_CK/SCK3/GPIO54 EMMC_DATA[6] C10 E10 I2C_SDA1 DDCR_DA/SDA3/GPIO53 EMMC_DATA[7] EMMC_IO6/[EMMC_D6]/GPIO221 AJ6 B11 I2C_SCL2 GPIO30/SCK4/GPIO85 EMMC_DATA[2] EMMC_IO7/[EMMC_D7]/GPIO220 AG8 A11 I2C_SDA2 GPIO31/SDA4/GPIO86 EMMC_DATA[1] EMMC_IO2/[EMMC_D2]/GPIO219 BIT10 AH7 P5 C11 I2C_SCL5 GPIO32/SCK5/GPIO87 GPIO_PM[1]/PM_UART1/GPIO11 /USB_OCD1 EMMC_DATA[0] EMMC_IO1/[EMMC_D1]/GPIO218 AJ8 P6 A12 AL2 BIT11 I2C_SDA5 GPIO33/SDA5/GPIO88 GPIO_PM[5]/PM_UART1/GPIO15 USB_CTL1 EMMC_DATA[3] EMMC_IO0/[EMMC_D0]/GPIO194 VIFP AJ4 B12 AM2 GPIO_PM[11]/PM_UART0/GPIO21 DATA_FORMAT_0_SOC EMMC_DATA[4] EMMC_IO3/[EMMC_D3]/GPIO193 VIFM AH4 C12 GPIO_PM[12]/PM_UART0/GPIO22 DATA_FORMAT_1_SOC EMMC_DATA[5] EMMC_IO4/[EMMC_D4]/GPIO192 B13 AK1 Close to MSTAR DTV_IF EMMC_IO5/[EMMC_D5]/GPIO222 SIFP AK2 10K 10K 10K 10K 10K 10K 10K 10K 10K SIFM 10K 10K 10K L6 G7 R183 100 C103 0.1uF OPT IF_P BIT10_0 BIT11_0 BIT2_0 BIT0_0 BIT1_0 BIT7_0 BIT8_0 BIT9_0 BIT4_0 BIT3_0 BIT5_0 BIT6_0 CPU_VID0 VID0/GPIO50 TESTPIN C107 M6 AK3 100pF CORE_VID0 VID1/GPIO51 IFAGC AD5 R126 LED0 R129 R106 R133 R136 R139 R141 LED0/GPIO29 R143 R147 R149 R113 R120 AD4 LED1 LED1/GPIO30 R184 100 C104 0.1uF OPT IF_N AB5 AJ1 C109 WOL_WAKE_UP_SOC WOL_INT_OUT/[GPIO]/GPIO52 TGPIO0/GPIO157 /USB_OCD3 33pF OPT E13 AJ2 C110 SPI1_DI/GPIO107 HP_DET TGPIO1/GPIO158 USB_CTL3 33pF D12 R4 SPI1_CK/GPIO106 RF_SWITCH_CTL TGPIO2/SCK1/GPIO159 I2C_SCL7 F11 R5 SPI2_DI/GPIO109 L/D_DI_SOC TGPIO3/SDA1/GPIO160 I2C_SDA7 D11 SPI2_CK/GPIO108 L/D_CLK_SOC E12 VSYNC_LIKE/GPIO105 L/D_VSYNC_SOC C101 0.1uF R185 47 D14 AM7 TU_SIF DIM0/GPIO110 SC_DET NC_1 C102 0.1uF R186 47 E14 AL7 R188 DIM1/GPIO111 AV1_CVBS_DET NC_2 C105 300 AM8 1000pF NC_3 ANALOG SIF OPT OPT AK7 NC_4 Close to MSTAR 20150123 version AL5 NC_5 +3.3V_NORMAL BIT(0/1) DVB ATSC JP AM5 GPIO34/GPIO89 CORE_VID1 M7 L100 00 TW/COL US NC_6 PZ1608U121-2R0TF Low High 01 CN/HK KR JP 10 EU BR T-con I2C R182 C106 BIT8 16Kbit 32Kbit 0.1uF BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP Protocol 10K 11 AJJA CI BIT(6/7) B/E(FRC) R187 00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default 0 00 LM14A only BIT9 Division NON_Division 4_Division IF_AGC Low High 01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT 01 N/A C108 BIT4 Display LCD OLED 0.047uF BIT10 Interface EPI Vx1 10 LM14A+URSA11 10 T/C T T/C ATSC 25V ISDB INT 4K@60Hz BIT5 Resolution FHD UHD 11 LM14A+URSA11 11 T2 BIT11 OS(DDR) WebOS Lite WebOS ATSC PIP 4K@120Hz +3.3V_TU +3.3V_LNA_TU +3.3V_NORMAL I2C PULL UP GPIO PULL UP Mstar Debug RS232C_Debug DDTS_Debug +3.3V_NORMAL MSTAR_DEBUG_OLD P101 +3.3V_NORMAL +3.3V_NORMAL DDTS_Debug R100 1.8K R101 1.8K R102 1.8K R103 1.8K R104 1.8K R107 1.8K R114 1.8K R121 1.8K R124 1.8K R127 1.8K R130 1.8K R131 1.8K R134 1.8K R137 1.8K MSTAR_DEBUG_NEW 12505WS-04A00 P100 P102 P103 12507WS-04L 12507WS-04L 12507WS-04L 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K I2C_SDA7 10K 10K 1 OPT I2C for URSA9 (URSA9 Only) OPT I2C_SCL7 OPT OPT 1 1 R152 1 R154 R164 I2C_SDA6 R156 R157 R161 R165 R170 R166 R168 I2C for LCD Module 2 R178 R180 I2C_SCL6 I2C_SDA1 2 SOC_RX 2 I2C for NAVRAM 2 DDTS_RX I2C_SCL1 10K 10K /TU_RESET1 DDCA_CK 3 I2C_SDA3 OPT OPT I2C for Micom RF_SWITCH_CTL 3 3 I2C_SCL3 3 AMP_RESET_N 4 R179 R181 I2C_SDA4 DDCA_DA I2C for Main Amp / Woofer AMP TCON_I2C_EN I2C_SCL4 4 4 SOC_TX 4 /USB_OCD3 5 DDTS_TX I2C_SDA5 I2C for tuner USB_CTL3 I2C_SCL5 5 5 5 /USB_OCD2 I2C_SDA2 USB_CTL2 I2C for tuner&LNB M_RFModule_RESET AR100 I2C_SCL2 33 PCM_5V_CTL I2C_SDA_MICOM I2C_SDA3 I2C_SCL_MICOM I2C_SCL3 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-001_00-HD SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-23 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 01 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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IC100 LGE5332(LM14A) WOL POWER ENABLE CONTROL +1.1V_VDDC_CPU +1.1V_VDDC +1.1V_VDDC 1st layer 4th layer +1.1V_Bypass Cap(CLOSE TO CHIP SIDE) J9 AC17 VDDC_1 VDDC_24 J10 AC18 BOTTOM_CAP_FOR_RIPPLE +1.1V_VDDC DVDD_DDR11 VDDC_2 VDDC_25 +3.5V_ST 0.1uF 0.1uF J11 AC19 +3.5V_WOL BOTTOM_CAP_FOR_RIPPLE 0.1uF 10uF VDDC_3 VDDC_26 IC201 4th layer J12 AC20 C263 C323 L226 VDDC_4 VDDC_27 AP2151WG-7 J13 AC21 10uF C208 0.1uF PZ1608U121-2R0TF VDDC_5 VDDC_28 10V 10uF 16V C322 PZ1608U121-2R0TF C276 C278 K9 AC22 C299 VDDC_6 VDDC_29 L203 10V K10 AD17 IN OUT K11 VDDC_7 VDDC_30 AD18 +3.3V_NORMAL 5 1 2A C324 C257 VDDC_8 VDDC_31 C242 R204 K12 AD19 0.47uF 0.47uF VDDC_9 VDDC_32 0.1uF GND 10K K13 AD20 2 6.3V 6.3V VDDC_10 VDDC_33 R203 OPT L9 AD21 Close to chip side VDDC_11 VDDC_34 1K L10 AD22 WOL_CTL 0 R202 OPT EN FLG VDDC_12 VDDC_35 4 3 L11 AE19 Close to chip side VDDC_13 VDDC_36 L12 AE20 VDDC_14 VDDC_37 R11 AE21 VDDC_15 VDDC_38 R12 AE22 VDDC_16 VDDC_39 Close to chip side R13 VDDC_17 +1.1V_VDDC T11 AE31 VDDC_18 VDD_SRAM_1 T12 AC24 1st layer 4th layer VDDC_19 VDD_SRAM_2 AVDDL_MOD11 T13 AD23 VDDC_20 VDD_SRAM_3 4th layer U11 AVDD_DMPLL VDDC_21 BOTTOM_CAP_FOR_RIPPLE U12 AE30 L202 BOTTOM_CAP_FOR_RIPPLE 0.1uF 0.1uF 0.1uF VDDC_22 CTRL_SRAMLDO PZ1608U121-2R0TF 10uF U13 1st layer 4th layer VDDC_23 C205 C261 10uF 0.1uF AVDDL_MOD11 A6 AVDD_DMPLL 10V 16V 2A C250 C230 C234 C235 EMMC_CTRL C320 W21 C238 0.1uF AVDDL_PREDRV_1 0.47uF 0.47uF 0.1uF Y21 6.3V AVDDL_PREDRV_2 6.3V AD29 V7 AVDDL_PREDRV_3 AVDD_NODIE 0.1uF AD30 DVDD_DDR11 C244 AVDDL_MOD_1 C245 W20 AVDD15_MOD AVDDL_MOD_2 Close to chip side Y20 L7 AVDDL_MOD_3 AVDDL_MHL3_1 AVDDP3P3_MHL U19 N12 C227 AVDD15_MOD_1 AVDDL_MHL3_2 Close to chip side V19 R7 AVDD15_MOD_2 AVDD3P3_MHL3_1 DVDD_DDR11 AA13 T7 AVDDL_USB3_1 AVDD3P3_MHL3_2 Close to chip side AF11 AVDD33_ADC AVDDL_USB3_2 AVDD_DMPLL U21 Y7 VDDC_CPU_1 AVDD3P3_ETH Close to chip side U22 AB7 +1.1V_VDDC_CPU VDDC_CPU_2 AVDD3P3_DADC_1 U23 AB8 VDDC_CPU_3 AVDD3P3_DADC_2 U24 AA7 +3.5V_WOL VDDC_CPU_4 AVDD3P3_ADC_1 AVDD_DMPLL U25 AA8 IC200 VDDC_CPU_5 AVDD3P3_ADC_2 V23 G9 AP2121N-3.3TRE1 V24 VDDC_CPU_6 AVDD3P3_USB_1 G10 AVDD_DMPLL +1.5V_Bypass Cap VDDC_CPU_7 AVDD3P3_USB_2 +1.5V_DDR AVDD_DDR V25 AB15 VIN 3 2 VOUT VDDC_CPU_8 AVDD3P3_USB3_1 W23 AF13 AVDD_AU33 VDDC_CPU_9 AVDD3P3_USB3_2 AVDDP3P3 1 W24 AD7 L227 VDDC_CPU_10 AVDD_AU33 GND PZ1608U121-2R0TF W25 AE7 VDDC_CPU_11 AVDD_EAR33 C246 1st layer 4th layer Y23 AF8 C243 1uF VDDC_CPU_12 AVDD3P3_DMPLL 0.1uF AVDD_DDR AVDD15_MOD Y24 AE15 10V L200 VDDC_CPU_13 VDDP_1 16V Y25 AF15 2A 0.47uF VDDC_CPU_14 VDDP_2 PZ1608U121-2R0TF 0.1uF 0.1uF 0.1uF 0.1uF AA22 0.1uF 0.1uF 0.1uF VDDC_CPU_15 L224 AA23 AA24 VDDC_CPU_16 V17 4A C207 10uF C201 10uF C247 C316 10uF C223 10uF C248 0.47uF C249 0.47uF AVDD_DMPLL 0.47uF VDDC_CPU_17 AVDD_MOD_1 10V 10V 6.3V PZ1608U121-2R0TF C314 0.1uF 10V 10V 6.3V 0.1uF AA25 V18 C209 C224 C225 C226 6.3V C203 C204 C287 VDDC_CPU_18 AVDD_MOD_2 AB24 W19 WOL_WAKE_UP VDDC_CPU_19 AVDD_LPLL_1 R205 AB25 Y19 VDDC_CPU_20 AVDD_LPLL_2 10K C307 C308 0 R169 AE16 WOL_WAKE_UP WOL_WAKE_UP_SOC MCP_VDDC_1 WOL_WAKE_UP AF16 N15 MCP_VDDC_2 AVDD_PLL_A N16 Close to chip side AVDD_PLL_B Close to chip side DVDD_NODIE VDDP_NAND_A VDDP_NAND_C L13 DVDD_NODIE DVDD_DDR11 H16 VDDP_3318_A/[3.3V/1.8V] K21 K16 C200 DVDD_DDR_1 VDDP_3318_C/[3.3V/1.8V] N21 AVDD_DDR 1uF DVDD_DDR_2 25V M21 J21 DVDD_DDR_3 AVDD_DDR_A_1 L21 K17 DVDD_DDR_4 AVDD_DDR_A_2 K18 AVDD_DDR_A_3 K19 AVDD_DDR_A_4 L17 AVDD_DDR_A_5 L19 AVDD_DDR_A_6 L20 AVDD_DDR_A_7 AVDD_DDR_B_1 J23 K22 GND JIG POINT +3.3V_Bypass Cap AVDD_DDR_B_2 K23 AVDD_DDR_B_3 M22 AVDD_DDR_B_4 N22 AVDD_DDR_B_5 4th layer JP202 JP204 JP205 JP203 N23 AVDD_DDR_B_6 +3.3V_NORMAL AVDDP3P3 P23 +3.3V_NORMAL AVDD_DDR_B_7 AVDD33_ADC 1st layer 4th layer L215 L221 PZ1608U121-2R0TF BOTTOM_CAP_FOR_RIPPLE BOTTOM_CAP_FOR_RIPPLE BOTTOM_CAP_FOR_RIPPLE L18 PZ1608U121-2R0TF 0.1uF AVDD_DDR_LDO_A 0.47uF L22 0.1uF AVDD_DDR_LDO_B C294 C295 AVDD5V_MHL 2A 1uF 1uF C251 0.47uF C252 0.47uF C222 2A C256 C217 25V 25V 6.3V 6.3V 10uF C268 10uF 10uF C274 H7 10V 10V C311 C253 10uF 10V AVDD_HDMI_5V_PA 10V R201 0 AVDD_DDR G8 GND_EFUSE 0.1uF Close to chip side C14 C229 AVDD_DDR_VBP_A_1 0.47uF C210 B14 +3.3V_NORMAL VDDP_NAND_C 5V_HDMI_1 AVDD5V_MHL AVDD_DDR_VBP_A_2 0 J17 Close to chip side Close to chip side AVDD_DDR_VBP_A_3 R207 J18 0.47uF C211 non_HDMI_LEAK AVDD_DDR_VBP_A_4 0.1uF R200 4th layer L208 10 B15 PZ1608U121-2R0TF AVDD_DDR_VBN_A_1 0.47uF C212 C15 AVDD_AU33 AVDD_DDR_VBN_A_2 C219 J19 +5V_NORMAL 4th layer AVDD_DDR_VBN_A_3 J20 0.47uF C213 2A C260 C266 0.1uF L219 HDMI_LEAK AVDD_DDR_VBN_A_4 10uF PZ1608U121-2R0TF R206 BOTTOM_CAP_FOR_RIPPLE 10K AVDDP3P3_MHL 10V AC30 C292 G AVDD_DDR_VBP_B_1 0.47uF C214 AVDD_DDR_VBP_B_2 AC31 K24 2A 0.47uF 6.3V L201 PZ1608U121-2R0TF BOTTOM_CAP_FOR_RIPPLE AVDD_DDR_VBP_B_3 0.47uF C215 S D L24 AVDD_DDR_VBP_B_4 0.1uF RUE003N02 C240 C241 0.1uF 0.47uF AD31 Q200 D VISHAY_HDMI_LEAK 6.3V AVDD_DDR_VBN_B_1 ROHM_HDMI_LEAK BOTTOM_CAP_FOR_RIPPLE AD32 C216 Q200-*1 AVDD_DDR_VBN_B_2 0.47uF VDDP_NAND_A G C221 L23 SI1012CR-T1-GE3 AVDD_DDR_VBN_B_3 Close to chip side M24 +1.8V S AVDD_DDR_VBN_B_4 0.47uF C220 L209 PZ1608U121-2R0TF Close to chip side 2A C236 C239 0.1uF 10uF 10V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-002_00-HD FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2014-12-21 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2_POWER 2 Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes

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DDR_VTT DDR_VTT AR400 AR407 M0_DDR_VREFDQ 56 56 Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ 1/16W 1/16W IC400 IC401 C424 0.1uF C453 0.1uF M0_DDR_A14 M1_DDR_A14 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M0_DDR_A8 M1_DDR_A8 M0_DDR_A11 M1_DDR_A11 EAN63053201 EAN63053201 C425 0.1uF C454 0.1uF M0_DDR_A6 M1_DDR_A6 M0_DDR_A0 N3 A0 DDR3 VREFCA M8 M0_DDR_A0 N3 A0 DDR3 VREFCA M8 AR401 AR408 P7 P7 4Gbit 56 56 M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1 1/16W 1/16W P3 P3 M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) C426 0.1uF C455 0.1uF N2 H1 N2 H1 M0_DDR_A1 M1_DDR_A1 M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ P8 P8 M0_DDR_A4 M1_DDR_A4 M0_DDR_A4 A4 M0_DDR_A4 A4 P2 P2 M0_DDR_A12 M1_DDR_A12 M0_DDR_A5 A5 M0_DDR_A5 A5 C427 0.1uF C456 0.1uF R8 L8 R400 240 R8 L8 R403 240 M0_DDR_BA1 M1_DDR_BA1 M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ R2 AVDD_DDR R2 AR402 AR409 M0_DDR_A7 A7 M0_DDR_A7 A7 AVDD_DDR T8 T8 56 56 M0_DDR_A8 A8 M0_DDR_A8 A8 1/16W 1/16W R3 B2 R3 B2 C428 0.1uF C457 0.1uF M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1 L7 D9 L7 D9 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A13 M1_DDR_A13 R7 G7 R7 G7 DDR3 1.5V bypass Cap - Place these caps near Memory DDR3 1.5V bypass Cap - Place these caps near Memory M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 N7 K2 N7 K2 M0_DDR_A9 M1_DDR_A9 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 C429 0.1uF C458 0.1uF A12/BC VDD_4 M0_DDR_A7 M1_DDR_A7 T3 K8 T3 K8 M0_DDR_A13 A13 VDD_5 M0_DDR_A13 A13 VDD_5 T7 N1 T7 N1 AR403 AR410 M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 56 56 M7 N9 M7 N9 1/16W 1/16W M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7 R1 R1 C430 0.1uF C459 0.1uF VDD_8 VDD_8 M0_DDR_A2 M1_DDR_A2 M2 R9 M2 R9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_A5 M1_DDR_A5 N8 N8 M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_A3 M1_DDR_A3 M3 M3 C431 0.1uF C460 0.1uF M0_DDR_BA2 BA2 M0_DDR_BA2 BA2 M0_DDR_A0 M1_DDR_A0 A1 A1 VDDQ_1 VDDQ_1 AR404 AR411 J7 A8 J7 A8 M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 56 56 K7 C1 K7 C1 1/16W 1/16W M0_D_CLKN CK VDDQ_3 M0_D_CLKN CK VDDQ_3 C432 0.1uF C461 0.1uF K9 C9 K9 C9 M0_DDR_BA0 M1_DDR_BA0 M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 D2 D2 M0_DDR_BA2 M1_DDR_BA2 VDDQ_5 VDDQ_5 L2 E9 L2 E9 M0_DDR_A15 M1_DDR_A15 M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 C433 0.1uF C462 0.1uF K1 F1 K1 F1 M0_DDR_A10 M1_DDR_A10 M0_DDR_ODT ODT VDDQ_7 M0_DDR_ODT ODT VDDQ_7 J3 H2 C410 0.1uF J3 H2 C440 0.1uF M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 AR405 AR412 K3 H9 C411 0.1uF K3 H9 C441 0.1uF 56 56 M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 1/16W 1/16W L3 L3 M0_DDR_WEN WE M0_DDR_WEN WE C434 0.1uF C463 0.1uF J1 J1 M0_DDR_WEN M1_DDR_WEN NC_1 NC_1 T2 J9 T2 J9 M0_DDR_CASN M1_DDR_CASN M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N RESET NC_2 IC100 L1 L1 M0_DDR_ODT M1_DDR_ODT NC_3 NC_3 C435 0.1uF C464 0.1uF LGE5332(LM14A) L9 L9 M0_DDR_RASN M1_DDR_RASN NC_4 NC_4 F3 F3 AR406 AR413 M0_DDR_DQS0 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n G3 IC400-*1 IC400-*2 G3 IC401-*1 K4B4G1646D-BCMA IC401-*2 SS_DDR3_2Gb IC401-*3 Hynix_DDR3_2Gb IC401-*4 56 56 K4B4G1646D-BCMA H5TQ4G63CFR_RDC H5TQ4G63CFR_RDC M0_DDR_DQS_N0 DQSL M0_DDR_DQS_N2 DQSL EAN63391401 K4B2G1646Q-BCMA H5TQ2G63FFR-RDC 1/16W 1/16W EAN63391401 EAN63053202 N3 M8 EAN63053202 F17 H28 N3 P7 A0 VREFCA M8 N3 P7 A0 VREFCA M8 P7 A0 A1 VREFCA N3 P7 A0 VREFCA M8 N3 EAN63667401 M8 N3 EAN63648701 M8 C436 0.1uF C465 0.1uF M0_DDR_A0 IO[3]/A-A0[AB-A0]/A-A6 IO[75]/B-A0[CD-A0]/B-A6 M1_DDR_A0 C7 A9 P3 A1 A2 P3 A1 A2 C7 A9 P3 N2 A2 H1 P3 A1 A2 P7 A0 A1 VREFCA P7 A0 A1 VREFCA M0_DDR_CKE M1_DDR_CKE C17 K31 M0_DDR_DQS1 DQSU N2 A3 VREFDQ H1 N2 A3 VREFDQ H1 M0_DDR_DQS3 P8 A3 A4 VREFDQ N2 A3 VREFDQ H1 P3 A2 P3 A2 M0_DDR_A1 IO[2]/A-A1[AB-A1]/A-A5 IO[80]/B-A1[CD-A1]/B-A5 M1_DDR_A1 VSS_1 P8 P2 A4 P8 P2 A4 DQSU VSS_1 P2 R8 A5 L8 P8 P2 A4 N2 P8 A3 VREFDQ H1 N2 P8 A3 VREFDQ H1 E17 J29 B7 B3 R8 A5 A6 ZQ L8 R8 A5 A6 ZQ L8 B7 B3 R2 A6 A7 ZQ R8 A5 A6 ZQ L8 P2 A4 A5 P2 A4 A5 M0_DDR_A2 IO[8]/A-A2[AB-A2]/A-A8 M1_DDR_A2 M0_DDR_DQS_N1 DQSU VSS_2 R2 A7 R2 A7 M0_DDR_DQS_N3 DQSU VSS_2 T8 A8 R2 A7 R8 R2 A6 ZQ L8 R8 R2 A6 ZQ L8 M0_D_CLKN M1_D_CLKN IO[83]/B-A2[CD-A2]/B-A8 E1 T8 R3 A8 B2 T8 R3 A8 B2 E1 R3 L7 A9 VDD_1 B2 D9 T8 R3 A8 B2 T8 A7 T8 A7 F18 K27 L7 A9 VDD_1 D9 L7 A9 VDD_1 D9 R7 A10/AP VDD_2 G7 L7 A9 VDD_1 D9 R3 A8 B2 R3 A8 B2 C437 0.1uF C466 0.1uF M0_DDR_A3 IO[12]/A-A3[AB-A3]/A-A4 IO[79]/B-A3[CD-A3]/B-A4 M1_DDR_A3 VSS_3 R7 A10/AP A11 VDD_2 VDD_3 G7 R7 A10/AP A11 VDD_2 VDD_3 G7 VSS_3 N7 A11 A12/BC VDD_3 VDD_4 K2 R7 A10/AP A11 VDD_2 VDD_3 G7 L7 A9 A10/AP VDD_1 VDD_2 D9 L7 A9 A10/AP VDD_1 VDD_2 D9 M0_D_CLK M1_D_CLK B18 K30 E7 G8 N7 T3 A12/BC VDD_4 K2 K8 N7 T3 A12/BC VDD_4 K2 K8 E7 G8 T3 A13 VDD_5 K8 N1 N7 T3 A12/BC VDD_4 K2 K8 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 R7 N7 A11 A12/BC VDD_3 VDD_4 G7 K2 M0_DDR_A4 M1_DDR_A4 M0_DDR_DM0 DML VSS_4 A13 VDD_5 VDD_6 N1 T7 A13 A14 VDD_5 VDD_6 N1 M0_DDR_DM2 DML VSS_4 M7 VDD_6 N9 T7 A13 A14 VDD_5 VDD_6 N1 T3 A13 VDD_5 K8 T3 A13 VDD_5 K8 IO[11]/A-A4[AB-A4]/A-BA1 IO[87]/B-A4[CD-A4]/B-BA1 D3 J2 M7 NC_5 VDD_7 N9 R1 M7 NC_5 VDD_7 N9 R1 D3 J2 NC_5 VDD_7 VDD_8 R1 M7 NC_5 VDD_7 N9 R1 M7 VDD_6 N1 N9 T7 M7 A14 VDD_6 N1 N9 E18 J28 M0_DDR_DM1 DMU M2 VDD_8 R9 M2 VDD_8 R9 M0_DDR_DM3 M2 BA0 VDD_9 R9 M2 VDD_8 R9 NC_5 VDD_7 R1 NC_5 VDD_7 R1 M0_DDR_A5 IO[14]/A-A5[AB-A5]/A-A0 IO[86]/B-A5[CD-A5]/B-A0 M1_DDR_A5 VSS_5 N8 BA0 VDD_9 N8 BA0 VDD_9 DMU VSS_5 N8 M3 BA1 N8 BA0 VDD_9 M2 BA0 VDD_8 VDD_9 R9 M2 BA0 VDD_8 VDD_9 R9 A17 K32 J8 M3 BA1 BA2 A1 M3 BA1 BA2 A1 J8 J7 BA2 VDDQ_1 A1 A8 M3 BA1 BA2 A1 N8 M3 BA1 N8 M3 BA1 M0_DDR_A6 IO[10]/A-A6[AB-A6]/A-A1 IO[90]/B-A6[CD-A6]/B-A1 M1_DDR_A6 VSS_6 J7 CK VDDQ_1 VDDQ_2 A8 J7 CK VDDQ_1 VDDQ_2 A8 VSS_6 K7 CK CK VDDQ_2 VDDQ_3 C1 J7 CK VDDQ_1 VDDQ_2 A8 BA2 VDDQ_1 A1 BA2 VDDQ_1 A1 D17 H31 E3 M1 K7 K9 CK VDDQ_3 C1 C9 K7 K9 CK VDDQ_3 C1 C9 E3 M1 K9 CKE VDDQ_4 C9 D2 K7 K9 CK VDDQ_3 C1 C9 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 J7 K7 CK CK VDDQ_2 VDDQ_3 A8 C1 M0_DDR_A7 M1_DDR_A7 M0_DDR_DQ0 DQL0 VSS_7 CKE VDDQ_4 VDDQ_5 D2 CKE VDDQ_4 VDDQ_5 D2 M0_DDR_DQ16 DQL0 VSS_7 L2 VDDQ_5 E9 CKE VDDQ_4 VDDQ_5 D2 K9 CKE VDDQ_4 C9 K9 CKE VDDQ_4 C9 IO[13]/A-A7[AB-A7]/A-A2 IO[78]/B-A7[CD-A7]/B-A2 F7 M9 L2 K1 CS VDDQ_6 E9 F1 L2 K1 CS VDDQ_6 E9 F1 F7 M9 K1 CS ODT VDDQ_6 VDDQ_7 F1 L2 K1 CS VDDQ_6 E9 F1 L2 VDDQ_5 D2 E9 L2 VDDQ_5 D2 E9 C16 J32 M0_DDR_DQ1 DQL1 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 M0_DDR_DQ17 J3 RAS VDDQ_8 H2 J3 ODT VDDQ_7 H2 K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1 M0_DDR_A8 IO[0]/A-A8[AB-A8]/A-A9 IO[77]/B-A8[CD-A8]/B-A9 M1_DDR_A8 VSS_8 K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 DQL1 VSS_8 K3 L3 CAS VDDQ_9 H9 K3 RAS VDDQ_8 H9 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 AVDD_DDR E16 G30 F2 P1 L3 CAS WE VDDQ_9 J1 L3 CAS WE VDDQ_9 J1 F2 P1 T2 WE NC_1 J1 J9 L3 CAS WE VDDQ_9 J1 K3 L3 RAS CAS VDDQ_8 VDDQ_9 H9 K3 L3 RAS CAS VDDQ_8 VDDQ_9 H9 M0_DDR_CKE M0_DDR_A9 M1_DDR_A9 M0_DDR_DQ2 DQL2 VSS_9 T2 NC_1 J9 T2 NC_1 J9 M0_DDR_DQ18 DQL2 VSS_9 RESET NC_2 L1 T2 NC_1 J9 WE J1 WE J1 IO[5]/A-A9[AB-A9]/A-A11 IO[73]/B-A9[CD-A9]/B-A11 F8 P9 RESET NC_2 NC_3 L1 RESET NC_2 NC_3 L1 F8 P9 NC_3 L9 RESET NC_2 NC_3 L1 T2 RESET NC_1 NC_2 J9 T2 RESET NC_1 NC_2 J9 B19 L30 M0_DDR_DQ3 DQL3 NC_4 L9 NC_4 L9 M0_DDR_DQ19 F3 DQSL NC_4 NC_6 T7 NC_4 L9 NC_3 L1 NC_3 L1 M0_DDR_A10 IO[9]/A-A10[AB-A10]/A-RASZ IO[93]/B-A10[CD-A10]/B-RASZ M1_DDR_A10 VSS_10 F3 G3 DQSL NC_6 T7 F3 G3 DQSL DQL3 VSS_10 G3 DQSL F3 G3 DQSL F3 NC_4 L9 T7 F3 NC_4 L9 H3 T1 1K R418 B17 J30 DQSL DQSL H3 T1 C7 DQSU VSS_1 A9 DQSL G3 DQSL DQSL NC_6 G3 DQSL DQSL M0_DDR_DQ4 AVDD_DDR OPT C7 A9 C7 A9 M0_DDR_DQ20 C7 A9 1K R405 M0_DDR_A11 IO[6]/A-A11[AB-A11]/A-A7 IO[84]/B-A11[CD-A11]/B-A7 M1_DDR_A11 DQL4 VSS_11 B7 DQSU VSS_1 B3 B7 DQSU VSS_1 B3 DQL4 VSS_11 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_1 B3 C7 DQSU VSS_1 A9 C7 DQSU VSS_1 A9 AVDD_DDR D20 L29 H8 T9 E7 DQSU VSS_2 VSS_3 E1 G8 E7 DQSU VSS_2 VSS_3 E1 G8 H8 T9 E7 D3 DML VSS_3 VSS_4 G8 J2 E7 DQSU VSS_2 VSS_3 E1 G8 B7 DQSU VSS_2 B3 E1 B7 DQSU VSS_2 B3 E1 M0_DDR_A12 IO[26]/A-A12[AB-A12]/A-BG0 M1_DDR_A12 M0_DDR_DQ5 DQL5 VSS_12 D3 DML VSS_4 J2 D3 DML VSS_4 J2 M0_DDR_DQ21 DQL5 VSS_12 DMU VSS_5 J8 D3 DML VSS_4 J2 E7 VSS_3 G8 E7 VSS_3 G8 IO[85]/B-A12[CD-A12]/B-BG0 G2 DMU VSS_5 VSS_6 J8 DMU VSS_5 VSS_6 J8 G2 E3 VSS_6 M1 DMU VSS_5 VSS_6 J8 D3 DML DMU VSS_4 VSS_5 J2 D3 DML DMU VSS_4 VSS_5 J2 F16 G31 M0_DDR_DQ6 DQL6 E3 DQL0 VSS_7 M1 E3 DQL0 VSS_7 M1 M0_DDR_DQ22 F7 DQL0 DQL1 VSS_7 VSS_8 M9 E3 DQL0 VSS_7 M1 VSS_6 J8 VSS_6 J8 M0_1_DDR_VREFDQ M0_DDR_A13 IO[4]/A-A13[AB-A13]/A-PARITY IO[74]/B-A13[CD-A13]/B-PARITY M1_DDR_A13 F7 F2 DQL1 VSS_8 M9 P1 F7 F2 DQL1 VSS_8 M9 P1 DQL6 F2 F8 DQL2 VSS_9 P1 P9 F7 F2 DQL1 VSS_8 M9 P1 E3 F7 DQL0 VSS_7 M1 M9 E3 F7 DQL0 VSS_7 M1 M9 B16 J31 H7 F8 DQL2 DQL3 VSS_9 VSS_10 P9 F8 DQL2 DQL3 VSS_9 VSS_10 P9 H7 H3 DQL3 DQL4 VSS_10 VSS_11 T1 F8 DQL2 DQL3 VSS_9 VSS_10 P9 F2 DQL1 DQL2 VSS_8 VSS_9 P1 F2 DQL1 DQL2 VSS_8 VSS_9 P1 M0_DDR_VREFDQ M0_DDR_RESET_N M0_DDR_A14 IO[7]/A-A14[AB-A14]/A-A13 M1_DDR_A14 M0_DDR_DQ7 DQL7 H3 DQL4 VSS_11 T1 H3 DQL4 VSS_11 T1 M0_DDR_DQ23 DQL7 H8 DQL5 VSS_12 T9 H3 DQL4 VSS_11 T1 F8 H3 DQL3 VSS_10 P9 T1 F8 H3 DQL3 VSS_10 P9 T1 IO[81]/B-A14[CD-A14]/B-A13 B1 H8 G2 DQL5 VSS_12 T9 H8 G2 DQL5 VSS_12 T9 B1 G2 H7 DQL6 H8 G2 DQL5 VSS_12 T9 H8 DQL4 VSS_11 T9 H8 DQL4 VSS_11 T9 E20 M28 DQL5 VSS_12 DQL5 VSS_12 R416 DQL6 DQL6 DQL6 1K 1% H7 H7 DQL7 H7 G2 G2 B1 M0_DDR_A15 VSSQ_1 DQL7 DQL7 VSSQ_1 VSSQ_1 DQL7 DQL6 DQL6 R410 1K 1% B1 B1 B1 H7 H7 IO[19]/A-A15[AB-A15]/A-A3 IO[96]/B-A15[CD-A15]/B-A3 M1_DDR_A15 D7 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 DQU0 VSSQ_1 VSSQ_2 B9 D7 B9 D7 C3 DQU0 VSSQ_2 B9 D1 D7 DQU0 VSSQ_1 VSSQ_2 B9 DQL7 VSSQ_1 B1 DQL7 VSSQ_1 B1 1% E19 L28 M0_DDR_DQ8 DQU0 C3 DQU1 VSSQ_3 D1 C3 DQU1 VSSQ_3 D1 M0_DDR_DQ24 C8 DQU1 DQU2 VSSQ_3 VSSQ_4 D8 C3 DQU1 VSSQ_3 D1 D7 DQU0 VSSQ_2 B9 D7 DQU0 VSSQ_2 B9 10K M0_DDR_BA0 IO[24]/A-BA0[AB-BA0]/A-A10 IO[88]/B-BA0[CD-BA0]/B-A10 M1_DDR_BA0 VSSQ_2 C8 C2 DQU2 VSSQ_4 D8 E2 C8 C2 DQU2 VSSQ_4 D8 E2 DQU0 VSSQ_2 C2 A7 DQU3 VSSQ_5 E2 E8 C8 C2 DQU2 VSSQ_4 D8 E2 C3 C8 DQU1 VSSQ_3 D1 D8 C3 C8 DQU1 VSSQ_3 D1 D8 C18 L31 C3 D1 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 C3 D1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 A7 DQU3 DQU4 VSSQ_5 VSSQ_6 E8 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 R445 M0_DDR_BA1 M1_DDR_BA1 M0_DDR_DQ9 DQU1 VSSQ_3 A2 DQU5 VSSQ_7 F9 A2 DQU5 VSSQ_7 F9 M0_DDR_DQ25 DQU1 VSSQ_3 B8 DQU6 VSSQ_8 G1 A2 DQU5 VSSQ_7 F9 A7 A2 DQU4 VSSQ_6 E8 F9 A7 A2 DQU4 VSSQ_6 E8 F9 IO[20]/A-BA1[AB-BA1]/A-CASZ IO[92]/B-BA1[CD-BA1]/B-CASZ C8 D8 B8 A3 DQU6 VSSQ_8 G1 G9 B8 A3 DQU6 VSSQ_8 G1 G9 C8 D8 A3 DQU7 VSSQ_9 G9 B8 A3 DQU6 VSSQ_8 G1 G9 B8 DQU5 VSSQ_7 G1 B8 DQU5 VSSQ_7 G1 F19 K28 M0_DDR_DQ10 DQU2 DQU7 VSSQ_9 DQU7 VSSQ_9 M0_DDR_DQ26 DQU7 VSSQ_9 A3 DQU6 VSSQ_8 G9 A3 DQU6 VSSQ_8 G9 M0_DDR_BA2 IO[21]/A-BA2[AB-BA2]/A-BA0 IO[82]/B-BA2[CD-BA2]/B-BA0 M1_DDR_BA2 VSSQ_4 DQU2 VSSQ_4 DQU7 VSSQ_9 DQU7 VSSQ_9 C479 G22 N28 C2 E2 C2 E2 C472 M0_D_CLK 1% M0_DDR_RASN M1_DDR_RASN M0_DDR_DQ11 DQU3 VSSQ_5 M0_DDR_DQ27 DQU3 VSSQ_5 0.1uF 1% IO[15]/A-RASZ[AB-RASZ]/A-ODT IO[97]/B-RASZ[CD-RASZ]/B-ODT A7 E8 A7 E8 0.1uF C483 R412 F21 N27 R417 M0_DDR_DQ12 DQU4 VSSQ_6 M0_DDR_DQ28 DQU4 VSSQ_6 C474 56 C477 R411 M0_DDR_CASN IO[17]/A-CASZ[AB-CASZ]/A-WEZ IO[94]/B-CASZ[CD-CASZ]/B-WEZ M1_DDR_CASN A2 F9 A2 F9 1000pF 0.01uF E21 L27 M0_DDR_DQ13 DQU5 M0_DDR_DQ29 1000pF 50V 1% M0_DDR_WEN M1_DDR_WEN VSSQ_7 DQU5 VSSQ_7 1K IO[16]/A-WEZ[AB-WEZ]/A-A12 IO[89]/B-WEZ[CD-WEZ]/B-A12 B8 G1 B8 G1 50V 50V 1K F20 M27 M0_DDR_DQ14 DQU6 M0_DDR_DQ30 M0_DDR_ODT IO[25]/A-ODT[AB-ODT]/A-ACTZ IO[95]/B-ODT[CD-ODT]/B-ACTZ M1_DDR_ODT VSSQ_8 DQU6 VSSQ_8 C19 M31 A3 G9 A3 G9 R413 M0_DDR_CKE IO[18]/A-CKE[AB-CKE]/A-CKE M1_DDR_CKE M0_DDR_DQ15 DQU7 VSSQ_9 SS_DDR3_2Gb Hynix_DDR3_2Gb M0_DDR_DQ31 DQU7 VSSQ_9 56 IO[91]/B-CKE[CD-CKE]/B-CKE IC400-*3 K4B2G1646Q-BCMA IC400-*4 H5TQ2G63FFR-RDC F15 G32 1% M0_DDR_RESET_N IO[1]/A-RST[AB-RST]/A-RST IO[76]/B-RST[CD-RST]/B-RST M1_DDR_RESET_N N3 EAN63667401 M8 N3 EAN63648701 M8 A20 N32 P7 A0 A1 VREFCA P7 A0 A1 VREFCA M0_D_CLK IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ M1_D_CLK P3 N2 A2 H1 P3 N2 A2 H1 B20 M30 P8 P2 A3 A4 VREFDQ P8 P2 A3 A4 VREFDQ M0_D_CLKN M0_D_CLKN IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK M1_D_CLKN R8 A5 A6 ZQ L8 R8 A5 A6 ZQ L8 E15 G29 R2 T8 A7 R2 T8 A7 M0_DDR_CS1 IO[23]/A-CSB1[AB-CSB1]/A-CSB1 IO[99]/B-CSB1[CD-CSB1]/B-CSB1 M1_DDR_CS1 R3 L7 A8 A9 VDD_1 B2 D9 R3 L7 A8 A9 VDD_1 B2 D9 D15 F32 R7 A10/AP A11 VDD_2 VDD_3 G7 R7 A10/AP A11 VDD_2 VDD_3 G7 M0_DDR_CS2 IO[22]/A-CSB2[AB-CSB2]/A-CSB2 IO[98]/B-CSB2[CD-CSB2]/B-CSB2 M1_DDR_CS2 N7 T3 A12/BC VDD_4 K2 K8 N7 T3 A12/BC VDD_4 K2 K8 M7 A13 NC_5 VDD_5 VDD_6 VDD_7 N1 N9 T7 M7 A13 A14 NC_5 VDD_5 VDD_6 VDD_7 N1 N9 AVDD_DDR M1_DDR_CKE R1 R1 VDD_8 VDD_8 M2 R9 M2 R9 BA0 VDD_9 BA0 VDD_9 N8 N8 BA1 BA1 M3 M3 BA2 BA2 A1 A1 C23 T31 J7 CK VDDQ_1 VDDQ_2 A8 J7 CK VDDQ_1 VDDQ_2 A8 M0_DDR_DQ0 M1_DDR_DQ0 K7 C1 K7 C1 AVDD_DDR 1K R433 IO[47]/A-DQ[0][A-DQL0]/A-DQ[0] IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] K9 CK VDDQ_3 C9 K9 CK VDDQ_3 C9 AVDD_DDR B22 P30 CKE VDDQ_4 VDDQ_5 D2 CKE VDDQ_4 VDDQ_5 D2 M0_DDR_DQ1 IO[31]/A-DQ[1][A-DQL1]/A-DQ[1] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] M1_DDR_DQ1 L2 E9 L2 E9 +1.5V_Bypass Cap CS VDDQ_6 CS VDDQ_6 K1 F1 K1 F1 OPT 1K R422 +1.5V_Bypass Cap ODT VDDQ_7 ODT VDDQ_7 B24 T30 J3 K3 RAS VDDQ_8 H2 H9 J3 K3 RAS VDDQ_8 H2 H9 M1_1_DDR_VREFDQ M0_DDR_DQ2 IO[48]/A-DQ[2][A-DQL2]/A-DQ[2] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] M1_DDR_DQ2 L3 CAS WE VDDQ_9 L3 CAS WE VDDQ_9 C21 P31 NC_1 J1 NC_1 J1 M1_DDR_VREFDQ M0_DDR_DQ3 B25 IO[29]/A-DQ[3][A-DQL3]/A-DQ[3] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3] U30 M1_DDR_DQ3 Close to DDR Power Pin T2 F3 RESET NC_2 NC_3 NC_4 J9 L1 L9 T7 T2 F3 RESET NC_2 NC_3 NC_4 J9 L1 L9 Close to DDR Power Pin R414 1K 1% DQSL NC_6 DQSL R408 1K 1% M0_DDR_DQ4 IO[50]/A-DQ[4][A-DQL4]/A-DQ[6] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] M1_DDR_DQ4 G3 DQSL G3 DQSL M1_DDR_RESET_N C20 N31 C7 B7 DQSU VSS_1 A9 B3 C7