Internal Use Only
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LED TV
SERVICE MANUAL
CHASSIS : LD52V
MODEL : 65UF95** 65UF95**-Z*
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL68679901 (1412-REV00) Printed in Korea
CONTENTS
CONTENTS ............................................................................................... 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 15
BLOCK DIAGRAM................................................................................... 22
EXPLODED VIEW ................................................................................... 36
SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX
TROUBLE SHOOTING GUIDE ................................................. APPENDIX
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method
This specification is applied to the LED TV used LD52V 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC specification
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Model General Specification
No. Item Specification Remarks
DTV & Analog (Total 37 countries)
DTV (MPEG2/4, DVB-T) : 26 countrie
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bul-
garia, France, Spain, Belgium, Luxemburg, Greece, Czech, Turkey,
Morocco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Ro-
mania, Albania, Bosnia, Slovakia, Belarus
DTV (MPEG2/4, DVB-T2) :11 countries
UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kaza-
khstan, Russia, Italy, Croatia, Serbia
DTV (MPEG2/4, DVB-C) : 37 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bul-
garia, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
EU(PAL Market-36Countries)/CIS
1 Market Czech, Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania,
+ Morocco(Africa)
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Bela-
rus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan
Supported satellite : 35 satellites
ABS1 75.0E , AMOS 4.0W , ASIASAT3S 105.5E , ASTRA 19.2E
, ASTRA 23.5E , ASTRA 28.2E , ASTRA 4.8E, ATLANTIC BIRD2
8.0W , ATLANTIC BIRD3 5.0W , BADR 26.0E , DIRECTV-1R 56.0E
, EUROBIRD 9A 9.0E , EUROBIRD3 33.0E , EUTELSAT 36 A/B
36.0E ,EUTELSAT W2A 10.0E , EUTELSAT W3A 7.0E , EUTELSA-
T7WA 7.3WEUTELSAT 16.0E , EXPRESS AM1 40.0E , EXPRESS
AM3 140.0E , EXPRESS AM33 96.5E , HELLASSAT 39.0E , HIS-
PASAT 1CDE 30.0WHOTBIRD 13.0E , INTELSAT10&7 68.5E ,
INTELSAT15 85.2E , INTELSAT1R 50.0W, INTELSAT903 33.5W ,
INTELSAT904 60.0E, NILESAT 7.0W , NSS12 57.0E , THOR 0.8W ,
TURKSAT 42.0E ,YAMAL201 90.0E , OTHER
(1) Digital TV
- DVB-T/T2
- DVB-C
2 Broadcasting system - DVB-S/S2
(2) Analogue TV
- PAL/SECAM B/G/I/D/K
- SECAM L/L’
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
(1) Digital TV
- VHF, UHF
- C-Band, Ku-Band
(2) Analogue TV
3 Program coverage
-VHF : E2 to E12
-UHF : E21 to E69
-CATV : S1 to S20
-HYPER : S21 to S47
► DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
► DVB-T2 (Model : *L*V*-Z* (T2 only Model))
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
4 Receiving system Digital : COFDM, QAM
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
► DVB-C
- Symbolrate : 4.0 Msymbols/s to 7.2 Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate :
DVB-S2 (8PSK / QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2 ~ 45 Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
Scart jack is Full scart and support ATV/DTV-OUT
5 Scart (1EA) PAL, SECAM (not support DTV Auto AV)
System : PAL, SECAM, PAL60
4 System : PAL, SECAM, NTSC4.43, PAL60
6 Video Input RCA (1EA) PAL, SECAM, NTSC4.43
Hybrid Type
Antenna, AV1, AV2, Component, HDMI1,
7 Head phone out HDMI2, HDMI3, HDMI4, USB1, USB2,
USB3
Y/Cb/Cr
8 Component Input (1EA)
Y/Pb/Pr
HDMI1-DTV
HDMI2-DTV
9 HDMI Input (4EA)
HDMI3-DTV
HDMI4-DTV
DVI Audio
10 Audio Input (3EA) Component/AV2 L/R Input
AV1
11 SPDIF out (1EA) SPDIF out
12 USB (3EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD
13 Ethernet Connect (1EA) Ethernet Connect
14 PCMCIA Card slot (1EA) PCMCIA slot
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. External Input Format
5.1. Component (Y, PB, PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1. 720*480i 15.73 59.94 13.500 SDTV, DVD 480I(525I)
2 720*480i 15.73 60.00 13.514 SDTV, DVD 480I(525I)
3. 720*576i 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz
4 720*480p 31.47 59.94 27.000 SDTV 480P
5 720*480p 31.50 60.00 27.027 SDTV 480P
6 720*576p 31.25 50.00 27.000 SDTV 576P 50Hz
7 1280*720 44.96 59.94 74.176 HDTV 720P
8 1280*720 45.00 60.00 74.250 HDTV 720P
9 1280*720 45.00 50.00 74.250 HDTV 720P 50Hz
10 1920*1080 28.125 50.00 74.250 HDTV 1080I 50Hz,
11 1920*1080 33.72 59.94 74.176 HDTV 1080I
12 1920*1080 33.75 60.00 74.25 HDTV 1080I
13 1920*1080 56.25 50 148.5 HDTV 1080P
14 1920*1080 67.5 60.00 148.5 HDTV 1080P
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
5.2. HDMI(PC/DTV)
(1) DTV mode
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*480 31.469 59.94 25.125 SDTV 480P
2 640*480 31.5 60.00 25.125 SDTV 480P
3 720*480 15.73 59.94 13.500 SDTV, DVD 480I(525I)
4 720*480 15.75 60.00 13.514 SDTV, DVD 480I(525I) Spec. out but display
5 720*576 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz
6 720*480 31.47 59.94 27 SDTV 480P
7 720*480 31.5 60.00 27.027 SDTV 480P
8 720*576 31.25 50.00 27 SDTV 576P
9 1280*720 44.96 59.94 74.176 HDTV 720P
10 1280*720 45 60.00 74.25 HDTV 720P
11 1280*720 37.5 50.00 74.25 HDTV 720P
12 1920*1080 28.125 50.00 74.25 HDTV 1080I
13 1920*1080 33.72 59.94 74.176 HDTV 1080I
14 1920*1080 33.75 60.00 74.25 HDTV 1080I
15 1920*1080 26.97 23.976 63.296 HDTV 1080P
16 1920*1080 27.00 24.000 63.36 HDTV 1080P
17 1920*1080 33.71 29.97 79.120 HDTV 1080P
18 1920*1080 33.75 30.00 79.20 HDTV 1080P
19 1920*1080 56.25 50.00 148.5 HDTV 1080P
20 1920*1080 67.432 59.94 148.350 HDTV 1080P
21 1920*1080 67.5 60.00 148.50 HDTV 1080P
22 3840*2160 53.95 23.98 296.703 UDTV 2160P
23 3840*2160 54 24.00 297.00 UDTV 2160P
24 3840*2160 56.25 25.00 297.00 UDTV 2160P
25 3840*2160 61.43 29.97 296.703 UDTV 2160P
26 3840*2160 67.5 30.00 297.00 UDTV 2160P
When HDMI1,2
27 3840*2160 112.5 50.00 594 UDTV 2160P
UHD DEEP COLOUR ON
When HDMI1,2
28 3840*2160 135 59.94 593.407 UDTV 2160P
UHD DEEP COLOUR ON
29 3840*2160 135 60.00 594 UDTV 2160P
30 4096*2160 53.95 23.98 296.703 UDTV 2160P
31 4096*2160 54 24.00 297 UDTV 2160P
32 4096*2160 56.25 25.00 297 UDTV 2160P
33 4096*2160 61.43 29.97 296.703 UDTV 2160P
34 4096*2160 67.5 30.00 297 UDTV 2160P
When HDMI1,2
35 4096*2160 112.5 50.00 594 UDTV 2160P
UHD DEEP COLOUR ON
When HDMI1,2
36 4096*2160 135 59.94 593.407 UDTV 2160P
UHD DEEP COLOUR ON
When HDMI1,2
37 4096*2160 135 60.00 594 UDTV 2160P
UHD DEEP COLOUR ON
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
(2) PC mode
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*350 31.468 70.09 25.17 EGA
2 720*400 31.469 70.08 28.32 DOS
3 640*480 31.469 59.94 25.17 VESA(VGA)
4 800*600 37.879 60.31 40 VESA(SVGA)
5 1024*768 48.363 60.00 65 VESA(XGA)
6 1360*768 47.712 60.015 84.75 VESA(WXGA)
7 1152*864 54.348 60.053 80 VESA
8 1280*1024 63.981 60.020 109.00 SXGA Support to HDMI-PC
9 1920*1080 67.5 60 158.40 WUXGA(Reduced Blanking)
10 3840*2160 54 24.00 297.00 UDTV 2160P
11 3840*2160 56.25 25.00 297.00 UDTV 2160P
12 3840*2160 67.5 30.00 297.00 UDTV 2160P
13 4096*2160 53.95 23.97 296.703 UDTV 2160P
14 4096*2160 54 24 297 UDTV 2160P
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
6. 3D Mode
6.1. RF Input
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 1280*720 37.500 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom
2 1920*1080 28.125 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom
6.2. HDMI Input
(1) HDMI 1.4/2.0(3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode
1 720*480 31.5 60 27.03 SDTV 480P
2 720*576 31.25 50 27 SDTV 576P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential, Row Inter-
45.00 60.00 74.25 HDTV 720P leaving, Column Interleaving
3 1280*720
37.500 50 74.25 HDTV 720P
33.75 60.00 74.25 HDTV 1080I
2D to 3D, Side by Side(Half), Top & Bottom
28.125 50.00 74.25 HDTV 1080I
27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
4 1920*1080 28.12 25 74.25 HDTV 1080P Checker Board, Row Interleaving, Column
33.75 30.00 74.25 HDTV 1080P Interleaving
67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential, Row
56.250 50 148.5 HDTV 1080P Interleaving, Column Interleaving
53.95 23.976 297.00
54 24.00 296.703
5 3840*2160 56.25 25.00 297.00 HDTV 2160P 2D to 3D, Top & Bottom(half), Side by Side(half),
61.43 29.970 297.00
67.5 30.00 296.703
6 112.5 50 HDTV 2160P 2D to 3D, Top & Bottom(half), Side by Side(half),
3840*2160
594 When HDMI1,2
7 4096*2160 135 60 HDTV 2160P UHD DEEP COLOUR ON
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
(2) HDMI 1.4b (3D Supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed
Top-and-Bottom Secondary(SDTV 480P)
31.469 / 31.5 59.94/ 60 25.125/25.2 1
Side-by-side(half) Secondary(SDTV 480P)
1 640*480 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)
Frame packing Secondary(SDTV 480P)
62.938/63 59.94/ 60 50.35/50.4 1
Line alternative (SDTV 480P)
Top-and-Bottom Secondary(SDTV 480P)
31.469 / 31.5 59.94 / 60 27.00/27.03 2,3
Side-by-side(half) Secondary(SDTV 480P)
2 720*480 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)
Frame packing Secondary(SDTV 480P)
62.938/63 59.94 / 60 54/54.06 2,3
Line alternative (SDTV 480P)
Top-and-Bottom Secondary(SDTV 576P)
31.25 50 27 17,18
Side-by-side(half) Secondary(SDTV 576P)
31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)
Frame packing Secondary(SDTV 576P)
62.5 50 54 17,18
3 720*576 Line alternative (SDTV 576P)
Frame packing Secondary(SDTV 576I)
Field alternative (SDTV 576I
15.625 50 27 21 Side-by-side(Full) (SDTV 576I
Top-and-Bottom Secondary(SDTV 576I)
Side-by-side(half) Secondary(SDTV 576I)
Top-and-Bottom Primary(HDTV 720P)
37.500 50 74.25 19
Side-by-side(half) Primary(HDTV 720P)
37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)
Frame packing Primary(HDTV 720P)
44.96 / 45 59.94 / 60 74.17/74.25 4
Line alternative (HDTV 720P)
4 1280*720
44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)
Top-and-Bottom Primary(HDTV 720P)
75 50 148.5 19
Side-by-side(half) Primary(HDTV 720P)
Frame packing Primary(HDTV 720P)
89.91/90 59.94 / 60 148.35/148.5 4
Line alternative (HDTV 720P)
Frame packing Secondary(HDTV 1080I)
28.125 50.00 74.25 20
Line alternative Primary(HDTV 1080I)
28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)
Top-and-Bottom Secondary(HDTV 1080I)
33.72 / 33.75 59.94 / 60 74.17/74.25 5
Side-by-side(half) Primary(HDTV 1080I)
33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)
Frame packing Primary(HDTV 1080I)
56.25 50.00 148.5 20
Field alternative (HDTV 1080I)
Frame packing Primary(HDTV 1080I)
67.432/67.50 59.94 / 60 148.35/148.5 5
Field alternative (HDTV 1080I)
Top-and-Bottom Primary(HDTV 1080P)
26.97 / 27 23.97 / 24 74.17/74.25 32
Side-by-side(half) Primary(HDTV 1080P)
26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Secondary(HDTV 1080P)
28.125 25 74.25 33
5 1920*1080 Side-by-side(half) Secondary(HDTV 1080P)
28.125 25 148.5 33 Side-by-side(Full) (HDTV 1080P)
33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Side-by-side(Full) (HDTV 1080P)
Frame packing Primary(HDTV 1080P)
33.716 / 33.75 29.976 / 30.00 148.35/148.5 34
Line alternative (HDTV 1080P)
Frame packing Secondary(HDTV 1080P)
43.94/54 23.97 / 24 148.35/148.5 32
Line alternative (HDTV 1080P)
Frame packing Primary(HDTV 1080P)
56.25 25 148.5 33
Line alternative (HDTV 1080P)
Frame packing Primary(HDTV 1080P)
67.432 / 67.5 29.976 / 30.00 148.35/148.5 34
Line alternative (HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
56.250 50 148.5 31
Side-by-side(half) Secondary(HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
67.43 / 67.5 59.94 / 60 148.35/148.50 16
Side-by-side(half) Secondary(HDTV 1080P)
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
(3) HDMI-PC Input (3D) (3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1024*768 48.36 60 65 HDTV 768P 2D to 3D, Side by Side(half), Top & Bottom
2 1360*768 47.71 60 85.5 HDTV 768P 2D to 3D, Side by Side(half), Top & Bottom
2D to 3D, Side by Side(half), Top & Bottom,
3 1920*1080 67.500 60 148.50 HDTV 1080P Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving
54 24.00 297.00
2D to 3D, Top & Bottom(half), Side by
4 3840*2160 56.25 25.00 297.00 HDTV 2160P
Side(half),
67.5 30.00 297.00
2D to 3D,
5 4096*2160 54 24 297.00 HDTV 2160P
Top & Bottom(half), Side by Side(half),
640*350
720*400
6 Others - - - 640*480 2D to 3D, Side by Side(half), Top & Bottom
800*600
1152*864
(4) Component Input (3D) (3D Supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 37.5 50 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom
2 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom
3 1280*720 44.96 59.94 74.176 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom
4 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom
5 1920*1080 33.72 59.94 74.176 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom
6 1920*1080 28.12 50 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom
7 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
8 1920*1080 67.432 59.94 148.352 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
9 1920*1080 27.000 24.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
10 1920*1080 28.12 25 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
11 1920*1080 56.25 50 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
12 1920*1080 26.97 23.976 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
13 1920*1080 33.75 30.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
14 1920*1080 33.71 29.97 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
6.3. USB - Movie (3D) (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 704x480 - - - 2D to 3D
Over 704x480
2 Under 1080P - - - 2D to 3D, Side by Side(Half), Top & Bottom
interlaced
2D to 3D, Side by Side(Half), Top & Bottom, Checker
Over 704x480 - 50 / 60 - Board, Row Interleaving, Column Interleaving, Frame
3 Under 1080P Sequential
progressive 2D to 3D, Side by Side(Half), Top & Bottom, Checker
- others -
Board, Row Interleaving, Column Interleaving
4 Over 2160P - 24/25/30/50/60 - 2D to 3D, Side by Side(Half), Top & Bottom
6.4. USB - Photo (3D) (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 320x240 - - - 2D to 3D
2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom
6.5. USB(3D) (3D supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1080p 33.75 30 74.25 Side by Side(Half), Top & Bottom, Checker Board
2 2160p 67.5 30 297 MPO(Photo), JPS(Photo)
6.6. Miracast, Widi (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1024*768p - 30/60 -
2 1280*720p - 30/60 - 2D to 3D, Side by Side(Half), Top & Bottom
3 1920*1080p - 30/60 -
4 Others - - - 2D to 3D
■ Remark: 3D Input mode
Single Frame Line Column
No. Side by Side Top & Bottom Checker board Frame Packing
Sequential Interleaving Interleaving
L R LLLLL R
1 L
R
L
Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 3.2. LAN Inspection
This specification sheet is applied to all of the LED TV with 3.2.1. Equipment & Condition
LD52V chassis. ▪ Each other connection to LAN Port of IP Hub and Jig
2. Designation
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
3.2.2. LAN inspection solution
▪ LAN Port connection with PCB
humidity if there is no specific designation.
▪ Setting automatic IP
(4) The input voltage of the receiver must keep AC 100-240
V~, 50/60 Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
▪ If you want manual connection, enter Network connection at
hours.
MENU Mode of TV. Press Start connection key, then
Network will be connected.
In case of keeping module is in the circumstance of below
-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3. Automatic Adjustment
3.1. MAC address D/L, CI+ key D/L, Widevine
key D/L, ESN D/L, HDCP2.0 D/L 3.2.3. WIDEVINE key Inspection
Connect: USB port - Confirm key input data at the "IN START" MENU Mode.
Communication Prot connection
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ Check the test process: DETECT → MAC → CI → Widevine
→ ESN → HDCP20
▪ Play: Press Enter key
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)
Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
3.3. LAN PORT INSPECTION(PING TEST) 3.5. CI+ Key checking method
Connect SET → LAN port == PC → LAN Port - Check the Section 3.1
Check whether the key was downloaded or not at ‘In Start’
SET PC menu. (Refer to below).
3.3.1. Equipment setting
(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program. => Check the Download to CI+ Key value in LGset.
*IP Number : 12.12.2.2 3.5.1. Check the method of CI+ Key value
(1) Check the method on Instart menu
3.3.2. LAN PORT inspection(PING TEST) (2) Check the method of RS232C Command
(1) Play the LAN Port Test Program. 1) Into the main ass’y mode(RS232: aa 00 00)
(2) Connect each other LAN Port Jack. CMD 1 CMD 2 Data 0
(3) Play Test (F9) button and confirm OK Message. A A 0 0
(4) Remove LAN cable.
2) Check the key download for transmitted command
(RS232: ci 00 10)
CMD 1 CMD 2 Data 0
C I 1 0
3) Result value
- Normally status for download : OKx
- Abnormally status for download : NGx
3.5.2. Check the method of CI+ key value(RS232)
1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1 CMD 2 Data 0
3.4. Model name & Serial number Download A A 0 0
3.4.1. Model name & Serial number D/L 2) Check the mothed of CI+ key by command
▪ Press "P-ONLY" key of service remote control.
(RS232: ci 00 20)
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
CMD 1 CMD 2 Data 0
▪ Write Serial number by use USB port. C I 2 0
▪ Must check the serial number at Instart menu.
3) Result value
i 01 OK 1d1852d21c1ed5dcx
3.4.2. Method & notice
CI+ Key Value
(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced 3.6. WIFI MAC ADDRESS CHECK
in production line, because serial number D/L is mandatory (1) Using RS232 Command
by D-book 4.0. H-freq(kHz) V-freq.(Hz)
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always) (2) Check the menu on in-start
It is impossible to download by bar code scan, so It need
Manual download.
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LB650V-ZA) or Serial
number like photo.
4) Check the model name Instart menu. → Factory name
displayed. (ex 47LB650V-ZA)
5) C heck the Diagnostics.(DTV country only) → Buyer
model displayed. (ex 47LB650V-ZA)
Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
4. Manual Adjustment (1) EDID
# HDMI 1(C/S: 0xE6, 0XF4)
4.1. ADC adjustment 1) HDMI Deep Color OFF (C/S: 0xE6, 0XF4)
(1) Remove Component and SCART Input Signal. 0 1 2 3 4 5 6 7 8 9 A B C D E F
(2) Press Adj. key on the Adjustment remote control, then 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
select “9.ADC Calibration”. 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
(3) Change ADC Type to Internal 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
(4) Move curser on the Start. 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
(5) Press OK. 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
4.2. EDID(The
Extended Display Identification 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
Data)/DDC(Display Data Channel) download 0 1 2 3 4 5 6 7 8 9 A B C D E F
4.2.1. Overview 0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21
It is a VESA regulation. A PC or a MNT will display an optimal 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
resolution through information sharing without any necessity 20 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02
of user input. It is a realization of "Plug and Play". 30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
40 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C
50 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
4.2.2. Equipment 60 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
- Since embedded EDID data is used, EDID download JIG, 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F4
HDMI cable and D-sub cable are not need.
- Adjustment remote control 2) HDMI Deep Color ON (C/S: 0xA0, 0x9E)
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.2.3. Download method 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
(1) Press "ADJ" key on the Adjustment remote control, then 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
select "12.EDID D/L", By pressing "Enter" key, enter EDID
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
D/L menu.
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
For HDMI EDID 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
DVI-D to HDMI or HDMI to HDMI 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 02 03 55 F1 58 10 9F 04 13 05 14 03 02 12 20 21
10 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
20 C0 15 07 50 09 57 07 7C 03 0C 00 10 00 B8 3C 20
30 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10
(2) S elect "Start" button by pressing "Enter" key, HDMI1/ 40 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00
HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG. 50 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36
60 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E
4.2.4. EDID DATA 70 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 9E
▪ Reference
- HDMI1 ~ HDMI3 # HDMI2
- In the data of EDID, bellows may be different by Input mode. 1) HDMI Deep Color OFF (C/S: 0xE6, 0XE4)
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
0x07 ⓓ 01 ⓔ1
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ 0 1 2 3 4 5 6 7 8 9 A B C D E F
0x02 ⓕ 0 02 03 46 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 20 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D
30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
40 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2
50 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
ⓐ Product ID 60 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
ⓑ Serial No: Controlled on production line. 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E4
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2013’ → ‘17’
ⓓ Model Name(Hex): LGTV
ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)
Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
2) HDMI Deep Color ON (C/S: 0xA0, 0x8E) 4.3. White Balance Adjustment
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.3.1. Overview
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
▪ W/B adj. Objective & How-it-works
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
(1) Objective: To reduce each Panel's W/B deviation
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 (2) How-it-works : When R/G/B gain in the OSD is at 192, it
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 means the panel is at its Full Dynamic Range. In order to
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A prevent saturation of Full Dynamic range and data, one
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC of R/G/B is fixed at 192, and the other two is lowered to
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0 find the desired value.
0 1 2 3 4 5 6 7 8 9 A B C D E F
(3) Adjustment condition : normal temperature
0 02 03 55 F1 58 10 9F 04 13 05 14 03 02 12 20 21 1) Surrounding Temperature : 25 °C ± 5 °C
10 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06 2) Warm-up time: About 5 Min
20 C0 15 07 50 09 57 07 7C 03 0C 00 20 00 B8 3C 20 3) Surrounding Humidity : 20 % ~ 80 %
30 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10
40 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00 4.3.2. Equipment
50 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36
(1) Color Analyzer: CA-210 (LED Module : CH 14)
60 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E
(2) Adjustment Computer(During auto adj., RS-232C protocol
70 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 8E
is needed)
# HDMI3 (C/S: 0xE6, 0XD4) (3) Adjustment Remote control
0 1 2 3 4 5 6 7 8 9 A B C D E F
(4) Video Signal Generator MSPG-925F 720p/216-Gray
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 (Model: 204, Pattern: 49)
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 → Only when internal pattern is not available
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 • Color Analyzer Matrix should be calibrated using CS-100.
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 4.3.3. Equipment connection MAP
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC Co lo r Analyzer
RS -232C
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 Probe
Co m p ut er
0 1 2 3 4 5 6 7 8 9 A B C D E F RS -232C
RS -232C
0 02 03 46 F1 54 10 9F 04 13 05 14 03 02 12 20 21 Pat t ern Generat o r
10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 Signal Source
20 09 57 07 7C 03 0C 00 40 00 B8 3C 20 C0 8E 01 02 * If TV internal pattern is used, not needed
30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
40 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C
50 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 4.3.4. Adj. Command (Protocol)
60 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4
- LEN: Number of Data Byte to be sent
# HDMI4 (C/S: 0xE6, 0XC4) - CMD: Command
0 1 2 3 4 5 6 7 8 9 A B C D E F - VAL: FOS Data value
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 - CS: Checksum of sent data
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 - A: Acknowledge
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 ▪ RS-232C Command used during auto-adjustment.
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
RS-232C COMMAND
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC Explanation
[CMD ID DATA]
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
wb 00 00 Begin White Balance adjustment
0 1 2 3 4 5 6 7 8 9 A B C D E F wb 00 10 Gain adjustment(internal white pattern)
0 02 03 46 F1 54 10 9F 04 13 05 14 03 02 12 20 21
wb 00 1f Gain adjustment completed
10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
20 09 57 07 7C 03 0C 00 40 00 B8 3C 20 C0 8E 01 02 wb 00 20 Offset adjustment(internal white pattern)
30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 wb 00 2f Offset adjustment completed
40 E4 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C End White Balance adjustment
wb 00 ff
50 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 (internal pattern disappears )
60 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C4 Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
* Checksum(HDMI 1/2/3/4) ja 00 ff -> Adj. data
FFh (Checksum) FFh (Checksum) jb 00 c0
Input
Deep Color : OFF Deep Color : ON ...
HDMI1 E6 F4 A0 9E ...
HDMI2 E6 E4 A0 8E wb 00 1f -> Gain adj. completed
HDMI3 E6 D4 N/A N/A *(wb 00 20(Start), wb 00 2f(end)) -> Off-set adj.
HDMI4 E6 C4 N/A N/A wb 00 ff -> End white balance auto-adj.
Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
▪ Adj. Map ▪ Adjustment condition and cautionary items
Command Data Range 1) Lighting condition in surrounding area
Default
Adj. item (lower case ASCII) (Hex.)
(Decimal)
Surrounding lighting should be lower 10 lux. Try to
CMD1 CMD2 MIN MAX isolate adj. area into dark surrounding.
R Gain j g 00 C0 2) Probe location
G Gain j h 00 C0 : Color Analyzer(CA-210) probe should be within 10 cm
B Gain j i 00 C0 and perpendicular of the module surface (80° ~ 100°)
Cool
R Cut 3) Aging time
G Cut - After Aging Start, Keep the Power ON status during 5
B Cut Minutes.
R Gain j a 00 C0 - In case of LCD, Back-light on should be checked
G Gain j b 00 C0
using no signal or Full-white pattern.
B Gain j c 00 C0
Medium
R Cut 4.3.6.
R eference (White balance adjusmtment
G Cut coordinate and color temperature)
B Cut ▪ Luminance : 206 Gray
R Gain j d 00 C0 ▪ Standard color coordinate and temperature using CS-1000
G Gain j e 00 C0 (over 26 inch)
Warm B Gain j f 00 C0 Coordinate
Mode Temp ∆uv
R Cut x y
G Cut Cool 0.271 0.270 13000 K 0.0000
Medium 0.286 0.289 9300 K 0.0000
Warm 0.313 0.329 6500 K 0.0000
4.3.5. Adj. method
(1) Auto adj. method ▪ Standard color coordinate and temperature using CA-210(CH 14)
1) Set TV in adj. mode using POWER ON key. Coordinate
2) Zero calibrate probe then place it on the center of the Mode Temp ∆uv
Display. x y
3) Connect Cable.(RS-232C to USB) Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000
4) Select mode in adj. Program and begin adj. Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000
5) When adj. is complete (OK Sign), check adj. status pre
Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
4.3.7. EDGE & IOL LED White balance table
▪ W/B Adj. must begin as start command “wb 00 00”, and ▪ EDGE LED module change color coordinate because of
finish as end command “wb 00 ff”, and Adj. offset if need. aging time.
▪ Apply under the color coordinate table, for compensated
(2) Manual adjustment. method aging time.
1) Set TV in Adj. mode using POWER ON. ▪ (Normal line) Edge LED White balance table
2) Zero Calibrate the probe of Color Analyzer, then place it
Aging Cool Medium Warm
on the center of LCD module within 10 cm of the surface.
time x y x y x y
3) Press ADJ key → EZ adjust using adj. R/C → 7. White-
(Min) 271 270 286 289 313 329
Balance then press the cursor to the right(key ►).
(When right key(►) is pressed 216 Gray internal pattern 1 0-2 282 289 297 308 324 348
will be displayed) 2 3-5 281 287 296 306 323 346
4) One of R Gain / G Gain / B Gain should be fixed at 192, 3 6-9 279 284 294 303 321 343
and the rest will be lowered to meet the desired value. 4 10-19 277 280 292 299 319 339
5) Adjustment is performed in COOL, MEDIUM, WARM 3 5 20-35 275 277 290 296 317 336
modes of color temperature.
6 36-49 274 274 289 293 316 333
7 50-79 273 272 288 291 315 331
** G-fix adjustment
Adjust modes (Cool), Fix the G gain to 172 (default data) 8 80-119 272 271 287 290 314 330
and change the others (G/B Gain). 9 Over 120 271 270 286 289 313 329
Adjust two modes(Medium / Warm), Fix the one of R/G/B
gain to 192 (default data) and decrease the others.
▪ If internal pattern is not available, use RF input. In EZ Adj.
menu 7.White Balance, you can select one of 2 Test-
pattern: ON, OFF. Default is inner(ON). By selecting OFF,
you can adjust using RF signal in 216 Gray pattern.
Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
4.4. Local Dimming Function Check 4.7. Option selection per country
(1) Turn on TV. (Power only mode) 4.7.1. Overview
(2) Press TILT key on the Adj.Remote. - Option selection is only done for models in AJ/JA/IL
(3) Check that Backlight move from left to right as below picture.
(4) Press “exit” Key to stop Local dimming check. 4.7.2.Method
(1) Press "ADJ" key on the Adjustment remote control, then
select Country Group Menu.
(2) Depending on destination, select Country Group Code or
Country Group then on the lower Country option, select
US, CA, MX. Selection is done using +, - or ►◄ KEY.
4.8. HDMI ARC Function Inspection
(1) Test equipment
4.5. Magic Motion Remote control test - Optic Receiver Speaker
- E quipment : RF Remote control for test, IR-KEY-Code - MSHG-600 (SW: 1220 ↑)
Remote control for test - HDMI Cable (for 1.4 version)
- You must confirm the battery power of RF-Remote control
before test(recommend that change the battery per every lot) (2) Test method
- Sequence (test) 1) Insert the HDMI Cable to the HDMI ARC port from the
1) If you select the ‘start key(OK)’ on the Adjustment remote master equipment. (HDMI2)
control, you can pairing with the TV SET. 2) Check the sound from the TV Set.
2) You can check the cursor on the TV Screen, when select
the "OK" key on the Adjustment remote control.
3) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the Adjustment remote control.
4.6. 3D function test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below. 3) Check the Sound from the Speaker or using AV & Optic
TEST program (It’s connected to MSHG-600)
4.9. Tool Option selection
- Method : Press "ADJ" key on the Adjustment remote control,
then select Tool option.
Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7 Tool 8
65UF950V-ZA (EU) 34473 12819 59050 19737 59812 3931 52111 0
65UF950V-ZA (CIS) 34473 12819 59018 19737 59812 3931 52111 0
(2) When 3D OSD appear automatically, then select green key.
4.10. Ship-out mode check (In-stop)
- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
(3) Don't wear a 3D Glasses, Check the picture like below.
Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only
Only for training and service purposes
5. GND and Internal Pressure check 7. USB S/W Download(Service only)
5.1. Method (1) Put the USB Stick to the USB socket.
(1) GND & Internal Pressure auto-check preparation (2) Go to General menu then enter to About This TV.
- Check that Power Cord is fully inserted to the SET. (If
loose, re-insert)
(2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX.) (3) Enter the USB EXPERT MODE.
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
5.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND (4) Updating is starting.
- Internal Pressure TEST = POWER CORD GND & LIVE & (5) Updating completed, the TV will restart automatically
NEUTRAL (6) If your TV is turned on, check your updated version and
▪ LEAKAGE CURRENT: At 0.5 mArms Tool option. (explain the Tool option, next stage)
* If downloading version is more new than your TV have,
6. Audio TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
No. Item Min Typ Max Unit
have a DTV/ATV test on production line.
Audio practical max 10 12 W EQ Off
1 Output, L/R (Distor- AVL Off
tion=10% max Output) 8.10 10.8 Vrms Clear Voice Off * After downloading, have to adjust Tool Option again.
EQ On (1) Push "IN-START" key in service remote control.
Speaker (2) Select "Tool Option 1" and push "OK" key.
2 10 12 W AVL On
(8 Ω Impedance)
Clear Voice On (3) Punch in the number. (Each model has their number)
Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
1. External
DIF(P/N)
AUDA/D
CVBS SPDIF
Tuner OPTIC
SIF
BB_TP_DATA
H/P Audio L/R
H/P AMP H/P
LNB LNB CVBS
2CH - 1AMP Model
Only for training and service purposes
H15A H15D (UD85, UF75, UF71)
SC_CVBS, RGB, Audio L/R
LG1210A DAC_DATA LG1210D I2S Audio AMP
SCART SPK
DTV/MNT_LR/V_OUT (Front 2ch)
AV1_CVBS AAD_DATA I2S Audio AMP
AV1 COMP1/AV1/DVI_ L/R (Woofer 2ch) SPK
HSR_P/M
Comp1 Y,Pb,Pr I2S Audio AMP
COMP1
(Tweeter 2ch) SPK
LG Electronics. Inc. All rights reserved.
HDMI_CEC
Logo Light 4.2CH - 3AMP Model (UF95)
IR/Joy key
WOL / WOW CI
CI Slot
RMII
LAN PHY
RS-232C
USB 2.0 (WIFI11ac & BT) DDR3
Motion-R & USB_WI-Fi 16x2
- 22 -
USB 3.0
USB1(USB3.0)
USB 2.0 16x4
USB2(USB2.0) 4Gb x 6 (1866)
USB 2.0
USB3(USB2.0)
USB 2.0
USB_CAM
HDMI1.4 &ARC
HDMI1.4 & MHL3.0
BLOCK DIAGRAM
MHL 3.0
HDMI1~4 HDMI2.0
HDMI2.0 16
eMMC
Vx1 8Lane / VIDEO Vx1 8Lane
Vx1 4Lane / OSD URSA9 Vx1 8Lane
16x4
DDR3
1Gb x 4 (1866)
LGE Internal Use Only
2. Internal
Copyright © LG Electronics. Inc. All rights reserved. - 23 - LGE Internal Use Only
Only for training and service purposes
3. H15 Data Path
Copyright © LG Electronics. Inc. All rights reserved. - 24 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
4. URSA9
SPI_CZ
SPI_DO
X-tal
SPI_CK 24MHz
SPI_DI XIN_URSA
Serial Panel
Flash(4MB)
URSA9 XO_URSA
Only for training and service purposes
LGE7410 3840x2160@120p
GPIO[25]
FLASH_WP_URSA
DDR3 16x4
[TXDBN0/P0~N7/P7_L] Vx1 8Lane 41P
1Gb x 4 (1866)
LG Electronics. Inc. All rights reserved.
[VBY1_RXM[0]~[7]
[C4TX_0N/P~7N/P] 4K@60p Vx1 8 Lane Video [VBY1_RXP[0]~[7]
[VBY1_RXM[8]~[11]
[C4TX_8N/P~11N/P] 1080p / 2160p Vx1 4 Lane OSD
[VBY1_RXP[8]~[11]
URSA9_CONNECT
[GPIO[3]] [GPIO[14]]
Vx1_LOCKn_O/V
[TX_LOCKN] [GPIO[16]/[17]]
[TXDAN0/P0~N7/P7_L] Vx1 8Lane 51P
- 25 -
I2CS_SDA/SCL [I2CS_SDA/SCL]
H15
(URSA Debug)
[VX1_LOCKN] LOCKn_IN/ HTPDn_IN
[VX1_HTDPN]
URSA_RESET_SOC MICOM H15 I2C_SCL1/SDA1
[RESET] (MICOM PORT #12)
BIT[2/1/0] UD_V x 1 Lane No.
UART2_RX GPIO[1]/[0] 0/0/0 4K@120P(16Lanes)
UART2_TX 0/0/1 4K@60P(8Lanes)
DIM5/GPIO[37]
DIM6/GPIO[38] URSA_BIT0/1/2
0/1/0 5K@120P(20Lanes)
DIM7/GPIO[39]
0/1/1 OLED ULTRA HD
1/0/0 FHD@120 (4Lane)
1/0/1 FHD@60 (4Lane)
1/1/0 Reserved
1/1/1 Reserved
LGE Internal Use Only
Copyright ©
D_DEMOD_CORE
5. Tuner
+3.3V_NORMAL
+3.3V_NORMAL
+2.5V_Normal
[+3.3V_LNA_TU] 1
[+3.3V_TUNER] 11
3.3K Ω
[+3.3V_DEMOD] 26
[+3.3V_1.2V_DEMOD] 28 33 Ω 7 [SCL]
[+2.5V_DEMOD] 38
LNB2
8 [SDA]
LNB_TX2 IC7000
[LNB_TX2] 52 10 [TONECTRL]
[LNB_OUT2] 47 LNB_OUT2 2 [LNB] A8303SESTR-TB
LNB_TX1
[LNB_TX1] 29 10 [TONECTRL]
Only for training and service purposes
LNB_OUT1 LNB1
[LNB_OUT1] 31 2 [LNB]
IC6900
[I2C_SCL4] 27 I2C_SCL4 7 [SCL]
33 Ω A8303SESTR-TB
[I2C_SDA4] 30 I2C_SDA4 8 [SDA]
+3.3V_NORMAL
33 Ω AW9 [SCL3]
TDJM-H3 3.3K Ω AV9 [SDA3] H15
[I2C_SCL6] 4 I2C_SCL6 BA42 [SCL5]
LG1210D
33 Ω
BA41 [SDA5]
LG Electronics. Inc. All rights reserved.
[I2C_SDA6] 5 I2C_SDA6
[FE_DEMOD1_TS_ERROR] 12 FE_DEMOD1_TS_ERROR AY37 [FE_TP_CLK]
[FE_DEMOD1_TS_CLK] 14 FE_DEMOD1_TS_CLK BB38 [FE_TP_SOP]
[FE_DEMOD1_TS_SYNC] 15 FE_DEMOD1_TS_SYNC BB37 [FE_TP_VAL]
[FE_DEMOD1_TS_VAL] 16 FE_DEMOD1_TS_VAL BA38 [FE_TP_ERROR]
FE_DEMOD1_TS_DATA [0-7]
FE_DEMOD1_TS_DATA[0-7] 17-24 BA37-AY38 [FE_DEMOD1_TS_DATA0-7]
- 26 -
FE_DEMOD2_TS_ERROR
[FE_DEMOD2_TS_ERROR] 62 BB36[STPI_ERR/GPIO44]
FE_DEMOD2_TS_SYNC
[FE_DEMOD2_TS_SYNC] 64 BA36[STPI_SOP/GPIO 46]
FE_DEMOD2_TS_CLK
[FE_DEMOD2_TS_CLK] 63 BB35 [STPI_CLK/GPIO 47]
FE_DEMOD2_TS_VAL
[FE_DEMOD2_TS_VAL] 65 BA35 [STPI_VAL/GPIO 45]
FE_DEMOD2_TS_DATA [0-7]
FE_DEMOD2_TS_DATA[0-7] 53-60 BA37-AY38 [FE_DEMOD1_TS_DATA0-7]
[FE_DEMOD3_TS_ERROR] 34 FE_DEMOD3_TS_ERROR BA33[STPI_ERR/GPIO55]
[FE_DEMOD3_TS_SYNC] 36 FE_DEMOD3_TS_SYNC BB32[STPI_SOP/GPIO 41]
[FE_DEMOD3_TS_CLK] 37 FE_DEMOD3_TS_CLK BA32 [STPI_CLK/GPIO 42]
[FE_DEMOD3_TS_VAL] 39 FE_DEMOD3_TS_VAL BB31 [STPI_VAL/GPIO 40]
FE_DEMOD3_TS_DATA
FE_DEMOD3_TS_DATA 40 BA31 [SPIO_DATA/GPIO54]
RESET_S_DEMOD AW36 [GPIO24]
[/TU_RESET1] 25
RESET_M_DEMOD AW37 [GPIO25]
[/TU_RESET2] 45,61
IF_P ADC_I_INP
[IF_P_TU] 6 V19 [UDMD_ADC_INP]
IF_N FILTER ADC_I_INN
[IF_N_TU] 7 V20 [UDMD_ADC_INN]
TUNER_SIF H14
[TU_SIF] 9 H20 [ADD_ADC_SIF]
TU_CVBS
[TU_CVBS_TU] 8 Y15 [CVBS_IN1] LG1210A
[IF_AGC_TU] 3 IF_AGC
J20[IFAGC]
LGE Internal Use Only
6. Video & Audio IN/OUT
Jack Side SOC Side
H15
(LG1210A)
CVBS 1
Phone JACK
AV1_CVBS_IN AV1_CVBS_IN_SOC
[CVBS_IN3]
COMP1/AV1/DVI_L/R_IN AUAD_L/R_CH2_IN
FULL [AUAD_L/R_CH2_IN]
SCART
(18P)
SC_CVBS_IN SC_CVBS_IN_SOC
[CVBS_IN2]
SC_R/G/B
/CVBS_IN_SOY
[PR1/Y1/PB1/SOY1_IN]
COMP1_PR_IN_SOC
COMP1_Y_IN_SOC
COMP1_PB_IN_SOC
COMP1_Y_IN_SOC_SOY
Component 1
Phone JACK
SC_L/R_IN AUAD_L/R_CH3_IN
[AUAD_L/R_CH3_IN]
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
COMP2_Y_IN_SOC_SOY
COMP1_Y/Pb/Pr COMP2_PR_IN_SOC
[PB2/Y2/SOY2/PR2_IN]
SPDIF OUT
SPDIF_OUT
[IEC958OUT]
H/P JACK
HP_L/ROUT
[AUDA_OUTL/R]
SPDIF_OUT_ARC
[HDMI_ARC]
Copyright © LG Electronics. Inc. All rights reserved. - 27 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
MICOM
7. Audio OUT
SCART
Mute
CTRL
[TR]
SCART_MUTE
[AUAD_L/R_CH1_IN]
SC_L/R_IN [AUAD_L/R_CH4_IN]
SCART_L/Rout_SOC AZ4580MTR DTV/MNT_L/R_OUT AUDIO L/R OUT
[AUAD_L/R_CH3_IN]
Only for training and service purposes
COMP1/AV1/DVI_L/R_IN pi filter
[AUAD_L/R_CH2_IN] OP AMP
[AUD_SCART_OUTL/R]
Main
AUD_SCK/LRCK AUD_SCK/LRCK LPF
[SCK]
[LRCK] NTP7515
LRCH LPF
[DACLRCH] LRCH
WOOFER [I2C_SDA1/SCL1] I2C_SDA1/SCL1
LG Electronics. Inc. All rights reserved.
LPF LPF
NTP7515 NTP7515
LPF I2C_SDA3/SCL3 [I2C_SDA3/SCL3] [DACSLRCH]
LRCH_TW LPF
AMP_RESET_N AMP_RESET_N Tweeter
[GPIO21]
H15
LG1210D
- 28 -
AMP_MUTE(Woofer_mute)
AMP_MUTE (Woofer_mute)
MICOM
SIDE_HP_MUTE
TU_SIF
TPA6138A2
[AAD_ADC_SIF] HP_L/ROUT_MAIN Headphone
[AUDA_OUTL] LPF H/P Jack
[HDMI_ARC] [IEC958OUT] AMP
HP_L/ROUT
Tuner
SPDIF_OUT
SPDIF_OUT_ARC
LGE Internal Use Only
Copyright ©
HDMI1.4b: 1, 2
8. HDMI2.0 Block
TMDS_1_Link
DDC_I2C_1
Only for training and service purposes
CEC_REMOTE SPDIF_OUT_ARC HDCP1.4
HDMI_HPD_1
TMDS_2_Link
DDC_I2C_2_MHL
MHL3.0 HDCP1.4
CEC_REMOTE MHL_DET
HDMI_HPD_2_MHL
IC
LG Electronics. Inc. All rights reserved.
OCP
(TPS2553) H15
LG1210D
HDMI2.0 : 3, 4
- 29 -
TMDS_3_Link
DDC_I2C_3
CEC_REMOTE HDMI2.0_ARC HDCP2.2
HDMI_HPD_3
TMDS_4_Link
DDC_I2C_4 HDCP2.2
CEC_REMOTE HDMI_HPD_4
MICOM
(R5F100GEAFB)
LGE Internal Use Only
Copyright ©
Only for training and service purposes
USB3_TX0P / 0M
[USB3_DP1 / DM1] USB3_RX0P / 0M
USB3_DP / DM
[USB3_TXP1/TXM1] USB1(3.0)
[USB3_RXP1/RXM1]
USB_DP1 / DM1
[USB2_DP0 / DM0] USB2
[USB2_DP1 / DM1] USB3
LG Electronics. Inc. All rights reserved.
USB_DP2 / DM2
9. USB / WIFI / M-REMOTE / UART
WIFI_DP / DM WOW/WOL_WAKE_UP
[USB3_DP3/ DM3] USB Wi-Fi / BT
MICOM
IC3000
- 30 -
H15 SOC_RX/TX
LG1210D
SOC_RX/TX RS232C
[UART0_RXD / TXD]
IC6801
SOC_RX/TX 2 Wafer
[UART2_RXD / TXD]
P4301
M_REMOTE_RX /TX
[UART1_RXD / TCD] Wifi / BT
M_REMOTE_RTS / CTS P4000
[UART1_RTS_N / CTS_N]
LGE Internal Use Only
Copyright ©
IC5600 I2C_SCL1
NTP7514 11 100 Ω AN 17 [SCL0/GPIO66]
I2C_SDA1
AMP 10 AM 17 [SDA0/GPIO65]
10. H15 I2C Map
100 Ω
IC5601
11 100 Ω
NTP7514
10
3.3k Ω
3.3k Ω
AMP
Only for training and service purposes
100 Ω
I2C_SCL3 IC5900
AP19 [SCL2/GPIO78] 100 Ω
P13000 33 Ω I2C_SDA3 NTP7514
FI-RE51S-HF-J-R1500 AN19 [SDA2/GPIO78] 100 Ω AMP
+3.3V_NOR
51P Wafer 33 Ω OPT
3.3k Ω
3.3k Ω
IC2500 33 Ω
URSA9
33 Ω
LG Electronics. Inc. All rights reserved.
H15 +3.3V_NOR
LG1210D
I2C_SCL2
IC3000 1 AN18 [SCL1/GPIO64] IC6900
R5F100GEAFB 33 Ω I2C_SDA2
2 AM 18 [SDA1/GPIO79] A8303SESTR-T
MICOM
LNB
- 31 -
AN8 [SCL3] I2C_SCL4 IC7000
3.3k Ω
7
3.3k Ω
AP8 [SDA3] I2C_SDA4 33 Ω A8303SESTR-T
8 LNB
+3.3V_NOR
33 Ω 27 [SCL_DEMOD]
3.3 k Ω
3.3 k Ω
33 Ω 30 [SDA_DEMOD]
+3.3V_NOR TU6701
TDJM-H151F
I2C_SCL5 I2C_SCL6
IC102 AF32 [SCL4] AF 34 [SCL5] 4 [SCL_RF]
33 Ω I2C_SDA5 AF 33 [SDA5] I2C_SDA6 33 Ω
NVRAM AG33 [SDA4] 5 [SDA_RF]
IC3202
3.3k Ω
3.3k Ω
3.3 k Ω
3.3 k Ω
SIL9679CNUC
MHL 3.0
+3.3V_NOR +3.3V_NOR
LGE Internal Use Only
Copyright ©
+3.5V_ST
3.3k Ω
3.3k Ω
11. MICOM I2C Map
Only for training and service purposes
RS-232C SOC_RX / TX
21 [P11/SI00/TXD0/TOOLRXD/SDA00]
Control I/F
EYE_SCL
11 [P70/KR0/SIK21/SCL21] 100 Ω
UART0_RXD / TXD
EYE_SDA WIFI/BT
I2C_SCL2 10 [P71/KR1/SI21/SDA21]
AW 14[SCL1/GPIO64] 1 [P60/SCLA0] 100 Ω NON_COMBO
AY 14 [SDA1/GPIO79] 33 Ω I2C_SDA2 2 [P61/SDAA0]
6 [P75/KR5/IMNTP9/SCK01/SCL01] IR P4000
H15 LG1210D 5 [P31/TI03/T003/INTP4] WOW_WAKE_UP
LG Electronics. Inc. All rights reserved.
INSTANT BOOT
GPIO19
SOC_RESET
PORES_N 18 [P14/RXD2/SI20/SDA20]
H14 LG1156A
MICOM
(IC3000)
- 32 -
R5F100GEAFB
HDMI_CEC
HDMI 1,2,3,4 7 [P74/KR4/INTP8/SI01/SDA01]
AMP_MUTE
AMP 22 [P10/SCK00/SCL00]
IC 5600
ETHERNET WOL_WAKE_UP
13 [P50//INTP1/SI11/SDA11]
IC5200
WOL POWER
WOL_CTL
ENABLE CTL 17[P15/PCLBUZ1/SCK20/SCL20]
IC5201
LGE Internal Use Only
/TU_RESET1
/TU_RESET2 [GPIO6] AK32 /RST_HUB
Copyright ©
TUNER AV36 [GPIO24] USB HUB(USB2,3)
RF_SWITCH_CTL [USB3_DP1] K37 USB2_HUB_IC_IN_DP
TU6702 AW37 [GPIO25] IC4202
[USB3_DM1] K36 USB2_HUB_IC_IN_DM
AV37 [GPIO26] GL857L-HHYXX
SPI FLASH MEMORY R9531_FLASH_WP [GPIO 34] AB39 USB_CTL1 OCP USB1
IC3207 AK33 [GPIO7] [GPIO 33] AB38 IC4401
/USB_OCD1
W25X20CLSNIG BD2242G
[GPIO 93] N41 USB_CTL2
/FRC_FLASH_WP [GPIO 90] N40 /USB_OCD2 OCP USB2/3
SPI FLASH MEMORY
AP6 [GPIO10] IC2301
IC1901 [GPIO 91] M40 USB_CTL3 TPS65286RHDR
MX25L3206EM2I-12G [GPIO 92] M41
/USB_OCD3
[USB3_DP1] U41 USB3_DP
COMPONENT1 PHONE JACK COMP1_DET [USB3_DM1] U42 USB1(3.0)
USB3_DM
JK3400 AW6[GPIO14] [USB3_TXP1] V41 JK4401
Only for training and service purposes
USB3_TX0P
PEJ038-4G6 [USB3_TXM1] V40 SJ113262
USB3_TX0M
[USB3_RXP1] T42 USB3_RX0P
CVBS1 PHONE JACK [USB3_RXM1] T41 USB3_RX0M
AV1_CVBS_DET
JK3402 AY6 [GPIO16] [USB3_RESREF1] Y40
12. GPIO(H15-LG1210D)
PEJ038-4Y6 USB_DP1
[USB2_DP0] Y41 USB2(2.0)
[USB2_DM0] Y42
USB_DM1
HEAD PHONE JACK
HP_DET
JK3403 AV38[GPIO28] USB_DP2
PEJ038-3B6 [USB2_DP1] W41 USB3(2.0)
AY15 [SCL0/GPIO66] [USB2_DM1] W42
AW15 [SDA0/GPIO65] USB_DM2
AW14 [SCL1/GPIO64] [USB3_DP0] AW1 WIFI_DP
LG Electronics. Inc. All rights reserved.
AY14 [SDA1/GPIO79] [USB3_DM0] AW2 WIFI_DM
I2C_SCL/SDA1~6 AV13 [SCL2/GPIO78] [GPIO19] AV7 BT_Reset
AW13 [SDA2/GPIO77] WIFI / BT Wafer
[GPIO18] AT7 M_RFMODULE_RESET P4000
Refer to I2C Map AW9 [SCL3] [GPIO86] AW10 M_REMOTE_RX
AV9 [SDA3] [GPIO85] AV10 M_REMOTE_TX SMAW200-H26S1
AF41 [SCL4] [GPIO83] AV11 M_REMOTE_RTS
AG40 [SDA4] [GPIO84] AV12 M_REMOTE_CTS
BA42 [SCL5]
BA41 [SDA5]
HDMI_HPD_1
CPU/GPU DUAL DCDC PMS_SCL Y39 [PMS_SCL] H15 [GPIO28] AM33 HDMI Jack(1,2,3,4)
IC2201 [GPIO29] AN32 HDMI_HPD_2
JK3203 / JK3200 / JK3201 / JK3202
- 33 -
AA38 [PMS_SDA] [GPIO24] AL32
65276V PMS_SDA HDMI_HPD_3 DADDR019A
IC100 [GPIO25] AL33
HDMI_HPD_4_MHL
RS232C SOC_RX AY11 [UART0_RXD]
LG1210D SIL9679_RESET MHL3.0
IC6801 AW12 [UART0_TXD] [GPIO30] AU37
MAX3232CDR SOC_TX [GPIO29] AF38 SIL9679_INT IC3202
SIL9679CNUC
TRST_N0 AU20 [TRST_N0]
Jtag I/F TMS0 AT19 [TMS0] OTP_WRITE H15D
P100 TCK0 AU18 [TCK0] [GPIO0] AF39
[VQPS] AJ36
12505WS-10A00 TDI0 AU19 [TDI0]
TDO0 AT18 [TDO0] TCON_I2C_EN
[GPIO22] AR7
L_DIM_EN Vx1 51p
[GPIO15] AP7
JACK SOC_RX2 AY11 [UART2_RXD/GPIO82] LOCKAn P13000
[GPIO13] AR6 FI-RE51S
P3401 Compensation_Done
AW12 [UART2_TXD/GPIO81]
12507WS-04L SOC_TX2 [GPIO30] AN33
[SC_CLK/GPIO125] D39 SMARTCARD_CLK
AMP(Woofer2) AMP(Woofer1) AMP(Center) [SC_DETECT/GPIO135] E38 SMARTCARD_DET
AMP_RESET_N SMARTCARD_VCC B-CAS
IC5900 IC5700 IC5400 AM6 [GPIO21] [SC_VCCEN/GPIO123] D37
[SC_VCC_SEL/GPIO122] E37 SMARTCARD_PWR_SEL IC6300
NTP7514 NTP7514 NTP7514 [SC_RST/GPIO124] D38 SMARTCARD_RST TDA8024TT
[SC_DATA/GPIO134] E39 SMARTCARD_DATA
MICOM INSTANT_BOOT AT6 [GPIO12]
IC3000 ETHERNET PHY
AT5 [GPIO11] /RST_PHY
R5F100GEAFB RETENTION_DISABLE [GPIO7] AY5 IC5200
RTL8201F-VB-CG
/PCM_CE1
J38 [CAM_CE1_N]
/PCM_CE2 K37 [CAM_CE2_N] SC_DET Full Scart(18P)
CAM_CD1_N H39 [CAM_CD1_N] [GPIO8] AY9
CI SLOT JK4800
CAM_CD2_N H38 [CAM_CD2_N]
JK700 G39 [CAM_IREQ_N] DA1R018H91E
CAM_IREQ_N
PCM_RESET H37 [CAM_RESET]
G37 [CAM_VCCEN_N] [PWM1/GPIO56] AE7 PWM2 POWER(24P)
PCM_5V_CTL G38 [CAM_WAIT_N]
CAM_WAIT_N J37 [CAM_REG_N] [PWM2/GPIO71] AE6 PWM1 P2301
CAM_REG_N SMAW200-H24S2
LGE Internal Use Only
RS232C
Copyright ©
IC6801
[P12/SO00/TxD0/TOOLTxD] 20
[P11/SI00/RxD0/TOOLrxD/SDA00] 21 SOC_RX/TX H15D
I2C_SCL/SDA2 1 [P60/SCLA0]/ 2[P61/SDAA0] IC100
H15
18 [P14/RxD2/SI20/SDA20] LG1210D
IC100 / IC101 SOC_RESET [P147/ANI18] 24 INSTANT BOOT
LG1210D/ LG1210A [P22/ANI2] 30 RETENTION DISABLE
AMP_MUTE AMP(MAIN)
GND PANEL_CTL [P10/SCK00/SCL00] 22 IC5600
4 [P63] NTP7514
+12V TO PANEL_VCC
6 [P75/KR5/INTP9/SCK01/SCL01] SIDE_HP_MUTE HP AMP
IR / KEY1/ KEY2 [P25/ANI5] 27 IC6100
EYE_SCL/SDA 10 [P71/KR1/SI21/SDA21]
WIFI/BT NON COMBO 11 [P70/KR0/SCK21/SCL21] TPA6138A2
P4000 WOW_WAKE_UP 5 [P31/TI03/TO03/INTP4]
Only for training and service purposes
LED_R / LOGO LIGHT 16 [P16/TI01/TO01/INTP5]
38 [P41/TI07/TO07]
[P24/ANI4] 28 OPT0 LOGO_LIGHT / NON_LOGO_LIGHT
12V-3.3V DCDC [P27/ANI7] 25 OPT1 PDP / LCD/OLED
ICIC2202 [P26/ANI6] 26 MODEL1_OPT_0~4 OPT2 NC5_5KEY / NC4_8KEY
TPS54527 [P23/ANI3] 29 OPT3 H14 / M14
32 [P20/ANI0/AVREFP]
[P62] 3 OPT4 GED / NON_GED
12V-1.5V DCDC DCDC 31 [P21/ANI1/AVREFM]
POWER_ON/OFF2_1
IC13493 IC6500 33 [P130]
BD9D321EFJ AP2132MP-2
EDID_WP
13. GPIO(MICOM - RENESAS)
[P146] 23 EXTERNAL EDID EEPROM
IC3203 / IC3204
LG Electronics. Inc. All rights reserved.
3.3V-2.5V LDO POWER_ON/OFF2_2
IC2301 8 [P73/KR3/SO01]
AP2132MP MICOM_DEBUG
[P40/TOOL0] 39 MICOM DEBUG 4P
MICOM_RESET P3000
12V-0.9V DUAL DCDC 12V-0.9V DCDC POWER_ON/OFF2_3 [/RESET] 40 12507WS-04L
IC2200 IC2204 9 [P72/KR2/SO21]
65276V TPS53513
(CPU/GPU) (H15D CORE) MICOM X-TAL
[P124/XT2/EXCLKS] 41
[P123/XT1] 42 X3000
12V-0.9V DCDC 32.768KHz
- 34 -
12V-1.0V DCDC
IC2205
IC12201
BD9D321EFJ
BD9D321EFJ
(DDR) HDMI_CEC HDMI 1 / 2 / 3 / 4
[P74/KR4/INTP8/SI01/SDA01] 7
JK3202, JK3203, JK3201, JK3200
12V-1.2V DCDC 12V-1.15V
IC2302 IC13402
AP2132MP TPS53513RVER
(DDR M2) (URSA9 CORE) SCART_MUTE SCART AUDIO MUTE
[P00/TI00/TXD1] 35
Q6000/Q6001
DCDC POWER_ON/OFF2_4
IC2303 34 [P01/TO00/RXD1]
BD9A300MUV
MHL_DET HDMI2 with MHL
[P137/INTP0] 43 JK3203
3.5V-1.8V DCDC 24V-5V DCDC POWER_ON/OFF1
IC2203 IC2300 15 [P17/TI02/TO02]
AP2132MP TPS65286RHDR MHL 3.0
IC3202
24V-5V DCDC SIL9679CNUC
IC2307
TPS54335DDA MHL OCP
IC3201
TPS2553DBV
WOL POWER ENABLE CONTROL WOL_CTL
IC5201 17 [P15/PCLBUZ1/SCK20/SCL20]
AP2151WG WIFI EN WIFI POWER ENABLE CONTROL
[P120/ANI19] 37 IC4000
RESET IC AP2191WG
POWER_DET
IC2304, IC2305 14 [P51/INTP2/SO11]
BD48K28G INV_CTL
[P13/TxD2/SO20] 19 24P POWER
ETHERNET RL_ON P2600
WOL_WAKE_UP [P140/PCLBUZ0/INTP6] 36 SMAW200-H24S5
IC5200 13 [P50/INTP1/SI11/SDA11]
RTL8201F-VB-CG
LGE Internal Use Only
14. DDR(LM, GM)
DDR3 IC500 DDR3 IC502
M0_DDR_A[0:15] M0_DDR_A[0:15]
M0_DDR_A0 [0:15] A[0:15] A[0:15]
M0_DDR_BA [0:2] M0_DDR_BA[0:2] M0_DDR_BA[0:2]
BA[0:2] BA[0:2]
M0_U_CLK/N
M0_DDR_U_CLK / CLKN CK / ~CK
M0_D_CLK/N
M0_DDR_D_CLK / CLKN CK / ~CK
M0_DDR_CKE
M0_DDR_CKE M0_DDR_CKE
CKE CKE
M0_DDR_ODT M0_DDR_ODT
M0_DDR_ODT ODT ODT
M0_DDR_RASN / CASN M0_DDR_RAS/CAS M0_DDR_RAS/CAS
H15
RASN/CASN RASN/CASN
M0_DDR_WEN M0_DDR_WEN
M0_DDR_WEN WEN WEN
M0_DDR_DQS0/N0
M0_DDR_DQS0 / DQS_N 0 DQSL / ~DQSL
M0_DDR_DQS0 / DQS_N 1 M0_DDR_DQS1/N0
DQSU / ~DQSU M0_DDR_DQS2/N2
M0_DDR_DQS0 / DQS_N 2 DQSL / ~DQSL
M0_DDR_DQS3/N3
M0_DDR_DQS0 / DQS_N 3 DQSU / ~DQSU
M0_DDR_DQ [0:15]
M0_DDR_DQ [0:31]
M0_DDR_DQ [16:31]
M0_RET MICOM
DDR3 IC501 DDR3 IC503
M1_DDR_A[0:15] M1_DDR_A[0:15]
M1_DDR_A0 [0:15] A[0:15] A[0:15]
M1_DDR_BA [0:2] M1_DDR_BA[0:2] M1_DDR_BA[0:2]
BA[0:2] BA[0:2]
M1_U_CLK/N
M1_DDR_U_CLK / CLKN CK / ~CK
M1_D_CLK/N
M1_DDR_D_CLK / CLKN CK / ~CK
M1_DDR_CKE
M1_DDR_CKE M1_DDR_CKE
CKE CKE
M1_DDR_ODT M1_DDR_ODT
M1_DDR_ODT ODT ODT
M1_DDR_RASN / CASN M1_DDR_RAS/CAS M1_DDR_RAS/CAS
H15
RASN/CASN RASN/CASN
M1_DDR_WEN M1_DDR_WEN
M1_DDR_WEN WEN WEN
M1_DDR_DQS0/N0
M1_DDR_DQS0 / DQS_N 0 DQSL / ~DQSL
M1_DDR_DQS0 / DQS_N 1 M1_DDR_DQS1/N0
DQSU / ~DQSU M1_DDR_DQS2/N2
M1_DDR_DQS0 / DQS_N 2 DQSL / ~DQSL
M1_DDR_DQS3/N3
M1_DDR_DQS0 / DQS_N 3 DQSU / ~DQSU
M1_DDR_DQ [0:15]
M1_DDR_DQ [0:31]
M1_DDR_DQ [16:31]
M1_RET MICOM
15. DDR(EM)
DDR3 IC600 DDR3 IC602
M2_DDR_A[0:15] M2_DDR_A[0:15]
M2_DDR_A0 [0:15] A[0:15] A[0:15]
M2_DDR_BA [0:2] M2_DDR_BA[0:2] M2_DDR_BA[0:2]
BA[0:2] BA[0:2]
M2_U_CLK/N
M2_DDR_U_CLK / CLKN CK / ~CK
M2_D_CLK/N
M2_DDR_D_CLK / CLKN CK / ~CK
M2_DDR_CKE
M2_DDR_CKE M2_DDR_CKE
CKE CKE
M2_DDR_ODT M2_DDR_ODT
M2_DDR_ODT ODT ODT
M2_DDR_RASN / CASN M2_DDR_RAS/CAS M2_DDR_RAS/CAS
H15
RASN/CASN RASN/CASN
M2_DDR_WEN M2_DDR_WEN
M2_DDR_WEN WEN WEN
M2_DDR_DQS0/N0
M2_DDR_DQS0 / DQS_N 0 DQSL / ~DQSL
M2_DDR_DQS0 / DQS_N 1 M2_DDR_DQS1/N0
DQSU / ~DQSU M2_DDR_DQS2/N2
M2_DDR_DQS0 / DQS_N 2 DQSL / ~DQSL
M2_DDR_DQS3/N3
M02DDR_DQS0 / DQS_N 3 DQSU / ~DQSU
M2_DDR_DQ [0:15]
M2_DDR_DQ [0:31]
M2_DDR_DQ [16:31]
M2_RET MICOM
Copyright © LG Electronics. Inc. All rights reserved. - 35 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
710
400
900
310
910
810
120
522
300
521
500
540
570
800
810
530
121
LV2
820
LV1
AG1
+Stand body
* Set + Stand
* Stand base
A10
A22
200
Copyright © LG Electronics. Inc. All rights reserved. - 36 - LGE Internal Use Only
Only for training and service purposes
Clock for LG1210D NVRAM
+3.3V_NORMAL
MAIN Clock(24Mhz) EMMC_DATA[0-7]
EB_ADDR[0-14]
X-TAL_1
IC102 C103
3.3pF 0.1uF EB_DATA[0-7]
GND_1
BR24G256FJ-3
SOC_EMMC_STRB
XIN_MAIN Write Protection
C100
- Low : Normal Operation
/USB_OCD3
/USB_OCD2
A0 VCC
EMMC_CLK
EMMC_CMD
USB_CTL2
USB_CTL3
EB_BE_N1
EB_BE_N0
1 8 - High : Write Protection
R108
2
1
EB_WE_N
EB_OE_N
EB_ADDR[14]
EB_ADDR[13]
EB_ADDR[12]
EB_ADDR[11]
EB_ADDR[10]
EB_ADDR[9]
EB_ADDR[8]
EB_ADDR[7]
EB_ADDR[6]
EB_ADDR[5]
EB_ADDR[4]
EB_ADDR[3]
EB_ADDR[2]
EB_ADDR[1]
EB_ADDR[0]
EB_DATA[7]
EB_DATA[6]
EB_DATA[5]
EB_DATA[4]
EB_DATA[3]
EB_DATA[2]
EB_DATA[1]
EB_DATA[0]
EMMC_DATA[7]
EMMC_DATA[6]
EMMC_DATA[5]
EMMC_DATA[4]
EMMC_DATA[3]
EMMC_DATA[2]
EMMC_DATA[1]
EMMC_DATA[0]
24MHz
X100
1M
A1 WP
2 7
3
4
A0’h 6
X-TAL_2
GND_2
A2 SCL
3.3pF R152 33 3 I2C_SCL5
XO_MAIN
C101
GND SDA
Move to x-tal side 4 5 I2C_SDA5 R136
(TSMC Recommend) 10K
1%
System Clock for Analog block(24Mhz)
AE42
AD40
AD41
AA41
AC40
AC41
AB40
AC42
AA40
AB41
AB42
AE41
N41
M41
M40
N40
K38
L37
P40
K39
L38
L41
H42
H40
F40
G40
F41
G41
G42
H41
J40
J41
K40
K41
K42
L40
L42
B42
C41
D40
D41
D42
E40
E42
E41
GPIO93/EB_CS3
GPIO92/EB_CS2
GPIO91/EB_CS1
GPIO90/EB_CS0
EB_WE_N
EB_OE_N
GPIO88/EB_WAIT
EB_BE_N1
EB_BE_N0
EB_ADDR15/GPIO89
EB_ADDR14
EB_ADDR13
EB_ADDR12
EB_ADDR11
EB_ADDR10
EB_ADDR9
EB_ADDR8
EB_ADDR7
EB_ADDR6
EB_ADDR5
EB_ADDR4
EB_ADDR3
EB_ADDR2
EB_ADDR1
EB_ADDR0
EB_DATA7
EB_DATA6
EB_DATA5
EB_DATA4
EB_DATA3
EB_DATA2
EB_DATA1
EB_DATA0
EMMC_CLK
EMMC_CMD
EMMC_STRB
EMMC_DATA7
EMMC_DATA6
EMMC_DATA5
EMMC_DATA4
EMMC_DATA3
EMMC_DATA2
EMMC_DATA1
EMMC_DATA0
EMMC_CAL
+3.3V_LNA_TU +3.3V_TUNER
+3.3V_NORMAL +3.3V_NORMAL
I2C PULL UP
3.3K
3.3K
3.3K
3.3K
IIC1_3.3K
IIC5_1.5K
IIC5_1.5K
IIC1_1,5K
R168-*1
R169-*1
R167-*1
IIC1_1.5K
R165-*1
B41 AC38
TU_NON_JP
TU_NON_JP
R134-*1 1.5K
IIC5_3.3K
XIN_MAIN
R133-*1 1.5K
XIN_MAIN GPIO143
IIC5_3.3K
3.3K
IIC1_3.3.K
A41 AB39
3.3K
1.5K
1.5K
1.5K
1.5K
AR109
AR110
R169
R167
USB_CTL1
R168
3.3K
R165
3.3K
XO_MAIN XO_MAIN GPIO142
3.3K
3.3K
AB38
R133
R134
R131
R132
GPIO141 /USB_OCD1
TU_JP
TU_JP
BB9 AC37
SOC_RESET PORES_N GPIO140 URSA9_CONNECT Can be changed other GPIO
AU38
I2C_SDA1 GPIO31
0.1uF
PLL SET[1:0] - Default(11) U35 AU37
I2C_SCL1 SIL9679_RESET
C108
OPM1 GPIO30
T35 AF38
00 : CPU clock(1104Mhz), M0 / M1 DDR(936Mhz) OPM0 GPIO29 SIL9679_INT
01 : CPU clock(1056Mhz), M0 / M1 DDR(936Mhz) AP9 AV38
I2C_SDA2 PLLSET1 PLLSET1 GPIO28 HP_DET
10 : CPU clock(579Mhz), M0 / M1 DDR(936Mhz) AN9 AE39
I2C_SCL2 PLLSET0 PLLSET0 GPIO27
11 : CPU clock(1104Mhz), M0 / M1 DDR(936Mhz) AD35 AV37
BOOT_MODE GPIO26 RF_SWITCH_CTL
AW37 R130
I2C_SDA3 GPIO25 /TU_RESET2
PLLSET1 AU20 AV36 100
I2C_SCL3 TRST_N0 TRST_N0 GPIO24 /TU_RESET1 AMP_RESET_N
AT19 AW7
R100
1.5K
PLLSET0 TMS0 C106
TMS0 GPIO23
AU18 AR7 1000pF
I2C_SDA4 TCK0 TCK0 GPIO22 TCON_I2C_EN
I2C for tuner AU19 AW8 50V
I2C_SCL4 +3.3V_NORMAL
TDI0 TDI0 GPIO21
AT18 AY8
TDO0 TDO0 GPIO20
AU16 AV7
I2C_SDA5 TRST_N1 GPIO19 BT_Reset
AT15 AT7
I2C_SCL5 C102 TMS1 GPIO18 M_RFMODULE_RESET
P100 AU14 AU5 R105 100
12505WS-10A00
0.1uF TCK1 GPIO17 3D_EN 3D_EN
T32_OPT AU15 AY6
I2C_SDA6 T32_OPT
HDMI_HPD_4_GPIO TDI1 GPIO16 AV1_CVBS_DET
I2C for tuner 1
AT14 AP7 R106 100 +3.3V_NORMAL
I2C_SCL6 TRST_N0 TDO1 GPIO15 L_DIM_EN L_DIM_EN
AW6
2
TDI0 WILL REMOVE H15D B0 GPIO14 COMP1_DET
AJ38 AR6
GPIO67 GPIO13 LOCKAn
3.3K
3
TDO0 AK37 AT6 R163 100
DEBUG
WebOS UHD HW Option
R103
5V_DET_HDMI3 GPIO68 GPIO12 INSTANT_BOOT
4
TMS0 AK36 AT5 R164 100
5V_DET_HDMI4 GPIO69 GPIO11 RETENTION_DISABLE
AL36 AP6 2 1
IC100
5
+3.3V_NORMAL TCK0 GPIO70 GPIO10 FRC_FLASH_WP
HDMI_HPD_3_GPIO AP5 For ISP
6 GPIO9 COMPENSATION_DONE
AY11 AY9 4 3
7
UART0_RXD GPIO8 SC_DET
AW11 AY5
UART0_TXD GPIO7 /RST_PHY SW100
8 AW10 AE38 JTP-1127WEM
INTERNAL_EDID
M_REMOTE_RX UART1_RXD/GPIO86 GPIO6
10K
AV10 AF37 DEBUG
LG1210D-B0(H15D-B0)
9
10K
10K
10K
10K
10K
10K
10K
10K
10K
M_REMOTE_TX UART1_TXD/GPIO85 GPIO5
10K
BIT0_1
BIT1_1
BIT4_1
BIT5_1
BIT6_1
BIT7_1
AV11 AE37 AE38,AD37,AE37,AF37 for UF85
OLED
M_REMOTE_RTS
FHD
10 UART1_RTS_N/GPIO83 GPIO4
AV12 AD37
M_REMOTE_CTS
R128
11 UART1_CTS_N/GPIO84 GPIO3
AW12 AD38
R111
R113
R115
R117
R119
R121
R123
R125
R126
R109
SOC_RX2 UART2_RXD/GPIO82 GPIO2
AY12 AC39
SOC_TX2 UART2_TXD/GPIO81 GPIO1
AF39
BIT0 AR112 33 GPIO0 OTP_WRITE
OPT AV34
SPI_CK_MHL SPI_SCLK0/GPIO37
BIT1
Jtag I/F For Main SPI_CS_HID
AV32
SPI_CS0/GPIO36
BIT2 AW34 BB4
+3.3V_NORMAL SPI_DO_MHL SPI_DO0/GPIO38 RGMII_REF_CLK EPHY_REFCLK
AY34 BB2
BIT3 SPI_DI_MHL SPI_DI0/GPIO39 RGMII_MDC EPHY_MDC
OPT AW33 BA2
AR113 33 SPI_SCLK1/GPIO137 RGMII_MDIO EPHY_MDIO
BIT4 READY FOR HID AY35
SPI_CS1/GPIO136
R137
AV33 BB6
10K
OPT
SPI_DO1/GPIO138 RGMII_RX_CLK
BIT5 AW35 BA1
SPI_DI1/GPIO139 RGMII_RXCTL EPHY_CRS_DV
HDMI_HPD_1_GPIO BA7
OPT
16V
0.1uF
BIT6 RGMII_RXD3
G
C109
AY15 BB8
I2C_SCL1 SCL0/GPIO66 RGMII_RXD2
AW15 BB7
BIT7 I2C_SDA1 SDA0/GPIO65 RGMII_RXD1 EPHY_RXD1
SOC_RX AW14 BA8
D
S
I2C_SCL2 SCL1/GPIO64 RGMII_RXD0 EPHY_RXD0
AR100 33 AY14
AO3438
BIT8 AR105
I2C_SDA2 SDA1/GPIO79
Q101
AV13 BA6 33
OPT
I2C_SCL3 SCL2/GPIO78 RGMII_TX_CLK
BIT9 AW13 BA3
I2C_SDA3 SDA2/GPIO77 RGMII_TXCTL EPHY_EN
AW9 BB5
BIT10 R138 0 I2C_SCL4 SCL3 RGMII_TXD3
AR104 33 AV9 BA5
+3.3V_NORMAL I2C_SDA4 SDA3 RGMII_TXD2
AF41 BB3
I2C_SCL5 SCL4 RGMII_TXD1 EPHY_TXD1
AR101 33 AF40 BA4
I2C_SDA5 SDA4 RGMII_TXD0 EPHY_TXD0
BA42
10K
EXTERNAL_EDID
R107
I2C_SCL6
10K
SCL5
10K
10K
10K
10K
10K
10K
R124 LCD 10K
10K
10K
10K
OPT
AR103 33 BA41
R122BIT7_0
R110BIT1_0
I2C_SDA6 SDA5
BIT0_0
BIT4_0
BIT5_0
BIT6_0
OPT
OPT
UHD
Y39
OPT
16V
0.1uF
G
R129
PMS_SCL PMS_SCL
C107
R114
R127
R104
R116
R118
R120
R112
AA38
PMS_SDA
GPIO122/SD_WP_N/SC_VCC_SEL
GPIO135/SD_DATA1/SC_DETECT
PMS_SDA
GPIO123/SD_CD_N/SC_VCCEN
GPIO134/SD_DATA0/SC_DATA
SOC_TX
D
S
G36
CTS_EXT
AO3438
GPIO125/SD_CLK/SC_CLK
GPIO124/SD_CMD/SC_RST
AB35
Q100
GTS_EXT
AM9
OPT
LTS_EXT
GPIO121/SD_DATA3
GPIO120/SD_DATA2
R139 0
USB3_RESREF0
USB3_RESREF1
CAM_VCCEN_N
CAM_IREQ_N
CAM_WAIT_N
CAM_CD1_N
CAM_CD2_N
CAM_CE1_N
CAM_CE2_N
CAM_RESET
CAM_REG_N
USB3_TXP0
USB3_TXM0
USB3_RXP0
USB3_RXM0
USB3_TXP1
USB3_TXM1
USB3_RXP1
USB3_RXM1
20140729 version
USB3_DP0
USB3_DM0
USB3_DP1
USB3_DM1
USB2_DP0
USB2_DM0
TXRTUNE0
USB2_DP1
USB2_DM1
TXRTUNE1
USB2_DP2
USB2_DM2
TXRTUNE2
BIT(0/1) DVB ATSC JP
00 TW/COL N/AMERICA
H39
H38
J38
K37
G39
H37
G37
G38
J37
D39
D38
D37
E37
F38
F37
E38
E39
AW1
AW2
AV3
AV4
AW3
AW4
AY3
U41
U42
V41
V40
T42
T41
Y40
Y41
Y42
P42
W41
W42
P41
R40
R41
N42
01 CN/HK KR JP
10 EU BR/PH
200 1%
200 1%
200 1%
200 1%
11 AJJA SRI LANKA
0.1uF
0.1uF
1K
1K
High Low High Low
OPT
OPT R101
R102
R162
R159
R157
R135
BIT2 Resolution UHD BIT2 Resolution UHD
C104
C105
FHD FHD
BIT3 Support BIT3 Support
EXTERNAL EDID INTERNAL EXTERNAL EXTERNAL EDID INTERNAL EXTERNAL
DDR Vendor Option
(ONLY H15D A1) FOR HDMI2.0 (FROM H15D B0) FOR HDMI1 (ONLY KOREA)
BIT(4/5) B/E(FRC)
CAM_CD1_N
CAM_CD2_N
/PCM_CE1
/PCM_CE2
CAM_IREQ_N
PCM_RESET
PCM_5V_CTL
CAM_WAIT_N
CAM_REG_N
SMARTCARD_CLK
SMARTCARD_RST
SMARTCARD_VCC
SMARTCARD_PWR_SEL
SMARTCARD_DET
SMARTCARD_DATA
WIFI_BT_DP
USB3_DP
USB3_DM
USB3_TX0P
USB3_TX0M
USB3_RX0P
USB3_RX0M
WIFI_BT_DM
USB_DP1
USB_DM1
USB_DP2
USB_DM2
00 NONE
01 URSA9
10 URSA9-P
11 URSA11
AC-coupling CAP
Place near by LG1156D
BIT(6/7) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP
00 T2/C/S2 PIP T2 PIP T2/C PIP Default ATSC PIP + T2 Default ISDB PIP Default
01 T2/C/S2 T2/S2 T2/C ATSC + T2 ISDB EXT
10 T/C T T/C ATSC ISDB INT
11 T2 ATSC PIP
High Low
BIT8 Display OLED LCD
BIT9 Model UF95 UF95/77
BIT10 Reserved
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-03-24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LG1210D System I/F
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LG1210A LG1210D
LG1210A
IC100
+3.3V_Bypass Cap LG1210D-B0(H15D-B0)
IC101 VDD09
LG1210A-AT(H15A-AT) PKG cap
+3.3V_NORMAL VDD09 : 0.1uF x 4
AVDD33_CVBS
+3.3V_NORMAL
AVDD33 +3.3V_NORMAL +0.9V_Bypass Cap PKG cap VDD33
K26
K27
DVDD33_1 DVDD09_1
U17
AVDD33_CVBS VDD33 : 0.1uF x 3 U18
AVDD33_XTAL (2) DVDD33_2 DVDD09_2
AVDD33 W16 K17 USB_BT_VDD33 : 0,1uF x 1 K28 U19
AVDD33_CVBS_1 GND_43 USB_VDD33 : 0,1uF x 1 DVDD33_3 DVDD09_3
Y16 K18 AB9 U20
AVDD33_CVBS_2 GND_44 HDMI_VDD33 : 0,1uF x 1 DVDD33_4 DVDD09_4
G12 L3 AC9 U21
DVDD33_1 GND_45 DVDD33_5 DVDD09_5
H16 L4 L216 AC33 U22
C241 0.1uF
C255 0.1uF
L222 DVDD33_6 DVDD09_6
C279 0.1uF
DVDD33_2 GND_46 L209 BLM18PG121SN1D AD33 U23
J16 L5 BLM18PG121SN1D BLM18PG121SN1D
DVDD33_3 GND_47 C13524 DVDD33_7 DVDD09_7
K16 L8 C13523 AE33 U24
DVDD33_4 GND_48 4.7uF 4.7uF DVDD33_8 DVDD09_8
U5 L9 AG9 U25
AVDD33_XTAL 10V 10V DVDD33_9 DVDD09_9
DVDD33_5 GND_49 AN18 U26
U6 L10
DVDD33_6 GND_50 DVDD33_10 DVDD09_10
U13 L11 AN22 V17
DVDD33_7 GND_51 DVDD33_11 DVDD09_11
U14 L12 AN23 V18
DVDD33_8 GND_52 DVDD33_12 DVDD09_12
T17 L13 V19
AVDD25 DVDD33_XTAL GND_53 VDD3V3_HDMI DVDD09_13 VDD09_CPU VDD09_GPU
P14 L16 VDD09 V33 V20 VDD09 VDD09_DDR
AVDD25_AAD GND_54 VDD09_XTAL AVDD33_USB_1 DVDD09_14
R8 L17 PKG cap W33 W17
VDD25_REF AVDD33_USB_2 DVDD09_15
AVDD25_AFE3CH_1 GND_55 DVDD18 : 0,1uF x 2 Y33 Y17
R9 L18 AVDD18_C4TX : 0,1uF x 1
AVDD25_AFE3CH_2 GND_56 AVDD33_USB_3 DVDD09_16
R10 M3 L227 AVDD18_HDMI : 0.1uF x 1 AN16 AB22
AVDD25_AFE3CH_3 GND_57 BLM18PG121SN1D AVDD33_BT_USB_1 DVDD09_17
AVDD18_LVRX : 0.1uF x 1 AN17 AB23
W4
AVDD25_AFE3CH_REF
M4
+2.5V_Bypass Cap DVDD18_XTAL : 0.1uF x 1 AVDD33_BT_USB_2 DVDD09_18 C282 C281
0.1uF
GND_58 AF33 AB24 C280 C283 C284
F17 M5
10uF
VDD25_AUD AVDD18_DR3PLL : 0.1uF x 1 AVDD33_HDMI_1 DVDD09_19 10uF 1uF 10uF 0.1uF 10uF
AVDD25_APLL GND_59 AG33 AB25
P7 M8 AFE 3CH Power OPT AVDD18_APLL : 0.1uF x 1 10V 10V 10V 10V
AVDD25_AUD_1 GND_60 AVDD33_HDMI_2 DVDD09_20
R7 M9 C240 AH33 AB26
AVDD25_AUD_2 GND_61 AVDD33_HDMI_3 DVDD09_21
R11 M10 0.1uF AC17
C301
C230
VDD25_LTX +2.5V_Normal AVDD25 VDD25_REF
AVDD25_CVBS_1 GND_62 16V DVDD09_22
R12 M11 R23 AD17
AVDD25_CVBS_2 GND_63 VDD18 DVDD18_1 DVDD09_23
F18 M12 L225 R25 AE17
DVDD25_LVDSTX_1 GND_64 L220 BLM15BD121SN1 DVDD18_2 DVDD09_24
F19 M13 BLM18PG121SN1D R26 AE18
DVDD25_LVDSTX_2 GND_65 DVDD18_3 DVDD09_25
0.1uF
R13 M16 R27 AE19
0.1uF
DVDD25_UDMD_1 GND_66 DVDD18_4 DVDD09_26
C270 10uF
R14 M17 T28 AE20
DVDD25_UDMD_2 GND_67 DVDD18_5 DVDD09_27
N7 M18 U28 AE21
AVDD18 AVDD25_VQPS GND_68 DVDD18_6 DVDD09_28
AB14 AF17
C288
M19
DVDD18_7 DVDD09_29
C274
GND_69 L226 AB28 AF18 Place Under Main SoC
G5 N1
DVDD18_1 GND_70 BLM15BD121SN1 C285 DVDD18_8 DVDD09_30 C213 C222
G7 N2 Place Under Main SoC AC14 AF19 C221
10uF 0.1uF 0.1uF
DVDD18_2 GND_71 VDD09 VDD09_HDMI_RX DVDD18_9 DVDD09_31 10uF
G11 N3 10V AC28 AF20 OPT
DVDD18_3 GND_72 DVDD18_10 DVDD09_32 10V
VSS25_REF AE28 AF21
H7 N4
DVDD18_4 GND_73 DVDD18_11 DVDD09_33
N5 1005 size bead AG14 AF22
GND_74 L228 DVDD18_12 DVDD09_34
G8 N8 Bottom side of chip BLM18PG121SN1D AH18 AF23
DVDD10_1 GND_75 DVDD18_13 DVDD09_35
G9 N9 AH19 AF24
0.1uF
VDDC10
DVDD10_2 GND_76 DVDD18_14 DVDD09_36
10uF
G10 N10 AH20 AF25
DVDD10_3 GND_77 DVDD18_15 DVDD09_37
J7 N11 AVDD18_HDMI AH22 AF26
DVDD18_16 DVDD09_38 VDD09_CPU
DVDD10_4 GND_78 AH23
J14 N12 PKG cap
VDD25_AUD DVDD18_17
C242
DVDD10_5 GND_79 AVDD18_C4TX
C243
K7 N13 +2.5V_Normal VDD25_LTX +2.5V_Normal V21 VDDCPU : 0.1uF x 5
DVDD10_6 GND_80 DVDD09_CPU_1
K14 N16 AD14 V22
DVDD10_7 GND_81 AVDD18_C4TX_1 DVDD09_CPU_2
L7 N17 L207 L200 C243 : Place Under Main SoC AE14 V23
DVDD10_8 GND_82 BLM18PG121SN1D BLM18PG121SN1D HDMI RX POWER SEPERATION AVDD18_C4TX_2 DVDD09_CPU_3
L14 N18 AF14 V24
DVDD10_9 AVDD18_C4TX_3 DVDD09_CPU_4
0.1uF
GND_83 AG25 V25
M7 P3
0.1uF
4.7uF
4.7uF
DVDD10_10 GND_84 VDD18_XTAL AVDD18_LVRX_1 DVDD09_CPU_5
M14 P4 OPT AH25 V26
VDD10_XTAL DVDD10_11 GND_85 AVDD18_LVRX_2 DVDD09_CPU_6
N14 P5 AF28 W21
DVDD10_12 GND_86 PKG cap AVDD18_HDMI_1 DVDD09_CPU_7
R19 P9 AG28 W22
C204
VDD15_M0 : 0.1uF x 3
C208
C202
C216
DVDD10_CVBS GND_87 AVDD18_HDMI_2 DVDD09_CPU_8
H14 P10 AH15 W23
DVDD10_LVDSTX GND_88 PKG cap AVDD18_HDMI_3 DVDD09_CPU_9
R20 P11 AH26 W24
DVDD10_XTAL GND_89 VDD15_M1 : 0.1uF x 3 AVDD18_HDMI_4 DVDD09_CPU_10
P8 P12 J30 W25
AVDD10_AFE3CH_LLPLL GND_90 AVDD18_DR3PLL DVDD09_CPU_11
G14 P13 PKG cap K30 W26
+1.5V_DDR DVDD18_XTAL DVDD09_CPU_12
AVDD10_APLL_2 GND_91 VDD15_M2 : 0.1uF x 3 Y21
R18 P16
AVDD10_UDMD GND_92 DVDD09_CPU_13
P17 G23 Y22
GND_93 DVDD15_M0_1 DVDD09_CPU_14
Y4 P18 G24 Y23
AVSS25_AFE3CH_REF GND_94 DVDD15_M0_2 DVDD09_CPU_15
P19 G25 Y24
VSS25_REF GND_95 DVDD15_M0_3 DVDD09_CPU_16
P20 G26 Y25
GND_96 DVDD15_M0_4 DVDD09_CPU_17
C19 R3 G27 Y26
GND_1 GND_97 DVDD15_M0_5 DVDD09_CPU_18
D3 R4 G28 AA21 Place Under Main SoC
GND_2 GND_98 DVDD15_M0_6 DVDD09_CPU_19
D4 R16 G29 AA22
GND_3 GND_99 DVDD15_M0_7 DVDD09_CPU_20 C219
D12 R17 G30 AA23 C217
+1.5V_DDR DVDD15_M0_8 DVDD09_CPU_21 0.1uF 10uF
GND_4 GND_100
D19
E4
GND_5 GND_101
T3
T4
+1.5V_Bypass Cap G31
G8
DVDD15_M0_9 DVDD09_CPU_22
AA24
AA25
OPT 10V
OPT
GND_6 GND_102 DVDD15_M1_1 DVDD09_CPU_23
E12 T16 G9 AA26 VDD09_GPU
GND_7 GND_103 DVDD15_M1_2 DVDD09_CPU_24
F16 T18 G10
GND_8 GND_104 DVDD15_M1_3 PKG cap
G4 T19 +1.5V_DDR +1.5V_DDR G11 AC22 VDDGPU : 0.1uF x 5
G13
GND_9
GND_10
GND_105
GND_106
T20 +1.0V_Bypass Cap +1.8V_Bypass Cap +1.5V_DDR G12
DVDD15_M1_4
DVDD15_M1_5
DVDD09_GPU_1
DVDD09_GPU_2
AC23
G16 U3 G13 AC24
GND_11 GND_107 VREF_M0_1 DVDD15_M1_6 DVDD09_GPU_3
G17 U4 VDD10_XTAL VREF_M0_0 G14 AC25
R200
R202
1K 1%
1K 1%
GND_12 GND_108 +1.0V_VDD DVDD15_M1_7 DVDD09_GPU_4
G18 U7 G15 AC26
GND_13 GND_109 DVDD15_M1_8 DVDD09_GPU_5
H4 U8 G16 AD22
GND_14 GND_110 L211 DVDD15_M1_9 DVDD09_GPU_6
H5 U9 BLM18PG121SN1D K7 AD23
VDD18 DVDD15_M2_1 DVDD09_GPU_7
GND_15 GND_111 AVDD18 L7 AD24
H8 U10
1%
1%
GND_16 GND_112 DVDD15_M2_2 DVDD09_GPU_8 Place Under Main SoC
0.1uF
4.7uF
H9 U11 M7 AD25
R201
R203
GND_17 GND_113 DVDD15_M2_3 DVDD09_GPU_9
H10 U12 N7 AD26
GND_18 GND_114 L300 DVDD15_M2_4 DVDD09_GPU_10 C218 C220
1K
1K
H11 U15 BLM18PG121SN1D P7 AE22 0.1uF
DVDD15_M2_5 DVDD09_GPU_11 0.1uF
C239
GND_19 GND_115
C211
H12 U16 R7 AE23 OPT 16V
For Debug DVDD15_M2_6 DVDD09_GPU_12
10uF
GND_20 GND_116 T7 AE24 OPT
H13 U17
GND_21 GND_117 DVDD15_M2_7 DVDD09_GPU_13
0.1uF
0.1uF
0.1uF
0.1uF
H17 U18 U7 AE25
GND_22 GND_118 DVDD15_M2_8 DVDD09_GPU_14 VDD09_DDR
H18 U19 VREF_M2_1 V7 AE26
DVDD15_M2_9 DVDD09_GPU_15
C225
GND_23 GND_119
J4 V3 OPT OPT OPT VREF_M2_0 PKG cap L204
GND_24 GND_120 BLM18PG121SN1D
C203
C206
C207
C317
J5 V4 AC1 AD16 AVDD09_C4TX : 0.1uF x 1
GND_25 GND_121 VREF_M1_1 M2_DDR_VREF_1 AVDD09_C4TX_1
J8 V5 D2 AE16 C228 C229
GND_26 GND_122 +1.5V_DDR +1.5V_DDR +1.5V_DDR +1.5V_DDR VREF_M1_0 M2_DDR_VREF_0 AVDD09_C4TX_2
J9 V6 +1.0V_VDD VDDC10 C1 AF16 0.01uF 1uF
GND_27 GND_123 VREF_M0_1 M1_DDR_VREF_1 AVDD09_C4TX_3 VDD09_XTAL 10V
J10 V7 A20
GND_28 GND_124 VREF_M0_0 M1_DDR_VREF_0
J11 V8 Place under A chip A21 J31
L206 VREF_M2_0 VREF_M2_1 VREF_M1_0 VREF_M1_1 M0_DDR_VREF_1 DVDD09_DR3PLL VDD18
GND_29 GND_125 MOSFET_TOSHIBA
R204
R206
R208
R210
1K 1%
1K 1%
1K 1%
1K 1%
J12 V9 BLM18PG121SN1D B40 K31
GND_30 GND_126 M0_DDR_VREF_0 DVDD09_XTAL Q200
J13 V10 VDD18_XTAL SSM3J332R
0.1uF
GND_31 GND_127
22uF
22uF
T16
D
J17 V11 AJ36
S
GND_32 GND_128 VDD09_DDR DVDD09_DDR_1 VQPS
4.7K
J18 V12 T17
R232
10K
GND_33 GND_129 DVDD09_DDR_2
T18 Y28
1%
1%
1%
1%
K3 V13
C209
C210
C214
DVDD09_DDR_3 AVDD18_APLL
G
GND_34 GND_130
R205
R207
R209
R211
K4 V14 T19 AA28
GND_35 GND_131 DVDD09_DDR_4 DVDD09_APLL VDD09_HDMI_RX
R230
K5 V15 V16
1K
1K
1K
1K
GND_36 GND_132 DVDD09_DDR_M2_1 VDD09_DDR
K8 V16 W16
DVDD09_DDR_M2_2 OTP_WRITE
GND_37 GND_133 Y16 AG15
K9 V17 MOSFET_AOS
GND_38 GND_134 DVDD09_DDR_M2_3 DVDD09_HDMI_TX Q200-*1
K10 W6 AG26
GND_39 GND_135 DVDD09_HDMI_RX_1 AO3435
K11 W17 AG27
D
S
GND_40 GND_136 C215 C212 DVDD09_HDMI_RX_2
K12 W20 10uF 0.1uF
GND_41 GND_137 10V
K13 Y17 OPT
GND_42 GND_138 OPT
G
Place Under Main SoC
PKG cap
DVDD09_XTAL : 0.1uF x 1
DVDD09_DR3PLL : 0.1uF x 1
DVDD09_APLL : 0.1uF x 1
GND JIG POINT +3.3V_Bypass Cap +1.8V_Bypass Cap
+3.3V_NORMAL VDD18 VDD18 VDD18
VDD33 VDD18_XTAL AVDD18_HDMI AVDD18_C4TX
L203 L234 L201 L202
BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
JP202
JP203
JP204
JP205
0.1uF
10uF
10uF
For Debug
C364 0.1uF
BLM18PG121SN1D
C2010.1uF
0.1uF
0.1uF
OPT C226 C227
1uF 0.01uF
C223
C224
C231
10V
OPT OPT
C200
C205
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-03-24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN POWER
11/05/31
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC101 IC100
LG1210A-AT(H15A-AT) LG1210D-B0(H15D-B0)
E1 BA10 BA32
INTR_HOSTIF INTR_GBB STPIO_CLK/GPIO42 FE_DEMOD3_TS_CLK
Clock for LG1210A INTR_AFE3CH
E2
D1
BB10
BA11
INTR_AFE3CH STPIO_SOP/GPIO41
BB32
BB31
FE_DEMOD3_TS_SYNC
INTR_AGPIO INTR_AGPIO STPIO_VAL/GPIO40 FE_DEMOD3_TS_VAL
BA33
STPIO_ERR/GPIO55 FE_DEMOD3_TS_ERROR
A6 BB17 BA31
AUD_FS20CLK AUD_FS20CLK STPIO_DATA/GPIO54 FE_DEMOD3_TS_DATA
MAIN Clock(24Mhz) B6 BA17 BB35
FE_DEMOD2_TS_CLK
X-TAL_1
AUD_FS21CLK AUD_FS21CLK STPI_CLK/GPIO47
IC101 A5 BA36
GND_1
12pF AUD_FS23CLK STPI_SOP/GPIO46 FE_DEMOD2_TS_SYNC
XIN_SUB LG1210A-AT(H15A-AT) B5 BB16 BA35
FE_DEMOD2_TS_VAL
AUD_FS24CLK DAC0CLK_OUT STPI_VAL/GPIO45
C426 A4 BA16 BB36
AUD_FS25CLK DAC1CLK_OUT STPI_ERR/GPIO44 FE_DEMOD2_TS_ERROR
C4 BB34 FE_DEMOD2_TS_DATA[0]
2
1
V18 FE_DEMOD2_TS_DATA[0-7]
24MHz
AUDCLK_OUT_SUB STPI_DATA0/GPIO43
R441
X400
UDMD_SIF_OUT BA34
N19 H20 FE_DEMOD2_TS_DATA[1]
1M
C450 0.1uF STPI_DATA1/GPIO103
XIN_SUB XIN_SUB AAD_ADC_SIF TU_SIF C20 BB33
N20 H19 C451 0.1uF FE_DEMOD2_TS_DATA[2]
XOUT_SUB AUD_HDMI_MCLK STPI_DATA2/GPIO102
3
4
XO_SUB AAD_ADC_SIFM AY32
J19 C452 10uF FE_DEMOD2_TS_DATA[3]
STPI_DATA3/GPIO101
X-TAL_2
GND_2
VSB_AUX_XIN A2 BA14 AW32
12pF R453 T1 C453 2.2uF FE_DEMOD2_TS_DATA[4]
AUDA_VBG_EXT AUD_DAC1_LRCK AUD_DAC1_LRCK STPI_DATA4/GPIO100
XOUT_SUB L1 P1 B2 BB13 AY31 FE_DEMOD2_TS_DATA[5]
C427 240 CLK_SEL AUDA_OUTL AUDA_OUTL AUD_DAC1_SCK AUD_DAC1_SCK STPI_DATA5/GPIO99
L2 P2 B1 BA13 AW31 FE_DEMOD2_TS_DATA[6]
Move to x-tal side CLK_IN AUDA_OUTR AUDA_OUTR AUD_DAC1_LRCH AUD_DAC1_LRCH STPI_DATA6/GPIO98
M20 R1 C2 BB12 AV31 FE_DEMOD2_TS_DATA[7]
(TSMC Recommend) CLK_OUT AUDA_SCART_OUTL SCART_Lout_SOC AUD_DAC0_LRCK AUD_DAC0_LRCK STPI_DATA7/GPIO97
R2 EU 100 R479 C1 BA12
AUDA_SCART_OUTR SCART_Rout_SOC AUD_DAC0_SCK AUD_DAC0_SCK
EU 100 R480 D2 BB11 AY37
0.01uF
0.01uF
AUD_DAC0_LRCH AUD_DAC0_LRCH FE_TP_CLK FE_DEMOD1_TS_CLK
T2 B4 BB15 BB38
AUD_ADC_LRCK AUD_ADC_LRCK FE_TP_SOP FE_DEMOD1_TS_SYNC
AUAD_L_CH4_IN
EU R426
EU R442
U1 A3 BA15 BB37
22K
22K
AUD_ADC_SCK AUD_ADC_SCK FE_TP_VAL FE_DEMOD1_TS_VAL
AUAD_R_CH4_IN B3 BB14 BA38
E3 V1 FE_DEMOD1_TS_ERROR
SOC_RESET PORES_N AUAD_L_CH3_IN AUAD_L_CH3_IN AUD_ADC_LRCH AUD_ADC_LRCH FE_TP_ERR
BA37
Place JACK Side Place SOC Side U2 FE_DEMOD1_TS_DATA[0]
C458
C460
EU
FE_TP_DATA0 FE_DEMOD1_TS_DATA[0-7]
EU
C400 AUAD_R_CH3_IN AUAD_R_CH3_IN
M2 W2 A7 BB18 BB41 FE_DEMOD1_TS_DATA[1]
0.1uF BB_SCL BB_SCL FE_TP_DATA1
OPM0 AUAD_L_CH2_IN AUAD_L_CH2_IN B7 BA18 AY40
M1 Y2 FE_DEMOD1_TS_DATA[2]
OPM1 AUAD_R_CH2_IN AUAD_R_CH2_IN BB_SDA BB_SDA FE_TP_DATA2
W3 D9 AW21 BB40 FE_DEMOD1_TS_DATA[3]
AUAD_L_CH1_IN BB_TP_CLK BB_TP_CLK FE_TP_DATA3
A8 Y3 C8 AY21 BA40 FE_DEMOD1_TS_DATA[4]
MIP_SCL MAIN_SCL AUAD_R_CH1_IN BB_TP_ERR BB_TP_ERR FE_TP_DATA4
B8 D8 AW20 AY39 FE_DEMOD1_TS_DATA[5]
MIP_SDA MAIN_SDA BB_TP_SOP BB_TP_SOP FE_TP_DATA5
W1 C7 AY20 BA39 FE_DEMOD1_TS_DATA[6]
AUAD_R_REF AUAD_R_REF BB_TP_VAL BB_TP_VAL FE_TP_DATA6
V2 D7 AW19 AY38 FE_DEMOD1_TS_DATA[7]
AUAD_L_REF AUAD_L_REF BB_TP_DATA7 BB_TP_DATA7 FE_TP_DATA7
FOR S2A E7 AV19
L408 2.2uH BB_TP_DATA6 BB_TP_DATA6 TPI_CLK
R434 E8 AV17 P39
100 C424 0.047uF W13 L19 BB_TP_DATA5 BB_TP_DATA5 TPI_CLK
AV1_CVBS_IN AV1_CVBS_IN_SOC AV1_CVBS_IN_SOC CVBS_IN3 DISEQCO E6 AV18 R37 TPI_SOP
Y14 K19 TP402 TPI_ERR
C405 C410 R410 SC_CVBS_IN_SOC CVBS_IN2 FT_CLK BB_TP_DATA4 BB_TP_DATA4 TPI_SOP TPI_VAL
Y15 D20 D6 AW18 R38
2200pF 2200pF 75 BB_TP_DATA3 BB_TP_DATA3 TPI_VAL
TU_CVBS_SOC CVBS_IN1 FT_CLK_SEL C5 AY18 T37 TPI_ERR
50V 1% C443 0.047uF Y13 K20
CVBS_VCM IFAGCS BB_TP_DATA2 BB_TP_DATA2 TPI_ERR TPI_DATA[0] TPI_DATA[0-7]
EU R450 68 L20 D5 AW17 N37
EU BB_TP_DATA1 BB_TP_DATA1 TPI_DATA0
L409 2.2uH DTV/MNT_V_OUT_SOC ABB_VSYNC R487 E5 AY17 N38 TPI_DATA[1]
R433 W15 J20
100 C425 0.047uF
BUF_OUT1 IFAGC IF_AGC BB_TP_DATA0 BB_TP_DATA0 TPI_DATA1 TPI_DATA[2]
SC_CVBS_IN SC_CVBS_IN_SOC W14 N39
C439 0 Close to LG1156A TPI_DATA2
C408 C462 DMD_DAC_OUT C459 A11 R451 BB22 P38 TPI_DATA[3]
EU OPT 100pF U20 330
2200pF 2200pF R411 C454 0.1uF 0.1uF CLK_54M CLK_54M TPI_DATA3
UDMD_INCOM
EU
50V E9 AV21 L39 TPI_DATA[4]
50V EU 75 SC_CVBS_IN_SOY V19 TU_W_BR/TW/CO
1% UDMD_ADC_INP ADC_I_INP CVBS_GC2 CVBS_GC2 TPI_DATA4 TPI_DATA[5]
EU V20 B9 BA20 M38
Placed as close as possible to SOC ADC_I_INN CVBS_GC1 CVBS_GC1 TPI_DATA5
UDMD_ADC_INN A9 BB20 M37 TPI_DATA[6]
R432 C423 0.047uF W7 W19
100 REFT REFT UDMD_ADC_I_INP CVBS_GC0 CVBS_GC0 TPI_DATA6 TPI_DATA[7]
TU_CVBS TU_CVBS_SOC Y6 Y19 E11 AV20 P37
REFB REFB UDMD_ADC_I_INN CVBS_UP CVBS_UP TPI_DATA7
R447 68 C440 0.047uF Y7 W18 E10 AV22
ADC1_COM UDMD_ADC_Q_INP CVBS_DN CVBS_DN
R448 68 C441 0.047uF W10 Y18 Close to LG1156A V37 TPO_CLK TPO_ERR
ADC2_COM UDMD_ADC_Q_INN TPIO_CLK TP400
R449 68 C442 0.047uF Y12 A13 R492 330 BB23 U39 TPO_SOP
ADC3_COM FS00CLK FS00CLK TPIO_SOP
W5 A12 R407 330 BA23 V38 TPO_VAL
EU SC_ID_SOC SC1_SID AUDCLK_OUT A2D_AMP_CLK TPIO_VAL
Y5 G3 Close to LG1156D W37 TPO_ERR
R423 100 TPIO_ERR TPO_DATA[0-7]
SC_FB_SOC SC_FB_SOC SC1_FB GPIO0 A10 TPO_DATA[0]
SC_FB W8 G2 DAC_START R400 330BA22 DAC_START
U37
COMP1_PB_IN_SOC PB1_IN GPIO1 TPIO_DATA0
10K EU Y8 G1 C11 AY24 T38 TPO_DATA[1]
R435 COMP1_Y_IN_SOC Y1_IN GPIO2 DAC_DATA4 DAC_DATA4 TPIO_DATA1
SC_ID SC_ID_SOC Y9 H3 D11 AW23 T39 TPO_DATA[2]
COMP1_Y_IN_SOC_SOY SOY1_IN GPIO3 BIT0 DAC_DATA3 DAC_DATA3 TPIO_DATA2
W9 H2 C10 AY23 U38 TPO_DATA[3]
EU NON_EU COMP1_PR_IN_SOC PR1_IN GPIO4 BIT1 DAC_DATA2 DAC_DATA2 TPIO_DATA3
R422 Y10 H1 D10 AW22 Y37 TPO_DATA[4]
EU
NON_EU R436 DAC_DATA1 DAC_DATA1 TPIO_DATA4
R436-*1 COMP2_PB_IN_SOC PB2_IN GPIO5 BIT2 B10 BA21 W38 TPO_DATA[5]
R422-*1 0 75 2.7K 0 W11 J3
COMP2_Y_IN_SOC Y2_IN GPIO6 BIT3 DAC_DATA0 DAC_DATA0 TPIO_DATA5
Y11 T5 W39 TPO_DATA[6]
COMP2_Y_IN_SOC_SOY SOY2_IN GPIO7 TPIO_DATA6
W12 R5 D14 AW25 Y38 TPO_DATA[7]
COMP2_PR_IN_SOC PR2_IN GPIO8 AAD_GC4 AAD_GC4 TPIO_DATA7
J2 C13 AV25
GPIO9 BIT4 AAD_GC3 AAD_GC3
E20 D13 AV23 AE5
GPIO10 BIT5 AAD_GC2 AAD_GC2 AUDCLK_OUT
F20 E14 AW24 AE7 AR405
I2S_I/F
AAD_GC1 AAD_GC1 DACRLRCH AUD_LRCK
GPIO11 BIT6 E13 AV24 AE6 100
E19 AAD_GC0 AAD_GC0 AUD_LRCH
GPIO12 BIT7 DACLRCH 1/16W
J1 AF5
BIT8 DACSLRCH/GPIO127 AUD_SCK
GPIO13 E18 AV29 AF6
K2 AAD_DATA9 AAD_DATA9 AUD_LRCH_TW
EU GPIO14 BIT9 DACCLFCH/GPIO126
R403 33 D18 AW29 AD6
EU EU EU EU
C417 0.047uF K1
SC_B COMP1_PB_IN_SOC GPIO15 BIT10 AAD_DATA8 AAD_DATA8 DACSCK C401
R404 33 EU C418 0.047uF C17 AY29 AD7
SC_G COMP1_Y_IN_SOC AAD_DATA7
D17 AW28
AAD_DATA7 DACLRCK
FOR EMI 5pF
C428 1000pF
SC_CVBS_IN_SOY COMP1_Y_IN_SOC_SOY AAD_DATA6 AAD_DATA6 50V
R427 C16 AV28 BA9
SC_R 33 C419 0.047uF
COMP1_PR_IN_SOC AAD_DATA5 AAD_DATA5 IEC958OUT SPDIF_OUT
OPT 50V 10pF
OPT 50V 10pF
D16 AV26
C472
C473
OPT 50V 10pF
R414 1% 75
R416 1% 75
EU
EU
EU
1% 75
C474
EU AAD_DATA4 AAD_DATA4
E16 AV27 AC6
AEC_KR/US
AEC_KR/US
AAD_DATA3 AAD_DATA3 PCMI3LRCK/GPIO113
E17 AW27 AC5
0 R401
0 R402
AAD_DATA2 AAD_DATA2 PCMI3SCK/GPIO112
R412
E15 AY27 AC7
AAD_DATA1 AAD_DATA1 PCMI3LRCH/GPIO114
D15 AW26
AAD_DATA0 AAD_DATA0
C14 AY26 AH37
AAD_DATAEN AAD_DATAEN AUD_SUBMCK/GPIO117
R405 33 C420 0.047uF AH36
COMP1_Pb COMP2_PB_IN_SOC AUD_SUBLRCH/GPIO104
R406 33 C421 0.047uF B20 BB30 AJ37
COMP1_Y COMP2_Y_IN_SOC ADCO_OUT_CLK ADCO_OUT_CLK AUD_SUBSCK/GPIO118
C429 1000pF AH38
COMP2_Y_IN_SOC_SOY AUD_SUBLRCK/GPIO119
A14 BA24
COMP1_Pr 33 C422 0.047uF
COMP2_PR_IN_SOC LVDSTX_TAP HSR_AP
B14 BB24 AF7
R415 1% 75
R417 1% 75
R431
R413 1% 75
Placed as close as possible to IC101 LVDSTX_TAN HSR_AN PCMI4LRCK/GPIO116 READY FOR ECHO CANCELLATION
A15 BA25 AH5 AEC_KR/US
LVDSTX_TBP HSR_BP PCMI4SCK/GPIO115 R424 0
+3.3V_NORMAL B15 BB25 AG7
LVDSTX_TBN HSR_BN PCMI4LRCH0/GPIO80 I2S_MAIN_OUT
A16 BA26 AG6 R425 0
LVDSTX_TCP HSR_CP PCMI4LRCH1/GPIO95 I2S_WOOF_OUT
B16 BB26 AJ5 AEC_KR/US
LVDSTX_TCN HSR_CN PCMI4LRCH2/GPIO94
A17 BA27 AH6 AR404
+2.5V_Normal LVDSTX_TCLKP HSR_CLKP PCMI4LRCH3/GPIO72 33
B17 BB27 1/16W +3.3V_NORMAL
LVDSTX_TCLKN HSR_CLKN
L407 A18 BA28 AL6
IC400 LVDSTX_TDP HSR_DP TEST0
AUDIO IN NJM2561BF1
LVDSTX_TDN
B18
A19
BB28
BA29
HSR_DN TEST1
AL5
1% C455 LVDSTX_TEP HSR_EP
R455 B19 BB29
10uF
R418
1%
EU 27K C432 EU 4.7uF
POWER_SAVE
1 6
V+
EU AUAD_L_REF
51K
1%
LVDSTX_TEN HSR_EN
For UF85
SC_L_IN AUAD_L_CH3_IN C412
4.7uF C449
R457
EU
47K R456 1%
EU 10K 1% VOUT GND 0.1uF 51K AM4
R437
0.1uF
2 5 C4TX_0N TXB4N/VX1_0N
C414
1% AM3
EU 4.7uF C4TX_0P TXB4P/VX1_0P
R419 EU 27K C433 AL2
SC_R_IN AUAD_R_CH3_IN
EU
VSAG VIN C4TX_1N TXB3N/VX1_1N
EU 10K 1% 3 4 BB19 AL1
R438 MIP_SCL D2A_SCL C4TX_1P TXB3P/VX1_1P
DTV/MNT_V_OUT DTV/MNT_V_OUT_SOC BA19 AL4
MIP_SDA D2A_SDA C4TX_2N TXBCLKN/VX1_2N
AL3
C4TX_2P TXBCLKP/VX1_2P
AUAD_R_REF AK4
C4TX_3N TXB2N/VX1_3N
AD4 AK3
1% L_VSOUT_LD/GPIO76 C4TX_3P TXB2P/VX1_3P
C456 AM5 AJ2
R458 4.7uF DIM0_SCLK/GPIO75 C4TX_4N TXB1N/VX1_4N
1% 47K AL7 AJ1
COMP1/AV1/DVI_L_IN 10V DIM0_MOSI/GPIO74 C4TX_4P TXB1P/VX1_4P
R420 27K C434 4.7uF AM7 AJ4
AUAD_L_CH2_IN
For UF85 AM6 DIM1_SCLK/GPIO73 C4TX_5N
AJ3
TXB0N/VX1_5N
R439 10K 1% DIM1_MOSI/GPIO87 C4TX_5P TXB0P/VX1_5P
1% AH4
COMP1/AV1/DVI_R_IN C4TX_6N TXA4N/VX1_6N
R421 27K C435 4.7uF AF42 AH3
AUAD_R_CH2_IN IROUT/GPIO133 C4TX_6P TXA4P/VX1_6P
PWM2 AH7 AG2
R440 10K 1% PWM0/GPIO57 C4TX_7N TXA3N/VX1_7N
PWM1 AJ6 AG1
R443 C437 PWM1/GPIO56 C4TX_7P TXA3P/VX1_7P
AK7 AG4
ADC_I_INN IF_N GPIO71 C4TX_8N TXACLKN/VX1_8N
56 0.01uF AJ7 AG3
PWM_IN C4TX_8P TXACLKP/VX1_8P
AF4
To ADC
C436
20pF
AFE 3CH REF Setting C4TX_9N
AF3
TXA2N/VX1_9N
C4TX_9P TXA2P/VX1_9P
AE2
R444 C438 C4TX_10N TXA1N/VX1_10N
AE1
ADC_I_INP IF_P C4TX_10P TXA1P/VX1_10P
56 0.01uF Placed as close as possible to IC101 AE4
C4TX_11N TXA0N/VX1_11N
AE3
C444 C4TX_11P TXA0P/VX1_11P
Tuner IF Filter Placed as close as possible to IC100
REFT
0.1uF AK6 AD3
FRC_LR/GPIO132 TX_LOCKN Vx1_LOCKn_V/O
C446
0.1uF Must be used
C445
REFB
0.1uF
DIMMING
AR402
PWM_DIM2
33
1/16W
PWM1
LG1210A LG1210D
PWM_DIM PWM2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H004-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-03-24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
MAIN AUDIO/VIDEO
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC100
LG1210D-B0(H15D-B0)
E29
M0_DDR_A0 M0_DDR_A0
E25
M0_DDR_A1 M0_DDR_A1
E31
M0_DDR_A2 M0_DDR_A2
E33
M0_DDR_A3 M0_DDR_A3
D23
M0_DDR_A4 M0_DDR_A4
D32
M0_DDR_A5 M0_DDR_A5
E23
M0_DDR_A6 M0_DDR_A6
E32
M0_DDR_A7 M0_DDR_A7
D24
M0_DDR_A8 M0_DDR_A8
E30 H15_DDR_Hynix_29n
M0_DDR_A9
D22
M0_DDR_A9 H15_DDR_Hynix_29n
M0_DDR_A10 M0_DDR_A10 IC500
D25 M0_DDR_VREFCA IC502 M0_1_DDR_VREFCA
M0_DDR_A11 M0_DDR_A11 H5TQ4G63AFR-RDC
M0_DDR_A12
D26
M0_DDR_A12
H5TQ4G63AFR-RDC
D30 DDR3
M0_DDR_A13 M0_DDR_A13 M0_1_DDR_VREFDQ
E24 M0_DDR_VREFDQ
M0_DDR_A14 M0_DDR_A14 N3 4Gbit M8 DDR3
E34 M0_DDR_A0 A0 VREFCA N3 M8
M0_DDR_A15/M0_DDR_CS1 M0_DDR_A1
P7
A1
(x16) M0_DDR_A0 A0 4Gbit VREFCA
P3 P7
D33 M0_DDR_A2 A2
M0_DDR_A1 A1 (x16)
N2 H1 P3
M0_DDR_BA0 M0_DDR_BA0 M0_DDR_A2 A2
E22 M0_DDR_A3 A3 VREFDQ N2 H1
M0_DDR_BA1 M0_DDR_BA1 P8 M0_DDR_A3 A3
D29 M0_DDR_A4 A4 VREFDQ
P2 +1.5V_DDR P8
M0_DDR_BA2 M0_DDR_BA2 M0_DDR_A4 A4
M0_DDR_A5 A5 R542 P2 +1.5V_DDR
R8 L8 M0_DDR_A5 A5
C26 M0_DDR_A6 A6 ZQ R544
M0_D_CLK M0_U_CLK R2 R8 L8
M0_DDR_U_CLK M0_U_CLK +1.5V_DDR 240 M0_DDR_A6 A6 ZQ
B26 M0_DDR_A7 A7 1% R2
M0_U_CLKN T8 240
M0_DDR_U_CLKN M0_DDR_A7 A7
100
100
C35 M0_DDR_A8 A8 T8 1%
R519
R535
M0_DDR_D_CLK M0_D_CLK R3 B2 M0_DDR_A8 A8
B35 M0_DDR_A9 A9 VDD_1 R3 B2
M0_DDR_D_CLKN M0_D_CLKN L7 D9 M0_DDR_A9 A9
E26 M0_DDR_A10 A10/AP VDD_2 VDD_1
R7 G7 L7 D9
M0_DDR_CKE M0_DDR_CKE M0_D_CLKN M0_U_CLKN M0_DDR_A10 A10/AP VDD_2
E27 M0_DDR_A11 A11 VDD_3 R7 G7
M0_DDR_CS0 M0_CS0_N N7 K2 M0_DDR_A11
M0_DDR_A12 A12/BC VDD_4 A11 VDD_3
C569 C570 C571 T3 K8 N7 K2
0.1uF 0.1uF M0_DDR_A13 A13 M0_DDR_A12 A12/BC VDD_4
E35 0.1uF VDD_5 T3 K8
M0_DDR_ODT M0_DDR_ODT 16V 16V 16V T7 N1 M0_DDR_A13 A13 VDD_5
D35 M0_DDR_A14 A14 VDD_6 T7 N1
M0_DDR_RASN M0_DDR_RASN M7 N9 M0_DDR_A14
D34 NC_5 VDD_7 A14 VDD_6
R1 M7 N9
M0_DDR_CASN M0_DDR_CASN NC_5 VDD_7
D27 VDD_8 R1
M0_DDR_WEN M0_DDR_WEN M2 R9
M0_DDR_BA0 BA0 VDD_9 VDD_8
N8 M2 R9
+1.5V_DDR +1.5V_DDR Place M0 POWER PLANE M0_DDR_BA0 BA0 VDD_9
D31 M0_DDR_BA1 BA1 N8
M0_DDR_RESET_N M0_DDR_RESET_N M3 M0_DDR_BA1
M0_DDR_BA2 BA2 BA1
M0_1_DDR_VREFCA A1 M3
M0_DDR_VREFCA M0_DDR_BA2 BA2
C40 240 R500 VDDQ_1 A1
M0_DDR_ZQCAL J7 A8
M0_D_CLK CK VDDQ_2 VDDQ_1
1% J7 A8
R514
R536
1K 1%
1K 1%
K7 C1 M0_U_CLK
B36 M0_D_CLKN CK VDDQ_3 CK VDDQ_2
K9 C9 K7 C1
M0_DDR_DQS0 M0_DDR_DQS0 M0_U_CLKN CK VDDQ_3
C36 M0_DDR_CKE CKE VDDQ_4 K9 C9
M0_DDR_DQS_N0 M0_DDR_DQS_N0 D2 M0_DDR_CKE CKE
B34 VDDQ_5 VDDQ_4
L2 E9 D2
M0_DDR_DQS1 M0_DDR_DQS1 VDDQ_5
A34 M0_CS0_N CS VDDQ_6 L2 E9
K1 F1
1%
1%
M0_DDR_DQS_N1 M0_DDR_DQS_N1 M0_CS0_N CS VDDQ_6
B27 M0_DDR_ODT ODT VDDQ_7 K1 F1
R515
R537
M0_DDR_DQS2 M0_DDR_DQS2 J3 H2 C534 0.1uF M0_DDR_ODT ODT
C27 M0_DDR_RASN RAS VDDQ_8 VDDQ_7
K3 H9 0.1uF J3 H2 C566 0.1uF
M0_DDR_DQS_N2 M0_DDR_DQS_N2 C535 M0_DDR_RASN RAS VDDQ_8
1K
1K
B25 M0_DDR_CASN CAS VDDQ_9 K3 H9 0.1uF
M0_DDR_DQS3 L3 C567
M0_DDR_DQS3 M0_DDR_WEN M0_DDR_CASN CAS VDDQ_9
A25 WE L3
M0_DDR_DQS_N3 M0_DDR_DQS_N3 J1 M0_DDR_WEN WE
NC_1 J1
T2 J9
A33 M0_DDR_RESET_N RESET NC_2 NC_1
L1 T2 J9
M0_DDR_DM0 M0_DDR_DM0 M0_DDR_RESET_N RESET NC_2
A36 NC_3 L1
M0_DDR_DM1 M0_DDR_DM1 L9
A24 NC_4 NC_3
F3 L9
M0_DDR_DM2 M0_DDR_DM2 NC_4
A27 M0_DDR_DQS0 DQSL F3
M0_DDR_DM3 M0_DDR_DM3 G3 M0_DDR_DQS2
M0_DDR_DQS_N0 DQSL IC500-*1 DQSL
H5TQ4G63CFR_RDC G3
M0_DDR_DQS_N2 DQSL IC502-*1
B38 H5TQ4G63CFR_RDC
M0_DDR_DQ0 M0_DDR_DQ0 C7 A9 H15_DDR_Hynix_25n
N3 M8
B31 M0_DDR_DQS1 DQSU VSS_1 P7
A0
A1
VREFCA
C7 A9 H15_DDR_Hynix_25n
M0_DDR_DQ1 M0_DDR_DQ1 B7 B3 P3
A2
M0_DDR_DQS3
N3
A0 VREFCA
M8
C39 M0_DDR_DQS_N1 DQSU VSS_2
N2
A3 VREFDQ
H1 DQSU VSS_1 P7
A1
M0_DDR_DQ2 E1
P8
A4
B7 B3 P3
A2
M0_DDR_DQ2 P2
A5 M0_DDR_DQS_N3 DQSU VSS_2
N2
A3 VREFDQ
H1
C32 VSS_3 R8
A6 ZQ
L8
E1
P8
A4
M0_DDR_DQ3 M0_DDR_DQ3 +1.5V_DDR E7 G8 R2
A7
P2
A5
A39 M0_DDR_DM0 DML VSS_4
T8 VSS_3 R8 L8
+1.5V_DDR +1.5V_DDR R3
A8
B2 E7 G8 R2
A6 ZQ
M0_DDR_DQ4 M0_DDR_DQ4 D3 J2 L7
A9 VDD_1
D9
M0_DDR_DM2 T8
A7
A31 M0_DDR_DM1 DMU VSS_5 R7
A10/AP VDD_2
G7 DML VSS_4 R3
A8
B2
M0_DDR_DQ5 J8 N7
A11 VDD_3
K2 D3 J2 L7
A9 VDD_1
D9
M0_DDR_DQ5 M0_1_DDR_VREFDQ T3
A12/BC VDD_4
K8 M0_DDR_DM3 DMU VSS_5 R7
A10/AP VDD_2
G7
B39 VSS_6 T7
A13 VDD_5
N1 J8 N7
A11 VDD_3
K2
M0_DDR_DQ6 M0_DDR_DQ6 M0_DDR_VREFDQ E3 M1 M7
A14 VDD_6
N9 T3
A12/BC VDD_4
K8
C31 M0_DDR_DQ0 DQL0 VSS_7 NC_5 VDD_7
R1 VSS_6 T7
A13 VDD_5
N1
M0_DDR_DQ7 F7 M9 M2
VDD_8
R9 E3 M1 M7
A14 VDD_6
N9
M0_DDR_DQ7 BA0 VDD_9
M0_DDR_DQ16 DQL0 VSS_7 NC_5 VDD_7
R516
R538
R1
1K 1%
1K 1%
N8
B32 M0_DDR_DQ1 DQL1 VSS_8 M3
BA1
F7 M9 M2
VDD_8
R9
M0_DDR_DQ8 M0_DDR_DQ8 F2 P1 BA2
A1
M0_DDR_DQ17 N8
BA0 VDD_9
B37 M0_DDR_DQ2 DQL2 VSS_9 J7
VDDQ_1
A8 DQL1 VSS_8 M3
BA1
M0_DDR_DQ9 C573 C574 C575 F8 P9 K7
CK VDDQ_2
C1 F2 P1 BA2
A1
M0_DDR_DQ9 0.1uF 0.1uF M0_DDR_DQ3 K9
CK VDDQ_3
C9 M0_DDR_DQ18 DQL2 VSS_9 J7
VDDQ_1
A8
C33 0.1uF DQL3 VSS_10 CKE VDDQ_4
D2 F8 P9 K7
CK VDDQ_2
C1
M0_DDR_DQ10 M0_DDR_DQ10 16V 16V 16V H3 T1 L2
VDDQ_5
E9
M0_DDR_DQ19 DQL3 K9
CK VDDQ_3
C9
C38 M0_DDR_DQ4 DQL4 VSS_11 K1
CS VDDQ_6
F1 VSS_10 CKE VDDQ_4
D2
M0_DDR_DQ11 H8 T9 J3
ODT VDDQ_7
H2 H3 T1 L2
VDDQ_5
E9
M0_DDR_DQ11 M0_DDR_DQ5 K3
RAS VDDQ_8
H9 M0_DDR_DQ20 DQL4 VSS_11 K1
CS VDDQ_6
F1
DQL5 VSS_12
1%
1%
C34 L3
CAS VDDQ_9
H8 T9 J3
ODT VDDQ_7
H2
M0_DDR_DQ12 M0_DDR_DQ12 G2 WE
J1
M0_DDR_DQ21 DQL5
K3
RAS VDDQ_8
H9
VSS_12
R517
R539
CAS VDDQ_9
A37 M0_DDR_DQ6 DQL6 T2
RESET
NC_1
NC_2
J9
G2
L3
WE
M0_DDR_DQ13 M0_DDR_DQ13 H7 NC_3
L1
M0_DDR_DQ22 DQL6 T2
NC_1
J1
J9
B33 M0_DDR_DQ7 DQL7 F3
NC_4
L9
H7 RESET NC_2
L1
1K
1K
M0_DDR_DQ14 M0_DDR_DQ14 B1 G3
DQSL
M0_DDR_DQ23 DQL7
NC_3
L9
C37 Place M1 POWER PLANE VSSQ_1 DQSL
B1
F3
DQSL
NC_4
M0_DDR_DQ15 M0_DDR_DQ15 D7 B9 C7
DQSU VSS_1
A9 G3
DQSL
B29 M0_DDR_DQ8 DQU0 VSSQ_2
B7
DQSU VSS_2
B3 VSSQ_1
C3 D1
E1 D7 B9 C7
DQSU VSS_1
A9
M0_DDR_DQ16 M0_DDR_DQ16 E7
VSS_3
G8
M0_DDR_DQ24 DQU0 VSSQ_2
B7
DQSU VSS_2
B3
C23 M0_DDR_DQ9 DQU1 VSSQ_3 D3
DML
DMU
VSS_4
VSS_5
J2
C3 D1 VSS_3
E1
M0_DDR_DQ17 M0_DDR_DQ17 C8 D8 VSS_6
J8
M0_DDR_DQ25 DQU1
E7
DML VSS_4
G8
C30 M0_DDR_DQ10 DQU2 VSSQ_4
E3
DQL0 VSS_7
M1 VSSQ_3 D3
DMU VSS_5
J2
M0_DDR_DQ18 C2 E2
F7
DQL1 VSS_8
M9 C8 D8 VSS_6
J8
M0_DDR_DQ18 M0_DDR_DQ11
F2
DQL2 VSS_9
P1
M0_DDR_DQ26 DQU2 VSSQ_4
E3
DQL0 VSS_7
M1
B22 DQU3 VSSQ_5 F8
DQL3 VSS_10
P9
C2 E2
F7
DQL1 VSS_8
M9
M0_DDR_DQ19 M0_DDR_DQ19 A7 E8 H3
DQL4 VSS_11
T1
M0_DDR_DQ27 DQU3
F2
DQL2 VSS_9
P1
A30 M0_DDR_DQ12 DQU4 VSSQ_6
H8
DQL5 VSS_12
T9 VSSQ_5 F8
DQL3 VSS_10
P9
M0_DDR_DQ20 A2 F9
G2
DQL6 A7 E8 H3
DQL4 VSS_11
T1
M0_DDR_DQ20 M0_DDR_DQ13
H7
DQL7 M0_DDR_DQ28 DQU4 VSSQ_6
H8
DQL5 VSS_12
T9
A22 DQU5 VSSQ_7 VSSQ_1
B1
A2 F9
G2
DQL6
M0_DDR_DQ21 M0_DDR_DQ21 B8 G1 D7
DQU0 VSSQ_2
B9
M0_DDR_DQ29 DQU5
H7
DQL7
B30 M0_DDR_DQ14 DQU6 VSSQ_8
C3
DQU1 VSSQ_3
D1 VSSQ_7 VSSQ_1
B1
M0_DDR_DQ22 +1.5V_DDR A3 G9
C8
DQU2 VSSQ_4
D8 B8 G1 D7
DQU0 VSSQ_2
B9
M0_DDR_DQ22 M0_DDR_DQ15
C2
DQU3 VSSQ_5
E2
M0_DDR_DQ30 DQU6 VSSQ_8
C3
DQU1 VSSQ_3
D1
C22 DQU7 VSSQ_9 A7
DQU4 VSSQ_6
E8
A3 G9
C8
C2
DQU2 VSSQ_4
D8
E2
M0_DDR_DQ23 M0_DDR_DQ23 A2
B8
DQU5 VSSQ_7
F9
G1 M0_DDR_DQ31 DQU7 VSSQ_9 A7
DQU3 VSSQ_5
E8
B23 A3
DQU6 VSSQ_8
G9 A2
DQU4 VSSQ_6
F9
M0_DDR_DQ24 M0_DDR_DQ24 DQU7 VSSQ_9 B8
DQU5
DQU6
VSSQ_7
VSSQ_8
G1
B28 A3
DQU7 VSSQ_9
G9
M0_DDR_DQ25 M0_DDR_DQ25
C24
M0_DDR_DQ26 M0_DDR_DQ26
C29
R524
10K
M0_DDR_DQ27 M0_DDR_DQ27
C25
M0_DDR_DQ28 M0_DDR_DQ28
A28 R502 22
M0_DDR_DQ29 M0_DDR_DQ29 DDR_RET
B24 5%
M0_DDR_DQ30 M0_DDR_DQ30
C28 R523 C
M0_DDR_DQ31 M0_DDR_DQ31 Q500
1K
B MMBT3904(NXP)
D21 INSTANT_BOOT
M0_RET DDR_RET
E
IC100 Real USE : 1Gbit
LG1210D-B0(H15D-B0) H5TQ1G63DFR-PBC(x16)
E13
1Gbit : T7(NC_6)
M1_DDR_A0 M1_DDR_A0
M1_DDR_A1
E9
M1_DDR_A1
H15_DDR_Hynix_29n 4Gbit : T7(A14) H15_DDR_Hynix_29n
M1_DDR_A2
E15
M1_DDR_A2
IC501 IC503
M1_DDR_VREFCA M1_1_DDR_VREFCA
M1_DDR_A3
E17
M1_DDR_A3
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC
D7
M1_DDR_A4 M1_DDR_A4
D16
M1_DDR_A5 M1_DDR_A5 M1_DDR_VREFDQ
E7 N3 M8 M1_1_DDR_VREFDQ
M1_DDR_A6 M1_DDR_A6 M1_DDR_A0 A0 DDR3 VREFCA M1_DDR_A0
N3 DDR3 M8
E16 P7 A0 VREFCA
M1_DDR_A7 M1_DDR_A7 M1_DDR_A1 A1 4Gbit M1_DDR_A1
P7
A1
4Gbit
D8 P3
M1_DDR_A8 (x16) P3
M1_DDR_A8
E14
M1_DDR_A2
N2
A2
H1 M1_DDR_A2 A2 (x16)
M1_DDR_A9 M1_DDR_A9 M1_DDR_A3 N2 H1
D6 A3 VREFDQ M1_DDR_A3 A3 VREFDQ
P8 P8
M1_DDR_A10 M1_DDR_A10 M1_DDR_A4 A4
D9 P2 M1_DDR_A4 A4
M1_DDR_A11 M1_DDR_A11 M1_DDR_A5 P2
D10 A5 M1_DDR_A5 A5
M1_D_CLK M1_U_CLK R8 L8 R543 240 R8 L8
M1_DDR_A12 M1_DDR_A12 M1_DDR_A6 A6 ZQ R545 240
D14 R2 M1_DDR_A6 A6 ZQ
M1_DDR_A13 M1_DDR_A13 M1_DDR_A7 +1.5V_DDR R2
A7
100
100
E8 T8 M1_DDR_A7 A7 +1.5V_DDR
R518
R530
M1_DDR_A14 M1_DDR_A14 M1_DDR_A8 T8
E18 A8 M1_DDR_A8 A8
R3 B2 R3 B2
M1_DDR_A15/M1_DDR_CS1 M1_DDR_A9 A9 VDD_1 M1_DDR_A9
L7 D9 A9 VDD_1
M1_DDR_A10 L7 D9
D17 M1_D_CLKN M1_U_CLKN A10/AP VDD_2 M1_DDR_A10 A10/AP VDD_2
R7 G7 R7 G7
M1_DDR_BA0 M1_DDR_BA0 M1_DDR_A11 A11 VDD_3
E6 N7 K2 M1_DDR_A11 A11 VDD_3
M1_DDR_BA1 M1_DDR_BA1 M1_DDR_A12 N7 K2
- Place these caps near Memory
A12/BC VDD_4
- Place these caps near Memory
D13 T3 K8 M1_DDR_A12 A12/BC VDD_4
M1_DDR_BA2 M1_DDR_BA2 M1_DDR_A13 T3 K8
A13 VDD_5 M1_DDR_A13 A13 VDD_5
T7 N1 T7 N1
M1_DDR_A14 A14 VDD_6 M1_DDR_A14
C6 M7 N9 A14 VDD_6
M1_DDR_U_CLK M1_U_CLK M7 N9
B6 NC_5 VDD_7 NC_5 VDD_7
R1 R1
M1_DDR_U_CLKN M1_U_CLKN VDD_8
C15 M2 R9 VDD_8
DDR3 1.5V bypass Cap
DDR3 1.5V bypass Cap
M1_DDR_D_CLK M1_D_CLK M1_DDR_BA0 M2 R9
B15 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9
N8 N8
M1_DDR_D_CLKN M1_D_CLKN M1_DDR_BA1 BA1
E10 M3 M1_DDR_BA1 BA1
M1_DDR_CKE M1_DDR_CKE M1_DDR_BA2 M3
E11 +1.5V_DDR +1.5V_DDR BA2 M1_DDR_BA2 BA2
A1 A1
M1_DDR_CS0 M1_CS0_N VDDQ_1
J7 A8 VDDQ_1
M1_D_CLK J7 A8
E19 M1_1_DDR_VREFCA CK VDDQ_2 M1_U_CLK CK VDDQ_2
M1_DDR_VREFCA K7 C1 K7 C1
M1_DDR_ODT M1_DDR_ODT M1_D_CLKN CK VDDQ_3
D19 K9 C9 M1_U_CLKN CK VDDQ_3
M1_DDR_RASN M1_DDR_RASN M1_DDR_CKE K9 C9
CKE VDDQ_4
R510
R531
1K 1%
1K 1%
D18 D2 M1_DDR_CKE CKE VDDQ_4
M1_DDR_CASN M1_DDR_CASN D2
D11 VDDQ_5 VDDQ_5
L2 E9 L2 E9
M1_DDR_WEN M1_DDR_WEN M1_CS0_N CS VDDQ_6
K1 F1 M1_CS0_N CS VDDQ_6
M1_DDR_ODT K1 F1
D15 ODT VDDQ_7 M1_DDR_ODT ODT VDDQ_7
J3 H2 C529 0.1uF J3 H2
M1_DDR_RESET_N M1_DDR_RESET_N M1_DDR_RASN RAS VDDQ_8 C561 0.1uF
M1_DDR_RASN
1%
1%
K3 H9 RAS VDDQ_8
C530 0.1uF K3 H9 C562 0.1uF
M1_DDR_CASN CAS VDDQ_9
R511
R532
B1 240 R501 L3 M1_DDR_CASN CAS VDDQ_9
M1_DDR_ZQCAL M1_DDR_WEN L3
WE M1_DDR_WEN WE
1% J1
1K
1K
J1
B16 NC_1 NC_1
T2 J9 T2 J9
M1_DDR_DQS0 M1_DDR_DQS0 M1_DDR_RESET_N RESET NC_2
C16 L1 M1_DDR_RESET_N RESET NC_2
M1_DDR_DQS_N0 M1_DDR_DQS_N0 L1
B14 NC_3 NC_3
L9 L9
M1_DDR_DQS1 M1_DDR_DQS1 NC_4
A14 F3 NC_4
M1_DDR_DQS_N1 M1_DDR_DQS_N1 M1_DDR_DQS0 F3
B7 DQSL M1_DDR_DQS2 DQSL
G3 G3
M1_DDR_DQS2 M1_DDR_DQS2 M1_DDR_DQS_N0 DQSL IC501-*1
C7 H5TQ4G63CFR_RDC M1_DDR_DQS_N2 DQSL IC503-*1
H5TQ4G63CFR_RDC
M1_DDR_DQS_N2 M1_DDR_DQS_N2
B5 C7 A9 H15_DDR_Hynix_25n
M1_DDR_DQS3 M1_DDR_DQS3 M1_DDR_DQS1
N3
A0 VREFCA
M8
C7 A9 H15_DDR_Hynix_25n
N3 M8
A5 DQSU VSS_1 P7
A1 M1_DDR_DQS3 DQSU VSS_1 P7
A0 VREFCA
B7 B3 P3
A2
B7 B3 P3
A1
M1_DDR_DQS_N3 M1_DDR_DQS_N3 M1_DDR_DQS_N1 DQSU VSS_2
N2
A3 VREFDQ
H1
N2
A2
H1
E1
P8
A4
M1_DDR_DQS_N3 DQSU VSS_2 P8
A3 VREFDQ
VSS_3
P2
R8
A5
L8
E1 P2
A4
A5
A13 +1.5V_DDR +1.5V_DDR E7 G8 R2
A6 ZQ
VSS_3 R8
A6 ZQ
L8
M1_DDR_DM0 M1_DDR_DM0 M1_DDR_DM0 T8
A7
E7 G8 R2
A16 DML VSS_4 R3
A8
B2 M1_DDR_DM2 DML VSS_4
T8
A7
A8
D3 J2 L7
A9 VDD_1
D9
D3 J2
R3 B2
M1_DDR_DM1 M1_DDR_DM1 M1_1_DDR_VREFDQ M1_DDR_DM1 DMU VSS_5 R7
A10/AP VDD_2
G7
L7
A9 VDD_1
D9
A4 J8 N7
A11 VDD_3
K2 M1_DDR_DM3 DMU VSS_5 R7
A10/AP VDD_2
G7
M1_DDR_DM2 M1_DDR_VREFDQ A12/BC VDD_4
J8 N7
A11 VDD_3
K2
M1_DDR_DM2 VSS_6
T3
A13 VDD_5
K8
T3
A12/BC VDD_4
K8
A7 E3 M1
T7
A14 VDD_6
N1
VSS_6 T7
A13 VDD_5
N1
M1_DDR_DM3 M1_DDR_DM3 M1_DDR_DQ0
M7
NC_5 VDD_7
N9
E3 M1 M7
A14 VDD_6
N9
DQL0 VSS_7
R512
R533
1K 1%
1K 1%
R1
F7 M9 M2
VDD_8
R9 M1_DDR_DQ16 DQL0 VSS_7 NC_5 VDD_7
VDD_8
R1
M1_DDR_DQ1 N8
BA0 VDD_9
F7 M9 M2 R9
B18 DQL1 VSS_8 M3
BA1
M1_DDR_DQ17 DQL1 VSS_8
N8
BA0
BA1
VDD_9
M1_DDR_DQ0 F2 P1 BA2
A1
F2 P1
M3
BA2
M1_DDR_DQ0 M1_DDR_DQ2 DQL2 VSS_9 J7
VDDQ_1
A8
M1_DDR_DQ18 VDDQ_1
A1
B11 F8 P9 K7
CK VDDQ_2
C1 DQL2 VSS_9 J7
CK VDDQ_2
A8
M1_DDR_DQ1 M1_DDR_DQ1 M1_DDR_DQ3 K9
CK VDDQ_3
C9 F8 P9 K7 C1
C19 DQL3 VSS_10 CKE VDDQ_4
D2 M1_DDR_DQ19 DQL3 VSS_10
K9
CK
CKE
VDDQ_3
VDDQ_4
C9
M1_DDR_DQ2 H3 T1 L2
VDDQ_5
E9
H3 T1 VDDQ_5
D2
M1_DDR_DQ2 M1_DDR_DQ4 DQL4 VSS_11 K1
CS VDDQ_6
F1
M1_DDR_DQ20
L2
CS VDDQ_6
E9
1%
1%
C12 H8 T9 J3
ODT VDDQ_7
H2 DQL4 VSS_11 K1
ODT VDDQ_7
F1
M1_DDR_DQ3 M1_DDR_DQ3 M1_DDR_DQ5 K3
RAS VDDQ_8
H9 H8 T9 J3 H2
DQL5 VSS_12 RAS VDDQ_8
R513
R534
CAS VDDQ_9 K3
A19 G2
L3
WE
M1_DDR_DQ21 DQL5 VSS_12 L3
CAS VDDQ_9
H9
M1_DDR_DQ4 M1_DDR_DQ4 M1_DDR_DQ6 NC_1
J1
G2 WE
J1
A11 DQL6 T2
RESET NC_2
J9
M1_DDR_DQ22 DQL6 T2
NC_1
J9
H7 L1 RESET NC_2
1K
1K
M1_DDR_DQ5 M1_DDR_DQ5 M1_DDR_DQ7
NC_3
L9 H7 L1
B19 DQL7 F3
NC_4
M1_DDR_DQ23 DQL7
NC_3
NC_4
L9
M1_DDR_DQ6 B1 G3
DQSL
B1
F3
DQSL
M1_DDR_DQ6 VSSQ_1 DQSL G3
DQSL
C11 D7 B9 C7 A9 VSSQ_1
M1_DDR_DQ7 M1_DDR_DQ7 M1_DDR_DQ8 B7
DQSU VSS_1
B3 D7 B9 C7 A9
B12 DQU0 VSSQ_2 DQSU VSS_2
E1 M1_DDR_DQ24 DQU0 VSSQ_2
B7
DQSU
DQSU
VSS_1
VSS_2
B3
M1_DDR_DQ8 C3 D1 E7
VSS_3
G8
C3 D1 VSS_3
E1
M1_DDR_DQ8 M1_DDR_DQ9 DQU1 VSSQ_3 D3
DML VSS_4
J2
M1_DDR_DQ25
E7
DML VSS_4
G8
B17 C8 D8
DMU VSS_5
J8 DQU1 VSSQ_3 D3
DMU VSS_5
J2
M1_DDR_DQ9 M1_DDR_DQ9 M1_DDR_DQ10 E3
VSS_6
M1 C8 D8 J8
C13 DQU2 VSSQ_4 F7
DQL0 VSS_7
M9 M1_DDR_DQ26 DQU2 VSSQ_4
E3
DQL0
VSS_6
VSS_7
M1
M1_DDR_DQ10 C2 E2 F2
DQL1 VSS_8
P1
C2 E2
F7
DQL1 VSS_8
M9
M1_DDR_DQ10 M1_DDR_DQ11 DQU3 VSSQ_5 F8
DQL2 VSS_9
P9
M1_DDR_DQ27
F2
DQL2 VSS_9
P1
C18 A7 E8 H3
DQL3 VSS_10
T1 DQU3 VSSQ_5 F8
DQL3 VSS_10
P9
M1_DDR_DQ11 M1_DDR_DQ11 M1_DDR_DQ12 H8
DQL4 VSS_11
T9 A7 E8 H3 T1
C14 DQU4 VSSQ_6 G2
DQL5 VSS_12
M1_DDR_DQ28 DQU4 VSSQ_6
H8
DQL4
DQL5
VSS_11
VSS_12
T9
M1_DDR_DQ12 A2 F9 H7
DQL6
A2 F9
G2
DQL6
M1_DDR_DQ12 M1_DDR_DQ13 DQU5 VSSQ_7 DQL7
B1
M1_DDR_DQ29
H7
DQL7
A17 B8 G1 D7
VSSQ_1
B9 DQU5 VSSQ_7 VSSQ_1
B1
M1_DDR_DQ13 M1_DDR_DQ13 M1_DDR_DQ14 C3
DQU0 VSSQ_2
D1 B8 G1 D7 B9
B13 DQU6 VSSQ_8 C8
DQU1 VSSQ_3
D8 M1_DDR_DQ30 DQU6 VSSQ_8
C3
DQU0
DQU1
VSSQ_2
VSSQ_3
D1
M1_DDR_DQ14 A3 G9 C2
DQU2 VSSQ_4
E2
A3 G9
C8
DQU2 VSSQ_4
D8
M1_DDR_DQ14 M1_DDR_DQ15 DQU7 VSSQ_9 A7
DQU3 VSSQ_5
E8
M1_DDR_DQ31
C2
DQU3 VSSQ_5
E2
C17 A2
DQU4 VSSQ_6
F9 DQU7 VSSQ_9 A7
DQU4 VSSQ_6
E8
M1_DDR_DQ15 M1_DDR_DQ15 B8
DQU5
DQU6
VSSQ_7
VSSQ_8
G1
A2
B8
DQU5 VSSQ_7
F9
G1
B9 A3
DQU7 VSSQ_9
G9
A3
DQU6 VSSQ_8
G9
M1_DDR_DQ16 M1_DDR_DQ16 DQU7 VSSQ_9
C3
M1_DDR_DQ17 M1_DDR_DQ17
C10
M1_DDR_DQ18 M1_DDR_DQ18
B2
M1_DDR_DQ19 M1_DDR_DQ19
A10
M1_DDR_DQ20 M1_DDR_DQ20
A2
M1_DDR_DQ21 M1_DDR_DQ21
B10
M1_DDR_DQ22 M1_DDR_DQ22
C2
M1_DDR_DQ23 M1_DDR_DQ23
B3
M1_DDR_DQ24 M1_DDR_DQ24
B8
M1_DDR_DQ25 M1_DDR_DQ25
C4
M1_DDR_DQ26 M1_DDR_DQ26
C9
M1_DDR_DQ27 M1_DDR_DQ27
C5
M1_DDR_DQ28 M1_DDR_DQ28
A8
M1_DDR_DQ29 M1_DDR_DQ29
B4
M1_DDR_DQ30 M1_DDR_DQ30
C8
M1_DDR_DQ31 M1_DDR_DQ31
D5
M1_RET DDR_RET
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H005-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012-09-14
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC100
LG1210D-B0(H15D-B0)
N5
M2_DDR_A0 M2_DDR_A0
U5 H15_DDR_Hynix_29n
M2_DDR_A1 M2_DDR_A1 H15_DDR_Hynix_29n
L5
M2_DDR_A2 M2_DDR_A2 IC600 IC602
J5 M2_DDR_VREFCA M2_1_DDR_VREFCA
M2_DDR_A3 M2_DDR_A3 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC
W4
M2_DDR_A4 M2_DDR_A4
K4
M2_DDR_A5 M2_DDR_A5 DDR3 M2_1_DDR_VREFDQ
W5 M2_DDR_VREFDQ DDR3
M2_DDR_A6 M2_DDR_A6 N3 4Gbit M8
K5 M2_DDR_A0 A0 VREFCA N3 M8
M2_DDR_A7 M2_DDR_A7 P7 (x16) M2_DDR_A0 A0 4Gbit VREFCA
V4 M2_DDR_A1 A1 P7
M2_DDR_A8 M2_DDR_A8 P3 M2_DDR_A1 A1 (x16)
M5 M2_DDR_A2 A2 P3
M2_DDR_A9 M2_DDR_A9 N2 H1 M2_DDR_A2 A2
Y4 M2_DDR_A3 A3 VREFDQ N2 H1
M2_DDR_A10 M2_DDR_A10 P8 M2_DDR_A3 A3 VREFDQ
U4 M2_DDR_A4 A4 P8
M2_DDR_A11 M2_DDR_A11 P2 +1.5V_DDR M2_DDR_A4 A4
T4 M2_DDR_A5 A5 R613 P2 +1.5V_DDR
M2_DDR_A12 M2_DDR_A12 R8 L8 M2_DDR_A5 A5 R615
M4 M2_DDR_A6 A6 ZQ R8 L8
M2_DDR_A13 M2_DDR_A13 R2 240 M2_DDR_A6 A6 ZQ
V5 M2_DDR_A7 A7 1% R2 240
M2_DDR_A14 M2_DDR_A14 T8 M2_DDR_A7 A7
H5 M2_DDR_A8 A8 T8 1%
M2_DDR_A15/M2_DDR_CS1 R3 B2 M2_DDR_A8 A8
M2_DDR_A9 A9 VDD_1 R3 B2
L7 D9 M2_DDR_A9 A9 VDD_1
J4 M2_DDR_A10 A10/AP VDD_2 L7 D9
M2_DDR_BA0 M2_DDR_BA0 R7 G7 M2_DDR_A10 A10/AP VDD_2
Y5 M2_DDR_A11 A11 VDD_3 R7 G7
M2_DDR_BA1 M2_DDR_BA1 N7 K2 M2_DDR_A11 A11 VDD_3
N4 M2_D_CLK M2_U_CLK M2_DDR_A12 A12/BC VDD_4 N7 K2
M2_DDR_BA2 M2_DDR_BA2 T3 K8 M2_DDR_A12 A12/BC VDD_4
M2_DDR_A13 A13 VDD_5 T3 K8
T7 N1 M2_DDR_A13
100
100
A13 VDD_5
R603
R609
V3 M2_DDR_A14 A14 VDD_6 T7 N1
M2_DDR_U_CLK M2_U_CLK M7 N9 M2_DDR_A14 A14 VDD_6
V2 NC_5 VDD_7 M7 N9
M2_DDR_U_CLKN M2_U_CLKN R1 NC_5 VDD_7
J3 VDD_8 R1
M2_DDR_D_CLK M2_D_CLK M2_D_CLKN M2_U_CLKN M2 R9 VDD_8
J2 M2_DDR_BA0 BA0 VDD_9 M2 R9
M2_DDR_D_CLKN M2_D_CLKN N8 M2_DDR_BA0 BA0 VDD_9
T5 M2_DDR_BA1 BA1 N8
M2_DDR_CKE M2_DDR_CKE M3 M2_DDR_BA1 BA1
R5 M2_DDR_BA2 BA2 M3
M2_DDR_CS0 M2_CS0_N A1 M2_DDR_BA2 BA2
VDDQ_1 A1
J7 A8 VDDQ_1
G5 M2_D_CLK CK VDDQ_2 J7 A8
M2_DDR_ODT M2_DDR_ODT K7 C1 M2_U_CLK CK VDDQ_2
G4 M2_D_CLKN CK VDDQ_3 K7 C1
M2_DDR_RASN M2_DDR_RASN K9 C9 M2_U_CLKN CK VDDQ_3
H4 +1.5V_DDR +1.5V_DDR M2_DDR_CKE CKE VDDQ_4 K9 C9
M2_DDR_CASN M2_DDR_CASN D2 M2_DDR_CKE CKE VDDQ_4
R4 VDDQ_5 D2
M2_DDR_WEN M2_DDR_WEN L2 E9 VDDQ_5
M2_1_DDR_VREFCA M2_CS0_N CS VDDQ_6 L2 E9
M2_DDR_VREFCA K1 F1 M2_CS0_N CS VDDQ_6
L4 M2_DDR_ODT ODT VDDQ_7 K1 F1
M2_DDR_RESET_N M2_DDR_RESET_N J3 H2 C600 0.1uF M2_DDR_ODT ODT VDDQ_7
M2_DDR_RASN J3 H2 0.1uF
R604
R610
1K 1%
1K 1%
RAS VDDQ_8 C602
K3 H9 C601 0.1uF M2_DDR_RASN RAS VDDQ_8
D3 240 R617 M2_DDR_CASN CAS VDDQ_9 K3 H9 C603 0.1uF
M2_DDR_ZQCAL L3 M2_DDR_CASN CAS VDDQ_9
1% M2_DDR_WEN WE L3
J1 M2_DDR_WEN WE
H2 NC_1 J1
M2_DDR_DQS0 M2_DDR_DQS0 T2 J9 NC_1
H3 M2_DDR_RESET_N RESET NC_2 T2 J9
1%
1%
M2_DDR_DQS_N0 M2_DDR_DQS_N0 L1 M2_DDR_RESET_N RESET NC_2
K2 L1
R605
R611
NC_3
M2_DDR_DQS1 M2_DDR_DQS1 L9 NC_3
K1 NC_4 L9
M2_DDR_DQS_N1 F3
1K
1K
M2_DDR_DQS_N1 NC_4
U2 M2_DDR_DQS0 DQSL F3
M2_DDR_DQS2 M2_DDR_DQS2 G3 M2_DDR_DQS2 DQSL
U3 M2_DDR_DQS_N0 DQSL G3
M2_DDR_DQS_N2 M2_DDR_DQS_N2 M2_DDR_DQS_N2 DQSL
W2
M2_DDR_DQS3 M2_DDR_DQS3 C7 A9
W1 M2_DDR_DQS1 DQSU VSS_1 C7 A9
M2_DDR_DQS_N3 M2_DDR_DQS_N3 B7 B3 M2_DDR_DQS3 DQSU VSS_1
M2_DDR_DQS_N1 DQSU VSS_2 B7 B3
E1 M2_DDR_DQS_N3 DQSU VSS_2
L1 VSS_3 E1
M2_DDR_DM0 M2_DDR_DM0 E7 G8 VSS_3
H1 M2_DDR_DM0 DML VSS_4 E7 G8
M2_DDR_DM1 M2_DDR_DM1 D3 J2 M2_DDR_DM2 DML VSS_4
Y1 M2_DDR_DM1 DMU VSS_5 D3 J2
M2_DDR_DM2 M2_DDR_DM2 J8 M2_DDR_DM3 DMU VSS_5
U1 VSS_6 J8
M2_DDR_DM3 M2_DDR_DM3 E3 M1 VSS_6
M2_DDR_DQ0 DQL0 VSS_7 E3 M1
F7 M9 M2_DDR_DQ16 DQL0 VSS_7
F2 M2_DDR_DQ1 DQL1 VSS_8 F7 M9
M2_DDR_DQ0 M2_DDR_DQ0 F2 P1 M2_DDR_DQ17 DQL1 VSS_8
N2 M2_DDR_DQ2 DQL2 VSS_9 F2 P1
M2_DDR_DQ1 M2_DDR_DQ1 F8 P9 M2_DDR_DQ18 DQL2 VSS_9
E3 +1.5V_DDR +1.5V_DDR M2_DDR_DQ3 DQL3 VSS_10 F8 P9
M2_DDR_DQ2 M2_DDR_DQ2 H3 T1 M2_DDR_DQ19 DQL3 VSS_10
M3 M2_DDR_DQ4 DQL4 VSS_11 H3 T1
M2_DDR_DQ3 M2_DDR_DQ3 M2_1_DDR_VREFDQ H8 T9 M2_DDR_DQ20 DQL4 VSS_11
E1 M2_DDR_VREFDQ M2_DDR_DQ5 DQL5 VSS_12 H8 T9
M2_DDR_DQ4 M2_DDR_DQ4 G2 M2_DDR_DQ21 DQL5 VSS_12
N1 M2_DDR_DQ6 DQL6 G2
M2_DDR_DQ5 H7 M2_DDR_DQ22
R600
R606
M2_DDR_DQ5 DQL6
1K 1%
1K 1%
E2 M2_DDR_DQ7 DQL7 H7
M2_DDR_DQ6 M2_DDR_DQ6 B1 M2_DDR_DQ23 DQL7
N3 VSSQ_1 B1
M2_DDR_DQ7 M2_DDR_DQ7 D7 B9 VSSQ_1
M2 M2_DDR_DQ8 DQU0 VSSQ_2 D7 B9
M2_DDR_DQ8 M2_DDR_DQ8 C3 D1 M2_DDR_DQ24 DQU0 VSSQ_2
G2 M2_DDR_DQ9 DQU1 VSSQ_3 C3 D1
M2_DDR_DQ9 M2_DDR_DQ9 C8 D8 M2_DDR_DQ25 DQU1 VSSQ_3
1%
1%
L3 M2_DDR_DQ10 DQU2 VSSQ_4 C8 D8
M2_DDR_DQ10 C2 E2 M2_DDR_DQ26
R601
R607
M2_DDR_DQ10 DQU2 VSSQ_4
F3 M2_DDR_DQ11 DQU3 VSSQ_5 C2 E2
M2_DDR_DQ11 M2_DDR_DQ11 A7 E8 M2_DDR_DQ27 DQU3 VSSQ_5
K3 M2_DDR_DQ12 DQU4 VSSQ_6 A7 E8
1K
1K
M2_DDR_DQ12 M2_DDR_DQ12 A2 F9 M2_DDR_DQ28 DQU4 VSSQ_6
G1 M2_DDR_DQ13 DQU5 VSSQ_7 A2 F9
M2_DDR_DQ13 M2_DDR_DQ13 B8 G1 M2_DDR_DQ29 DQU5 VSSQ_7
L2 M2_DDR_DQ14 DQU6 VSSQ_8 B8 G1
M2_DDR_DQ14 M2_DDR_DQ14 A3 G9 M2_DDR_DQ30 DQU6 VSSQ_8
G3 M2_DDR_DQ15 DQU7 VSSQ_9 A3 G9
M2_DDR_DQ15 M2_DDR_DQ15 M2_DDR_DQ31 DQU7 VSSQ_9
R2
M2_DDR_DQ16 M2_DDR_DQ16
AA3
M2_DDR_DQ17 M2_DDR_DQ17
P3
M2_DDR_DQ18 M2_DDR_DQ18
AB2
M2_DDR_DQ19 M2_DDR_DQ19
P1
M2_DDR_DQ20 M2_DDR_DQ20
AB1
M2_DDR_DQ21 M2_DDR_DQ21
P2
M2_DDR_DQ22 M2_DDR_DQ22 +1.5V_DDR
AB3
M2_DDR_DQ23 M2_DDR_DQ23
AA2
M2_DDR_DQ24 M2_DDR_DQ24
T2
M2_DDR_DQ25 M2_DDR_DQ25 IC602-*1
Y3 H15_DDR_Hynix_25n H5TQ4G63CFR_RDC
M2_DDR_DQ26 M2_DDR_DQ26 IC600-*1
R3 H5TQ4G63CFR_RDC H15_DDR_Hynix_25n
N3 M8
M2_DDR_DQ27 M2_DDR_DQ27 P7
A0 VREFCA
W3 C604 C605 C606 N3 M8
P3
A1
A2
M2_DDR_DQ28 M2_DDR_DQ28 0.1uF 0.1uF 0.1uF C607 C608 C609 C610 P7
A0 VREFCA N2
P8
A3 VREFDQ
H1
T1 16V 16V 4.7uF 4.7uF 4.7uF 4.7uF P3
A1
A4
M2_DDR_DQ29 M2_DDR_DQ29 16V N2
A2
A3 VREFDQ
H1
P2
R8
A5
L8
P8
Y2 10V 10V 10V 10V P2
A4 R2
A6
A7
ZQ
M2_DDR_DQ30 M2_DDR_DQ30 R8
A5
L8
T8
R3
A8
B2
T3 R2
A6
A7
ZQ
L7
A9 VDD_1
D9
M2_DDR_DQ31 M2_DDR_DQ31 T8
R3
A8
B2
R7
A10/AP VDD_2
G7
A11 VDD_3
A9 VDD_1 N7 K2
L7 D9 A12/BC VDD_4
A10/AP VDD_2 T3 K8
R7 G7 A13 VDD_5
T7 N1
AA4 Place PCB TOP FOR APPLYING EMI SIMULATION RESULT N7
A11
A12/BC
VDD_3
VDD_4
K2
M7
A14 VDD_6
N9
M2_RET DDR_RET T3
T7
A13 VDD_5
K8
N1
NC_5 VDD_7
VDD_8
R1
A14 VDD_6 M2 R9
M7 N9 BA0 VDD_9
Place M2 POWER PLANE NC_5 VDD_7
VDD_8
R1
N8
M3
BA1
M2 R9 BA2
BA0 VDD_9 A1
N8 VDDQ_1
BA1 J7 A8
M3 CK VDDQ_2
BA2 K7 C1
A1 CK VDDQ_3
VDDQ_1 K9 C9
J7 A8 CKE VDDQ_4
CK VDDQ_2 D2
K7 C1 VDDQ_5
CK VDDQ_3 L2 E9
K9 C9 CS VDDQ_6
CKE VDDQ_4 K1 F1
D2 ODT VDDQ_7
VDDQ_5 J3 H2
L2 E9 RAS VDDQ_8
CS VDDQ_6 K3 H9
K1 F1 CAS VDDQ_9
ODT VDDQ_7 L3
J3 H2 WE
RAS VDDQ_8 J1
K3 H9 NC_1
CAS VDDQ_9 T2 J9
L3 RESET NC_2
WE L1
J1 NC_3
NC_1 L9
+1.5V_DDR T2
RESET NC_2
J9
L1
F3
DQSL
NC_4
NC_3 G3
L9 DQSL
NC_4
F3
DQSL C7 A9
G3 DQSU VSS_1
DQSL B7 B3
DQSU VSS_2
E1
C7 A9 VSS_3
DQSU VSS_1 E7 G8
B7 B3 DML VSS_4
DQSU VSS_2 D3 J2
E1 DMU VSS_5
VSS_3 J8
E7 G8 VSS_6
DML VSS_4 E3 M1
D3 J2 DQL0 VSS_7
F7 M9
C618 C617 C614 C615 C616 C611 C612 C613 C619 C620 C621 C622 DMU VSS_5
VSS_6
J8
F2
DQL1 VSS_8
P1
E3 M1 DQL2 VSS_9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF F7
DQL0
DQL1
VSS_7
VSS_8
M9
F8
H3
DQL3 VSS_10
P9
T1
F2 P1 DQL4 VSS_11
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V F8
DQL2
DQL3
VSS_9
VSS_10
P9
H8
G2
DQL5 VSS_12
T9
H3 T1 DQL6
DQL4 VSS_11 H7
H8 T9 DQL7
DQL5 VSS_12 B1
G2 VSSQ_1
DQL6 D7 B9
H7 DQU0 VSSQ_2
DQL7 C3 D1
B1 DQU1 VSSQ_3
VSSQ_1 C8 D8
D7 B9 DQU2 VSSQ_4
DQU0 VSSQ_2 C2 E2
C3 D1 DQU3 VSSQ_5
DQU1 VSSQ_3 A7 E8
C8 D8 DQU4 VSSQ_6
DQU2 VSSQ_4 A2 F9
C2 E2 DQU5 VSSQ_7
DQU3 VSSQ_5 B8 G1
A7 E8 DQU6 VSSQ_8
DQU4 VSSQ_6 A3 G9
A2 F9 DQU7 VSSQ_9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+5V_CI_ON
C702 C703 CI_DATA[0-7]
0.1uF 4.7uF
10V CI
CI JK700
CI
10125901-115LF
/PCM_CE1
35 1
R716 100 36 2 CI_DATA[3]
/CI_CD1
CI 37 3 CI_DATA[4]
CI_TS_DATA[3]
38 4 CI_DATA[5]
CI_TS_DATA[4]
39 5 CI_DATA[6]
CI_DATA[0-7]
CI_TS_DATA[5] CI
40 6 CI_DATA[7]
CI_TS_DATA[6] AR712
CI R721 33 CI_DATA[0] 33 EB_DATA[0]
CI_TS_DATA[7] 41 7
CI_ADDR[10] CI_DATA[1] EB_DATA[1]
/PCM_CE2 42 8 CI_ADDR[10]
/PCM_IORD CI_DATA[2] EB_DATA[2]
/PCM_IOWR 43 9 /PCM_OE
CI_ADDR[11] CI_DATA[3] EB_DATA[3]
44 10 CI_ADDR[11] +5V_CI_ON
CI_IN_TS_DATA[0-7] 45 11 CI_ADDR[9]
EB_DATA[0-7]
CI_ADDR[9]
46 12 CI_ADDR[8] CI
CI_ADDR[8]
CI_IN_TS_DATA[0] CI_ADDR[13] R723 CI_DATA[4] AR713 EB_DATA[4]
47 13 CI_ADDR[13] 33
10K
CI_IN_TS_DATA[1] 48 14 CI_ADDR[14] CI_DATA[5] EB_DATA[5]
CI_ADDR[14] CI
CI_IN_TS_DATA[2] 49 15 CI_DATA[6] EB_DATA[6]
/PCM_WE
CI_IN_TS_DATA[3] 50 16 CI_DATA[7] EB_DATA[7]
/PCM_IRQA
51 17 C706 0.1uF C707
CI EB_DATA[0-7]
CI 0.1uF
+5V_CI_ON 52 18 16V
CI_IN_TS_DATA[4] 53 19
CI_DATA[0-7]
CI_IN_TS_DATA[5] 54 20
CI_IN_TS_DATA[6] 55 21 CI_ADDR[12]
R709 CI_ADDR[12]
10K CI_IN_TS_DATA[7] 56 22 CI_ADDR[7]
CI_ADDR[7]
CI 57 23 CI_ADDR[6]
CI_TS_CLK CI_ADDR[6]
R701 33 CI 58 24 CI_ADDR[5]
PCM_RESET CI_ADDR[5]
R702 33 CI 59 25 CI_ADDR[4]
/PCM_WAIT CI_ADDR[4]
60 26 CI_ADDR[3]
CI_ADDR[3]
/PCM_REG 61 27 CI_ADDR[2]
CI_ADDR[2]
CI_TS_VAL 62 28 CI_ADDR[1]
CI_ADDR[1]
CI_TS_SYNC 63 29 CI_ADDR[0]
CI_ADDR[0]
64 30 CI_DATA[0]
CI_TS_DATA[0]
65 31 CI_DATA[1]
CI_TS_DATA[1]
66 32 CI_DATA[2]
CI_TS_DATA[2]
/CI_CD2 R717 CI 100 67 33
68 34
/PCM_CE2
G2 69 G1
CI_IN_TS_VAL
CI_IN_TS_CLK
CI_IN_TS_SYNC
C705
12pF
50V
OPT
TPO_DATA[0-7] CI
AR701
TPO_DATA[0] 33
CI_IN_TS_DATA[0]
TPO_DATA[1]
CI_IN_TS_DATA[1]
TPO_DATA[2]
CI_IN_TS_DATA[2]
TPO_DATA[3]
CI_IN_TS_DATA[3]
TPO_DATA[4]
CI_IN_TS_DATA[4]
TPO_DATA[5]
CI_IN_TS_DATA[5]
TPO_DATA[6]
CI_IN_TS_DATA[6]
TPO_DATA[7]
CI_IN_TS_DATA[7]
AR706 CI
33 CI
AR707
CI 33
AR705 CI_ADDR[3] EB_ADDR[3]
33 CI_ADDR[2] EB_ADDR[2]
TPO_CLK CI_IN_TS_CLK
TPO_SOP CI_ADDR[1] EB_ADDR[1]
CI_IN_TS_SYNC
TPO_VAL CI_IN_TS_VAL CI_ADDR[0] EB_ADDR[0]
CI
AR708 CI
33
CI_ADDR[4] EB_ADDR[4] AR710
33
CI_ADDR[5] EB_ADDR[5] /PCM_OE EB_OE_N
CI_ADDR[6] EB_ADDR[6] /PCM_WE EB_WE_N
CI_ADDR[7] EB_ADDR[7] /PCM_IORD EB_BE_N1
/PCM_IOWR EB_BE_N0
+5V_NORMAL
CI
AR709
33
CI_ADDR[9] EB_ADDR[9]
CI_ADDR[8] EB_ADDR[8]
CI_ADDR[13] EB_ADDR[13]
R703
EB_ADDR[14]
R705
AR702 CI_ADDR[14]
10K
10K
/PCM_WAIT CAM_WAIT_N CI
/PCM_IRQA CAM_IREQ_N AR711
/CI_CD2 33
CAM_CD2_N CI_ADDR[12] EB_ADDR[12]
100
/CI_CD1
CAM_CD1_N CI_ADDR[10] EB_ADDR[10]
CI_ADDR[11] EB_ADDR[11]
CI
CI /PCM_REG CAM_REG_N
C700 C701
0.1uF 0.1uF
16V 16V AR703 CI
CI_TS_CLK TPI_CLK
CI_TS_VAL TPI_VAL C704
100
CI_TS_SYNC TPI_SOP 12pF
50V
OPT
AR704 CI
CI_TS_DATA[7] TPI_DATA[7]
CI_TS_DATA[6] TPI_DATA[6]
CI_TS_DATA[5] TPI_DATA[5]
100 CI POWER ENABLE CONTROL
CI_TS_DATA[4] TPI_DATA[4]
IC700
+5V_NORMAL AP2151WG-7 +5V_CI_ON
AR700 CI
CI_TS_DATA[3] TPI_DATA[3] CI IN OUT
5 1
CI_TS_DATA[2] TPI_DATA[2] C709 CI
CI_TS_DATA[1] TPI_DATA[1] 0.1uF C708
100 50V GND
CI_TS_DATA[0] TPI_DATA[0] 2 1uF
CI R706
25V
CI 10K
R704
100 EN FLG CI
PCM_5V_CTL 4 3
R700
10K
CI
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H007-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012-10-20
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCIA
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA27
AA33
AA34
AA35
AA36
AA37
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB27
AB33
AB34
AB36
AB37
AC15
AC16
AC18
AC19
AC20
AC21
AC27
AC34
AC35
AC36
AD15
AD18
AD19
AD20
AD21
AD27
AD28
AD34
AD36
AE15
AE27
AE34
AE35
AE36
AF15
AF27
AF34
AF35
AF36
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG34
AG35
AG36
AG37
AH14
AH16
AH17
AH21
AH24
AH27
AH28
AH34
AH35
AJ33
AJ34
AJ35
AK33
AK34
AK35
AL33
AL34
AL35
AM33
AM34
AM35
AN11
AN12
AN13
AN14
AB4
AB5
AB6
AB7
AB8
AC3
AC4
AC8
AD8
AD9
AE8
AE9
AF8
AF9
AG8
AH8
AH9
AJ8
AJ9
AK8
AK9
AL8
AL9
AM8
AN3
AN4
AN6
AN7
AN8
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264
GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272
GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293
GND_294
GND_295
GND_296
GND_297
GND_298
GND_299
GND_300
GND_301
GND_302
GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329
GND_330
GND_331
GND_332
GND_333
GND_334
GND_335
GND_336
GND_337
GND_338
GND_339
GND_340
GND_341
GND_342
GND_343
GND_344
GND_345
GND_346
GND_347
GND_348
GND_349
GND_350
GND_351
GND_352
GND_353
GND_354
GND_355
GND_356
GND_357
GND_358
GND_359
GND_360
B20 AN15
GND_1 GND_361
B21 AN19
GND_2 GND_362
C20 AN20
GND_3 GND_363
C21 AN21
GND_4 GND_364
D20 AN24
GND_5 GND_365
E4 AN25
GND_6 GND_366
E20 AN26
GND_7 GND_367
E21 AN27
GND_8 GND_368
F4 AN28
GND_9 GND_369
F5 AN29
GND_10 GND_370
F7 AN30
GND_11 GND_371
F8 AN31
GND_12 GND_372
F9 AN33
GND_13 GND_373
F10 AN34
GND_14 GND_374
F11 AN35
GND_15 GND_375
F13 AP8
GND_16 GND_376
F14 AP11
GND_17 GND_377
F15 AP12
GND_18 GND_378
F16 AP13
GND_19 GND_379
F17 AP14
GND_20 GND_380
F18 AP15
GND_21 GND_381
F19 AP16
GND_22 GND_382
F20 AP17
GND_23 GND_383
F21 AP18
GND_24 GND_384
F22 AP19
GND_25 GND_385
F23 AP20
GND_26 GND_386
F24 AP21
GND_27 GND_387
F25 AP22
GND_28 GND_388
F26 AP23
GND_29 GND_389
F27 AP24
GND_30 GND_390
F29 AP25
GND_31 GND_391
F30 AP26
GND_32 GND_392
F31 AP27
GND_33 GND_393
F32 AP28
GND_34 GND_394
F33 AP29
GND_35 GND_395
F34 AP30
GND_36 GND_396
F35 AP31
GND_37 GND_397
G6 AP33
GND_38 GND_398
G17 AP34
GND_39 GND_399
G18 AP35
GND_40 GND_400
G19 AR8
GND_41 GND_401
G20 AR10
GND_42 GND_402
G21 AR11
GND_43 GND_403
G22 AR12
GND_44 GND_404
G32 AR13
GND_45 GND_405
G33 AR14
GND_46 GND_406
G34 AR15
GND_47 GND_407
IC100
H6 AR16
GND_48 GND_408
H7 AR17
GND_49 GND_409
H9 AR18
GND_50 GND_410
H10 AR19
GND_51 GND_411
H11 AR20
GND_52 GND_412
H12 AR21
GND_53 GND_413
H13 AR22
GND_54 GND_414
H14 AR23
GND_55 GND_415
H15 AR24
GND_56 GND_416
H16 AR25
GND_57 GND_417
LG1210D-B0(H15D-B0)
H17 AR26
GND_58 GND_418
H18 AR27
GND_59 GND_419
H19 AR28
GND_60 GND_420
H20 AR29
GND_61 GND_421
H21 AR30
GND_62 GND_422
H22 AR31
GND_63 GND_423
H23 AR32
GND_64 GND_424
H24 AR34
GND_65 GND_425
H25 AR35
GND_66 GND_426
H26 AT9
GND_67 GND_427
H27 AT10
GND_68 GND_428
H28 AT11
GND_69 GND_429
H29 AT12
GND_70 GND_430
H30 AT13
GND_71 GND_431
H31 AT16
GND_72 GND_432
H32 AT17
GND_73 GND_433
H33 AT20
GND_74 GND_434
H35 AT21
GND_75 GND_435
H36 AT22
GND_76 GND_436
J6 AT23
GND_77 GND_437
J7 AT24
GND_78 GND_438
J8 AT25
GND_79 GND_439
J10 AT26
GND_80 GND_440
J11 AT27
GND_81 GND_441
J12 AT28
GND_82 GND_442
J13 AT29
GND_83 GND_443
J14 AT30
GND_84 GND_444
J15 AT31
GND_85 GND_445
J16 AT32
GND_86 GND_446
J17 AT33
GND_87 GND_447
J18 AT35
GND_88 GND_448
J19 AU6
GND_89 GND_449
J20 AU8
GND_90 GND_450
J21 AU9
GND_91 GND_451
J22 AU10
GND_92 GND_452
J23 AU11
GND_93 GND_453
J24 AU12
GND_94 GND_454
J25 AU13
GND_95 GND_455
J26 AU17
GND_96 GND_456
J27 AU21
GND_97 GND_457
J28 AU22
GND_98 GND_458
J29 AU23
GND_99 GND_459
J32 AU24
GND_100 GND_460
J34 AU25
GND_101 GND_461
J35 AU26
GND_102 GND_462
J36 AU27
GND_103 GND_463
K6 AU28
GND_104 GND_464
K8 AU29
GND_105 GND_465
K9 AU30
GND_106 GND_466
K11 AU31
GND_107 GND_467
K12 AU32
GND_108 GND_468
K13 AU33
GND_109 GND_469
K14 AU34
GND_110 GND_470
K15 AV5
GND_111 GND_471
K16 AV8
GND_112 GND_472
K17 AV14
GND_113 GND_473
K18 AV15
GND_114 GND_474
K19 AV16
GND_115 GND_475
K20 AW16
GND_116 GND_476
K21 BA30
GND_117 GND_477
K22 BB21
GND_118 GND_478
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
GND_239
K23
K24
K25
K29
K33
K34
K35
K36
L6
L8
L9
L33
L34
L35
L36
M6
M8
M9
M33
M34
M35
M36
N6
N8
N9
N33
N34
N35
N36
P8
P9
P33
P34
P35
P36
R6
R8
R9
R14
R15
R16
R17
R18
R19
R20
R21
R22
R24
R28
R33
R34
R35
R36
T6
T8
T9
T14
T15
T20
T21
T22
T23
T24
T25
T26
T27
T33
T34
T36
U6
U8
U9
U14
U15
U16
U27
U33
U34
U36
V6
V8
V9
V14
V15
V27
V28
V34
V35
V36
W6
W7
W8
W9
W14
W15
W18
W19
W20
W27
W28
W34
W35
W36
Y6
Y7
Y8
Y9
Y14
Y15
Y18
Y19
Y20
Y27
Y34
Y35
Y36
AA5
AA6
AA7
AA8
AA9
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-03-24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LG1210D GND
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
CPU / GPU IC2200
GPU_0.95V
R2218-*1
SN1406033 R2
1%
1/16W
1/16W
R2218
MAX 5.9A
22K
18K
+0.9V H15D Core
1%
R2202
POWER_ON/OFF2_310K EN1 FB2 GPU_1.05V
1 32
THERMAL
C2203 R2200
33
0.01uF EN2 VOUT2 0 C2223
+12V 25V 2 31
1%
1/16W
R2219 82pF
1/16W 50V VDD09_GPU
5% 13K
PGND2_1 BST2 C2214
3 30
R2230
L2200 0.047uF L2203 R1 10K
PGND2_2 LX2_2 3.3uH
4 29 R2233
R2236
24.9K
1/16W
39K
R1
1%
PVIN2_1 LX2_1 1/16W
5 28
C2230
5%
1%
1/16W
91K
OPT ZD2202
16V
0.1uF
C2232 C2234
R2232
C2258 C2259
2.5V
22uF 22uF 22uF 150uF
C2242
[EP]
GND2
GND1
NC_3
TRIP
PVIN2_2 SS2 C2212 10V 6.3V
R2237
1/16W
6 27 10V 10V 1000pF +12V
VO
47K
50V R2
1%
1/16W
27K
0.01uF C2216 R2216
1%
POSCAP
R2231
C2200
1%
1/16W
20K
R2238
10uF ADDR COMP2
28
27
26
25
24
25V 7 26 4700pF 8.2K
C2217 1% RF 1 23 FB
THERMAL
MODE AGND 47pF PGOOD 2 22 GND L2210
8 25 29
R2224 1K EN MODE
R2211 16V 3 21
POWER_ON/OFF2_3
C2205 V7V ROSC 91K 0.1uF IC2204
9 24 VBST 4 20 VREG
4.7uF 1% C2218 R2217 TPS53513RVER
R2229
C2245 NC_1 VDD
5 19
4.7
VIN COMP1 C2241 R2222
10 23 4700pF 8.2K 2K
C2219 1% SW_1 6 18 NC_2
0.1uF 1/16W C2254 C2228 C2255
PVIN1_1 SS1 C2213 47pF SW_2 7 17 VIN_3
11 22 VDD09 16V 5% 1uF 10uF 10uF
25V 25V 25V
0.01uF VDD09_CPU L2208 SW_3 8 16 VIN_2
PVIN1_2
12 21
LX1_2 1.0uH
SW_4 9
8A 15 VIN_1
+3.3V_NORMAL L2204
10
11
12
13
14
C2201
R2225
1/10W
AR2202 PGND1_1 LX1_1 3.3uH
3.3K 10uF
13 20
3.3
1/16W 25V
5%
C2248
C2238
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
C2224 82pF
22uF
C2226
C2237
16V
0.1uF
2200pF
R1 C2231 150uF
ZD2204
PGND1_2 BST1 C2215
OPT ZD2203
C2233 C2256 C2235 50V
2.5V
14 19 0.1uF C2257
2.5V
6.3V
OPT
10V
22uF 22uF 22uF 150uF C2244
AR2200 0.047uF 16V
1%
1/16W
R2201 R2220 10V 10V 10V 6.3V 470pF
33 POSCAP
1/16W SDA VOUT1 0 50V
15 18 13K
PMS_SDA
1/16W POSCAP
SCL FB1 5%
PMS_SCL 16 17
Vout=0.6*(1+R1/R2)
1%
1/16W
R2221
18K
R2
VoutGPU=0.6*(1+R1/R2) = 0.9V
VoutCPU=0.6*(1+R1/R2) = 1.1V
+1.8V
+12V IC2203 VDD18
LG1154A
+1.0V_VDD +3.5V_ST AP2132MP-2.5TRG1 [EP]
R2234
L2201 33K
1 8 1% R2
BLM18PG121SN1D +1.0V_VDD
THERMAL
PG GND
R2226
R2235
10K
9
2 7 R1
68K
1%
POWER_ON/OFF1 EN ADJ
C2202
3 6
10uF ZD2205 C2239
25V IC2201 5V 10uF VIN VOUT
BD9D320EFJ [EP]FIN 10V +5V_NORMAL 2A
ZD2200
4 5
2.5V
OPT ZD2206
2.5V
VCTRL NC C2250
OPT
R2206 10uF
POWER_ON/OFF2_3 10K EN VIN EAN61387601
1 8 10V
16V
THERMAL
C2240
1% R22030.1uF
C2220 1uF
FB BOOT 0
9
2 7 10V
PS064T-2R2MS
R2205 L2205
R1 2.2uH
11K VREG SW
3 6
C2206
100pF
50V
SS GND C2222
R2207
4
3A 5
22uF
10V
C2225
22uF
10V
C2260
22uF
10V Vout=0.6*(1+R1/R2)
33K C2208 C2209
1uF 3300pF
10V 50V
1%
Switching freq: 700K R2
Vout=0.765*(1+R1/R2)
+12V
VDD09_DDR
+3.3V_NORMAL L2207
BLM18PG121SN1D
MAX : 500mA
VDD09_DDR
+12V
+3.3V_NORMAL
C2236
L2202 TPS54527 => development 10uF
25V IC2205
BLM18PG121SN1D
BD9D320EFJ
ZD2207
[EP]FIN
2.5V
OPT
R2227
POWER_ON/OFF2_3 10K EN VIN
C2204 1 8
10uF 16V
THERMAL
C2261 0.1uF
25V 1% C2249
1uF FB BOOT
IC2202
9
2 7 PS064T-2R2MS
TPS54527DDAR [EP]GND
ZD2201
R2223 L2209
R1
5V
6.8K VREG SW 2.2uH
R2209
OPT
3 6
10K EN VIN C2246
1 8 1uF
16V 10V
THERMAL
POWER_ON/OFF2_1 0.1uF SS GND C2251 C2253 C2252
1% VFB VBST C2221 C2243
330pF
4
3A 5
22uF 22uF 0.1uF
9
2 7 50V R2212 C2247 10V 10V 16V
PS064T-2R2MS 270K
R2208 L2206 3300pF
R1 2.2uH 50V
51K VREG5 SW 1/16W
3 6 1%
C2207 R2228 APPLYING FOR EMI SIMULATION
100pF
50V
SS GND Switching freq: 700K 33K
OPT R2210
4
5A 5 C2227
22uF
10V
C2229
22uF
10V
C2262
22uF
10V
R2 1% Vout=0.765*(1+R1/R2)
15K C2210 C2211
1uF 0.015uF
10V 50V
1%
Switching freq: 700K R2
Vout=0.765*(1+R1/R2)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LG1156 2012-12-31
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CORE POWER
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+24V
Power_DET
DCDC +18V AMP Q2302
UBW2012-121F
AON7240
PD_12V
+12V
L2301
+3.5V_ST R2332 +3.5V_ST
S_1 1 OPT 100K
PD_12V PD_3.5V PD_12V R2337
R2320 R2326 10K
S_2 2 0 IC2304
2.7K OPT
1% 5% BD48K28G
S_3 3 POWER_DET
VDD 3 2 VOUT
Q2300 C2334 1
C2318 C2326 AON7240 G 4 5 D PD_12V 0.1uF GND
10uF 10uF 2012 R2321 16V
35V 35V 1.2K
PWR_DET_MERGE
C2328 C2344
1%
1uF S_1 1 0.1uF
R2340
50V 16V
IC2302 OPTION FOR CST IDEA PD_20_24V not to RESET
0
TPS40170RGY [EP] S_2 2
+24V R2331 at 8kV ESD
100K
R2312 C2359
10K ENABLE UVLO S_3 3 PD_20_24V 0.1uF PWR_DET_SEPARATE
1 20 IC2305
POWER_ON/OFF2_3 PD_UHD_24V PD_20V PD_24V 16V
THERMAL
+18V R2324-*2 R2324-*1
5.6K
R2324
8.2K
BD48K28G
21
SYNC VIN G 4 5 D 9.1K
2 19 1% 1% 1% R2341 POWER_DET_1
VDD VOUT 0
3 2
R2327
M/S BOOT 5.1 1 PWR_DET_SEPARATE
3 18 PD_20V PD_24V C2335
PD_UHD_24V
1/10W L2302 R2325-*1 R2325 0.1uF GND
R2325-*2 24V-->3.48V
R2319 R2329 R2339 : 3.6 OHM,1/4W 10uH 1.6K 1.3K 1.5K 16V
RT HDRV 2.2 C2332 1% 1%
4 17 1% PD_20_24V 20V-->3.51V
20K 0.1uF
1% 1/10W 12V-->3.58V
3216
50V Q2301 C2346 C2355 C2356 C2357
C2323 SS SW AON7240 10uF 10uF 10uF 10uF ST_3.5V-->3.5V
5 16 25V 25V 25V 25V
R2339
25V 0.047uF
3.6
R2322
R2302 TRK VBP S_1 1
10K 6 15
1/4w
10K 1/16W
R2300 C2306 2200pF
300 1% 50V FB LDRV S_2 2 1608
7 14
C2340
R2301
1.8K 1%
C2301
0.01uF 50V
COMP
8 13
PGND S_3 3
820pF
50V DDR M0_M1_M2 +1.5V
AGND ILIM G 4 5 D
9 12
C2300 POWER_ON/OFF2_4
C2313 VDD PGOOD R2333
R2323
330pF 50V 10 11 C2336
10K
1% 100K
4.7uF LG1210D
1uF 25V 16V
C2331
0.1uF
R2303
1/16W
+3.5V_ST
1000pF
16V
C2333
330
1%
1%
1%
0.1uF
[EP]FIN
R2334
C2330
R2338
+1.5V_DDR
C2338
11K
10K
1000pF 16V
AVIN
BOOT
PGD
50V
EN
50V
L2309 L2311
UCLAMP2501T.TCT
16
15
14
13
2.2uH
PVIN_1 1 12 SW_3
ZD2302
THERMAL
PVIN_2 SW_2
C2329 2 11 C2354 C2345
2.5V
C2327 17 C2353
C2341
OPT
0.1uF 22uF 22uF 0.1uF
16V 10uF PGND_1 SW_1 16V
3 IC2303 10 150uF 10V 10V
10V
BD9A300MUV C2337 6.3V
PGND_2 4 9 SS
3A 0.01uF
5
6
7
8
50V POSCAP
APPLYING FOR EMI SIMULATION
R1
AGND
FB
ITH
MODE
1/16W 12K
R2330 C2343
R2335
1%
330K 100pF
50V
R2328
+2.5V LDO 56K
1%
C2339
4700pF
50V R2
OPT
+2.5V_Normal
+3.3V_NORMAL IC2301
1%
1/16W
13K
R2336
AP2132MP-2.5TRG1 [EP]
R2317 R2
16K
1 8 1%
Vout=0.8*(1+R1/R2)=1.538V
THERMAL
PG GND
R2306
R2318
10K
DCDC +5V MHL3.0
9
2 7
51K
R1
1%
POWER_ON/OFF2_2 EN ADJ
3 6
VIN VOUT
2A +24V
C2310
10uF
10V
+5V_NORMAL 4 5
NC
DCDC +5.0V Normal & USB
OPT ZD2300
VCTRL C2322
2.5V
EAN61387601 10uF
10V
C2311 L2306
1%
R2308180K 1%
R2304 16K 1%
1uF 120-ohm C2314 OPT R2
10V IC2307 2200pF C2315 C2316
R2307 16K
+24V 50V 100pF 0.047uF
1%
1/16W
TPS54335DDA [EP]GND
6.8K
R2314
C2358 C2349 50V 25V
C2350
0.1uF
R2309
+5V_MHL 10uF 10uF 10K
25V
35V 35V R2344
OPT BOOT RT 100K
ZD2301
1 8 C2321 C2324 C2325
OPT
22uF 10uF
RSET2
RSET1
22uF
THERMAL
L2304 1/16W
[EP]
AGND
RLIM
COMP
Vout=0.6*(1+R1/R2)=2.51V 10uH VIN EN 1% C2319 R1 10V 10V
FB
SS
L2305
9
2 7 MHL_EN 82pF
120-ohm
1%
1/16W
51K
C2347 10K 50V
R2315
C2348
28
27
26
25
24
23
22
22uF R2346
22uF PH COMP VIN_1 LX_3
10V 10V 3 6 1 21 L2307
THERMAL 4.7uH
R2345
VIN_2 2 20 LX_2
3.6K
29
GND VSENSE
4 5 C2352 VIN_3 LX_1 C2317
R1 C2307 C2308 3 19
+5V_NORMAL
R2342
1/16W
120pF
100K
10uF 10uF 0.047uF
1%
50V IC2300
1%
PGND_1 BST 25V +3.3V_NORMAL
eMMC POWER C2351
0.015uF
50V
35V
OPT
35V
PGND_2
4 18
SN1302001(TPS65286RHDR)
5 17 SW_IN2
C2320
R2343
1/16W
PGND_3 SW_IN1 1uF
18K
6 16
10V
6A
1%
V7V NFAULT1
R2313
1/16W
R2316
7 15
1/16W
100K 5%
3.3V_EMMC
100K 5%
+3.3V_NORMAL EMMC_VCCQ R2
25V
1uF
C2309
10
11
12
13
14
VDD18
8
9
MODE/SYNC
EN
SW_OUT2
SW_OUT1
SW_EN2
SW_EN1
NFAULT2
/USB_OCD1
L2300 L2303
BLM18PG121SN1D BLM18PG121SN1D Vout=0.8*(1+R1/R2)=5.24V /USB_OCD2
10K
10K
C2302 C2303 C2304 C2305 C2312
+5V_USB_2
+5V_USB_1
R2305
0.1uF 22uF 0.1uF 22uF
10K
0.0068uF
R2310
R2311
16V 10V 16V 10V 50V
USB_CTL1
USB_CTL2
POWER_ON/OFF1
Vout=0.6*(1+R1/R2)=5.1V
POWER UP SEQUENCE
5V/3.3V->2.5V->1.5V/1.1V->1.0V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES LG1154D BSD-NC4_H023-HD
: 3.3V->2.5V->1.5V->1.1V
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LG1154AN : 3.3V->2.5V->1.0V
LG1154 2012-12-07
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+12V
MODULE_UPPER_79
+3.5V_ST
MMBT3906(NXP)
Upper 79"
PANEL_POWER TYP 6000mA
L2605 L2606
MLB-201209-0120P-N2
MLB-201209-0120P-N2
10K
R2601
1
PANEL_VCC
R2600
Q2600
RL_ON 10K C2607
0.1uF Q2602
2
AO4447A
+3.3V_NORMAL 25V
3
S_1 D_4
1 8
R2603 S_2 D_3
1K R2606 C2609 C2610 2 7
25 10K 10uF 10uF S_3 D_2
3 6
R2602 25V 25V R2608 R2609 C2608 C2611 C2617
PWR ON 23 INV_CTL 100 INV_CTL G D_1 2K 2K 10uF 10uF 0.1uF
24 4 5
L2600 OPT OPT 25V 25V 25V
+3.5V_ST UBW2012-121F PDIM#1 21 22 PDIM#2
PWM_DIM PWM_DIM2 51pin_12V
51pin_12V
3.5V 19 20 GND R2607
+12V
C2600 3.5V 17 18 3.5V 1.8K
L2602
0.1uF GND 15 16 GND
UBW2012-121F
16V 12V 13 12V C
14 R2605
+12V L2601 +24V 10K
12V 11 12 12V B Q2601
UBW2012-121F C2612 C2613 PANEL_CTL 1st :EBK61012601(NXP)
12V 9 GND 0.1uF L2603 MMBT3904(NXP)
10 0.1uF 2nd :0TRKE80046A(KEC)
50V UBW2012-121F PANEL_CTL_TR_NXP
GND 7 8 24V 50V E
+24V C2601
0.1uF 24V 5 6 24V
L2604 C2604 C2614 C
50V UBW2012-121F 24V 3 4 24V 0.1uF 10uF
GND 1 2 GND 50V 35V B Q2601-*1
2N3904S
C2615 C2616 PANEL_CTL_FET_KEC
10uF 0.1uF E
35V 50V
SMAW200-H24S5
P2600
For Protecting flowing different current
Because of each Bead’s DCR
’14 UHD POWER Module dc current(Y14)
84":4400~5720mA
TCON_PWR_5pin_Wafer 79":4260~5538mA
P2601
20037WR-05A00
T-con power 65":3850~5000mA
1
2
MODULE_UPPER_79 PANEL_VCC
Upper 79"
3
L2607
MLB-201209-0120P-N2
4
5
L2608
6 MLB-201209-0120P-N2
C2602 C2603 C2605 C2606
10uF 0.1uF 10uF 0.1uF
25V 25V 25V 25V
OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Renesas MICOM
For Debug
+3.5V_ST
X3000-*1
32.768KHz
CRYSTAL_KDS
POWER_DET_1
18pF
15pF
MICOM_DEBUG
LOGO_LIGHT
R3016 1K
R3014 10K
C3002
C3003
MICOM_DEBUG Don’t remove R3014,
MICOM_RESET
MICOM_DEBUG
LOGO_LIGHT
P3000
12507WS-04L
not making float P40 X3000
WIFI_EN
1 32.768KHz
CRYSTAL_EPSON
2
MICOM_DEBUG
R3028
3
4.7M +3.5V_ST
4
MICOM_RESET HDMI_WAUP:HDMI_INIT OPT
5
MHL_DET
10K
POWER_DET_1
R3030
MICOM_RESET_SW
GND SW3000
JTP-1127WEM
2 1
33
R3031
270K
OPT
C3004
P124/XT2/EXCLKS
0.47uF
0.1uF 4 3
+3.5V_ST
16V
R3029
P122/X2/EXCLK
P41/TI07/TO07
C3001
P137/INTP0
P120/ANI19
P40/TOOL0
P123/XT1
C3000
P121/X1
0.1uF
RESET
+3.5V_ST
REGC
VDD
VSS
R3021
10K
GP4 High/MID Power SEQUENCE
48
47
46
45
44
43
42
41
40
39
38
37
P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
I2C_SCL2
POWER_ON/OFF! P61/SDAA0 P00/TI00/TXD1
I2C_SDA2
2 35 SCART_MUTE SCART_MUTE
P62 3 34 P01/TO00/RXD1 POWER_ON/OFF2_4
3D&L_DIM_EN POWER_ON/OFF2_4
POWER_ON/OFF2_1
P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1
WOW_WAKE_UP 5 32 KEY2
RETENTION_DISABLE
POWER_ON/OFF2_2
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM RETENTION_DISABLE
IR KEY1
R3000
0 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
HDMI_CEC
P73/KR3/SO01 8 29 P23/ANI3
R3010
POWER_ON/OFF2_2 MODEL1_OPT_3
POWER_ON/OFF2_3
1K
POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4
MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5
EYE_SDA SIDE_HP_MUTE
POWER_ON/OFF2_4
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MHL_EN
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
MODEL1_OPT_1
10K
SOC_RESET
13
14
15
16
17
18
19
20
21
22
23
24
AR3000
INSTANT_BOOT
3.3K
EYE_Q
OPT
R3004
INSTANT_BOOT
+3.5V_ST
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION MICOM MODEL OPTION
+3.5V_ST
0 1
MICOM_LOGO_LIGHT
MODEL_OPT_0 NON LOGO LOGO For LOGO LIGHT
10K
10K
10K
MICOM_H15
MICOM_PDP
MODEL_OPT_1
R3003
R3007
R3013
LCD OLED Need to Assign ADC port
MODEL_OPT_2 Reserved Reserved --> MHL_EN
MODEL_OPT_3 LM15U H15
MODEL1_OPT_0
MODEL_OPT_4 Reserved Reserved --> 3D&L_DIM_EN
MODEL1_OPT_1
* WILL EXCHANGE #12 PORT & #24 PORT FROM BO REVISION BOARD
FOR UNIFYING WITH LM14 MICOM PORT
MODEL1_OPT_3
INV_CTL
WOL_WAKE_UP
URSA_RESET_MICOM
POWER_DET
POWER_ON/OFF1
LED_R
WOL_CTL
SOC_RESET
SOC_TX
SOC_RX
AMP_MUTE
EDID_WP
MICOM_NON_LOGO_LIGHT
MICOM_LCD/OLED
10K
10K
10K
MICOM_M14
For CEC
R3001
R3005
R3012
+3.5V_ST
URSA_RESET_MICOM
LED_R
EDID_WP
R3033 R3034
27K 100K
G
D3000
HDMI1.4_CEC
BAT54_SUZHO R3009 22
CEC_REMOTE HDMI_CEC
D
S
Q3001 R3008 22
RUE003N02 HDMI2.0_CEC
HDMI2.0_CEC
G
HDMI_CEC_FET_ROHM HDMI2.0 CEC
Q3001-*1
SI1012CR-T1-GE3
D
S
HDMI_CEC_FET_VISHAY
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012.02.22
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+1.0V_SIL9679
5V_HDMI_1 IC100
5V_HDMI_2_MHL
LG1210D-B0(H15D-B0)
33
R3252
EXTERNAL_EDID 5V_HDMI_2_MHL R3266
4.7K MHL_DIODE_KEC
R3274
R3222 0 BODY_SHIELD OPT IC3205 D3213-*1
1K Q3212 1/16W +5V_SIL9679 5V_HDMI_2_MHL
5%
1/16W
4.7K
E R3253
BD82034FVJ AV39 AT4
B
R3254 MMBT3904(NXP) +5V_MHL SMAB34
EXTERNAL_EDID 4.7K HDMI_HPD_1_GPIO E D0-_HDMI1 HDMI_0_RX0N HDMI_TX0N
C 20 R3255 AV40 AT3
4.7K D0+_HDMI1 HDMI_0_RX0P HDMI_TX0P
R3224 INTERNAL_EDID R3273 HP_DET 40V AV41 AU4
Q3202 B 1K 100 MMBT3906(NXP)
GND OUT_3 D1-_HDMI1 HDMI_0_RX1N HDMI_TX1N
C
19 1/16W B Q3211 1 8 AV42 AU3
MMBT3904(NXP) 5V D1+_HDMI1
ESD_HDMI
BODY_SHIELD OPT HDMI_HPD_1 HDMI_0_RX1P HDMI_TX1P
VA3201
5% AU39 AU1
EXTERNAL_EDID C
R3263
18 MHL_DIODE_SUZHOU D2-_HDMI1 HDMI_0_RX2N HDMI_TX2N
E
100K
R3241 GND HDMI_HPD_2_MHL D3213 AU40 AU2
20 IN_1 OUT_2
ESD_HDMI
4.7K D2+_HDMI1 HDMI_0_RX2P HDMI_TX2P
VA3214
2 7
ESD_HDMI
17 AW39 AR2
VA3212
HP_DET OPT DDC_DATA C3214 CK-_HDMI1
40V HDMI_0_RXCN HDMI_TXCN
19 DDC_SDA_2_MHL 0.1uF C3220 AW40 AR1
ESD_HDMI
AR3200 R3276 16 CK+_HDMI1 HDMI_0_RXCP HDMI_TXCP
VA3215
5V DDC_CLK 16V IN_2 OUT_1 R3220
33 0 3 6 10uF
DDC_SCL_2_MHL 5V_HDMI_1
18 1/16W 15 100K 10V AY42 AP3
GND NC AR3206 DDC_SCL_1_Buffer
DDC_SDA_1 33 DDCD0_CK/GPIO53 DDCD_T_CK/GPIO60
17 EN OC AY41 AP4
DDC_DATA 14 4 5 DDC_SDA_1_Buffer DDCD0_DA/GPIO52 DDCD_T_DA/GPIO61
DDC_SCL_1 CE_REMOTE 1/16W MHL_DET AT36 AN2
R3248
11K
INTERNAL_EDID INTERNAL_EDID HDMI_HPD_1 HDMI_0_HPD HDMI_TX_HPD
16 R3224-*1 R3274-*1 CEC_REMOTE
DDC_CLK 100 13 ESD_HDMI SPDIF_OUT_ARC AT37
R3214
VA3204 150 CK- ESD_HDMI HDMI_0_ARC
VA3202 VA3216 VA3217 D3209 AU36 AR3
ESD_HDMI
10K
15 ESD_HDMI 12 DF10G7M1N HDMI_0_5V_IN HDMI_TX_CEC
ARC CK_GND AR4
IO1 NC_5
HDMI_TX_DDCCEC
EAG63530102
14 1 10 CK-_HDMI2_JACK
11 AN1
22K
R3249
CE_REMOTE CK+
CEC_REMOTE 10 IO2 NC_4 HDMI_TX_REXT
13 2 9 CK+_HDMI2_JACK AR39
CK- D0-_HDMI2_MHL HDMI_1_RX0N
D0- AR40
9 GND
3 8
NC_3 D0+_HDMI2_MHL HDMI_1_RX0P
12 D3203 AP39
CK_GND D0_GND OPT D1-_HDMI2_MHL
DF10G7M1N HDMI_1_RX1N
3.3V Power Separation
EAG63530102
8 IO3
4 7
NC_2
D0-_HDMI2_JACK AP40
11 IO1
1 10
NC_5
CK-_HDMI1 +3.3V_NORMAL +5V_MHL D1+_HDMI2_MHL
CK+ D0+ HDMI_1_RX1P
10 AP41
IO2 NC_4
7 IO4
5 6
NC_1
D0+_HDMI2_JACK D2-_HDMI2_MHL HDMI_1_RX2N
D0- 2 9 CK+_HDMI1 AP42
R3235
9 D1- +3.3V_NORMAL +5V_MHL D2+_HDMI2_MHL HDMI_1_RX2P
6 AT41
10K
GND NC_3
D0_GND 3 8 CK-_HDMI2_MHL HDMI_1_RXCN
8 OPT D1_GND AT42
5 IO1
1 10
NC_5
D1-_HDMI2_JACK VDD3V3_HDMI 5V_HDMI_2_MHL CK+_HDMI2_MHL HDMI_1_RXCP
R3208
IO3 NC_2
D0+ 4 7 D0-_HDMI1 +3.3V_SIL9679
D1+
10K
7
G
IO4 NC_1
4 IO2
2 9
NC_4
D1+_HDMI2_JACK L3207 AT40
D1- 5 6 D0+_HDMI1 DDC_SCL_2_MHL_OUT DDCD1_CK/GPIO51
D2- BLM18PG121SN1D
R3260
11K
6 AT39
3 GND
3 8
NC_3
DDC_SDA_2_MHL_OUT DDCD1_DA/GPIO50
D1_GND AR37
G
S
D
D2_GND OPT HDMI_HPD_2_MHL_OUT HDMI_1_HPD
5 2 IO3 NC_2
L3200
IO1 NC_5 4 7 D2-_HDMI2_JACK AO3438 AR38
D1+ 1 10 D1-_HDMI1 BLM18PG121SN1D HDMI_1_5V_IN
4 D2+ Q3204 AP38
IO2 NC_4
1 IO4
5 6
NC_1
D2+_HDMI2_JACK C3221 C3238 HDMI_1_CD_SE
S
D
D2- 2 9 D1+_HDMI1
22K
R3261
D3208 0.1uF 10uF
3 AO3438
GND NC_3 DF10G7M1N +3.5V_ST C3206 16V 10V AM41
D2_GND 3 8 Q3200 C3211 D0-_HDMI3 HDMI2_0_RX0N
2 OPT 10uF 0.1uF AM42
R3212 D0+_HDMI3 HDMI2_0_RX0P
IO3 NC_2 JK3203 HDMI LEAKAGE
R3229
D2+ 4 7 D2-_HDMI1 1K 10V 16V AL39
1 D1-_HDMI3 HDMI2_0_RX1N
10K
IO4 NC_1 05008WR-H19C. R3230 E MMBT3906(NXP) AL40
5 6 D2+_HDMI1 1/16W D1+_HDMI3 HDMI2_0_RX1P
10K Q3208 WILL REMOVE H15D B0 AK39
R3213
D3202 5% D2-_HDMI3 HDMI2_0_RX2N
300K
DF10G7M1N C B AK40
D3214
5V_DET_HDMI3 D2+_HDMI3 HDMI2_0_RX2P
JK3202 AM39
B C CK-_HDMI3 HDMI2_0_RXCN
MHL_DET AM40
05008WR-H19C. HDMI1 C3212 Q3207 CK+_HDMI3 HDMI2_0_RXCP
0.1uF
MMBT3904(NXP) E
(CD_SENCE)
16V AN40
5V_HDMI_3 HDMI2 With MHL OPT
5V_HDMI_3 DDC_SCL_3_Buffer
DDC_SDA_3_Buffer
AN39
DDCD2_0_CK/GPIO63
DDCD2_0_DA/GPIO62
AR36
HDMI_HPD_3 HDMI2_0_HPD
R3243
11K
AN37
R3225 HDMI2_0_ARCN
R3279 HDMI2.0_ARC AN36
1K R3238 HDMI_HPD_3_GPIO HDMI2_0_ARCP
150 AP36
4.7K HDMI2_0_5V_IN
C +3.3V_NORMAL +3.3V_NORMAL +3.3V_NORMAL AM38
R3233 R3275 R3239
HDMI2_0_CEC/GPIO59
Q3205 B 100 100 DDC buffer +5V_MHL +5V_MHL +5V_MHL 1.6K AP37
22K
R3247
MMBT3904(NXP) IC3203 IC3208 IC3207 HDMI2_0_REXT
BODY_SHIELD OPT HDMI_HPD_3
ESD_HDMI
1%
VA3219
PCA9509DP PCA9509DP PCA9509DP Close to Main Change to AH39
1.62K
R3256
E
D0-_HDMI4
100K
20 HDMI2_1_RX0N
AH40
D0+_HDMI4 HDMI2_1_RX0P
HP_DET OPT AH41
R3202
R3203
R3218
R3219
R3271
R3272
VCC_A VCC_B VCC_A VCC_B VCC_A VCC_B D1-_HDMI4 HDMI2_1_RX1N
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
1 8 1 8 1 8
OPT
OPT
OPT
19 R3277 AH42
5V
OPT
OPT
OPT
HDMI1.4_ARC D1+_HDMI4 HDMI2_1_RX1P
0 HDMI2.0_CEC AG39
ESD_HDMI
5V_HDMI_3
VA3213
18 AR3201 R3215 D2-_HDMI4 HDMI2_1_RX2N
GND SPDIF_OUT_ARC A1 B1 DDC_SCL_1 A1 B1 DDC_SCL_3 A1 B1 DDC_SCL_4 AG40
33 0 2 7 2 7 2 7
1/16W D2+_HDMI4 HDMI2_1_RX2P
17
R3205
DDC_DATA AJ39
DDC_SCL_1_Buffer DDC_SCL_3_Buffer DDC_SCL_4_Buffer CK-_HDMI4 HDMI2_1_RXCN
DDC_SDA_3
OPT
A2 B2 DDC_SDA_1 A2 B2 DDC_SDA_3 A2 B2 DDC_SDA_4 5V_HDMI_4 AJ40
1K
16 R3257 CK+_HDMI4 HDMI2_1_RXCP
DDC_CLK HDMI2.0_ARC 3 6 3 6 3 6
DDC_SCL_3 0
15 DDC_SDA_1_Buffer R3217 DDC_SDA_3_Buffer R3223 DDC_SDA_4_Buffer R3270 AK42
NC C3203
R3209
11K
HDMI2.0_ARC GND EN GND EN GND EN DDC_SCL_4_Buffer DDCD2_1_CK/GPIO49
1uF 10K 10K 10K AK41
14 4 5 4 5 4 5
CE_REMOTE DDC_SDA_4_Buffer DDCD2_1_DA/GPIO48
AL37
R3206
CEC_REMOTE 25V HDMI_HPD_4 HDMI2_1_HPD
3.9K
13 VA3206 OPT AM37
OPT
CK-
C3204 R3228 HDMI2_1_5V_IN
ESD_HDMI R3240 AM36
12 0.1uF HDMI2_1_CEC/GPIO58
22K
R3242
CK_GND 22 1.6K AL38
VA3205 16V
EAG63530102
11 VA3208 HDMI2.0_CEC HDMI2_1_REXT
CK+ ESD_HDMI ESD_HDMI D3201 1%
10 RCLAMP7534P
1
D0- CK-_HDMI3
9 Change to 1.62K
DDC_SCL_2_MHL_OUT
DDC_SDA_2_MHL_OUT
5
D0_GND CK+_HDMI3 Close to Main
8
2 OPT DDC pull-up
DDC_SCL_2_MHL
DDC_SDA_2_MHL
D0+
7
+5V_MHL 5V_DET_HDMI4
SPI_DO_MHL
SPI_DI_MHL
SPI_CS_HID
SPI_CS_MHL
SPI_CK_MHL
4
D1- D0-_HDMI3
+5V_MHL+3.5V_ST
I2C_SDA5
6
I2C_SCL5
WILL REMOVE H15D B0 +3.3V_SIL9679
MHL_DET
3 D0+_HDMI3
D1_GND +3.3V_VDDH
5
3.3V_SIL9679
D1+ D3200
A1
A2
A1
A2
4 RCLAMP7534P L3201
1
D2- D1-_HDMI3 BLM18PG121SN1D --> MAX 20mA
3 D3206
5 D1+_HDMI3 D3215
C3228
AR3210 33
D2_GND MMBD6100
C
AR3205 33
C
2 +5V_MHL +5V_MHL +1.0V_VDD10 +3.3V_VDDIO +3.3V_VDDIO 10uF
2 OPT
D2+ 10V
1 L3202
AR3203
BLM18PG121SN1D
1/16W
4
D2-_HDMI3
47K
AR3208
AR3209
3
D2+_HDMI3 C3227
1/16W
1/16W
R3236 1.8K C3225 10uF
47K
47K
C3224
JK3201 DDC_SDA_2_MHL 0.1uF 0.1uF 10V
R3244 10 16V 16V
05008WR-H19C.
HDMI3_HDMI2.0_ARC DDC_SCL_2_MHL DDC_SCL_3 DDC_SCL_4 R3237 1.8K +1.0V_SIL9679
+1.0V_AVDD 1.0V_SIL9679 +1.0V_VDD10
HSIC_VDD10
DDC_SDA_3 DDC_SDA_4
VDDIO33_3
L3203
SPI_MISO
SPI_MOSI
[EP]GND
LPSBV5V
VDD10_4
SPI_CS1
SPI_CS0
SPI_CLK
VDD10_3
C3217 C3218 C3219 BLM18PG121SN1D
--> MAX 350mA
WAKEUP
MHL_CD
5V_HDMI_4
External EDID EEPROM for HDMI port #1 0.1uF
TDSDA
TDSCL
0.1uF 0.1uF
DSDA
DSCL
NC_7
CSDA
CSCL
C3229 C3230 16V 16V 16V
0.1uF C3216
(ONLY for KR MODEL) 5V_HDMI_1 +5V_MHL
+5V_SIL9679
16V
0.1uF
16V
+1.0V_AVDD
10uF
R3231 R3281 EXTERNAL_EDID 10V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
1K R3251 150 HDMI_HPD_4_GPIO E R3200 L3204
4.7K EXTERNAL_EDID 1K C3210 VDD33OUT 1 57 HSIC_VDD33 BLM18PG121SN1D
C MMBT3904(NXP) EDID_WP HDMI_HPD_2_MHL 4.7uF --> MAX 80mA
R3234 R3280 R3246 10V VDD5V_IN 2 56 VDD12OUT C3209
Q3201 B THERMAL C3235
B 100 100 4.7uF
A1
A2
Q3206 10 RPWR5V HSIC_GND 10uF
BODY_SHIELD +3.5V_ST 3 77 55 10V +1.0V_AVDD_PLL
MMBT3904(NXP) IC3201 C
ESD_HDMI
OPT HDMI_HPD_4 CBUS_HPD HSIC_STB 10V
VA3218
C3222 4 54
R3204
20 E M24C02-RMN6T D3210 R3245 COC_GND HSIC_DAT
100K
1uF 5 53
MMBD6100 5.1K L3205
C
HP_DET EXTERNAL_EDID 10V AVDD10_DOC NC_6
6 52 BLM18PG121SN1D
R3278 R3201
19
5V 0 E0 VCC CK-_HDMI2_JACK
RXCN 7 51 XTAL_GND --> MAX 15mA
1 8 4.7K +3.3V_VDDH C3236
CK+_HDMI2_JACK RXCP 8 50 XTAL_OUT +1.0V_AVDD_ETC
18 OPT AR3202 10uF
GND AVDD10_1 XTAL_IN
33 9 49
ESD_HDMI
10V
AR3204
VA3210
1/16W E1 WC IC3202
1/16W
17 2 7 VDD33 10 48 XTAL_VDD33
DDC_DATA L3206
47K
DDC_SDA_4 RX0N 11 SIL9679CNUC 47 TX2P BLM18PG121SN1D
16 C3223 D0-_HDMI2_JACK CK-_HDMI2_MHL
DDC_CLK RX0P TX2N --> MAX 60mA
DDC_SCL_4 E2 SCL 0.1uF 12 46 CK+_HDMI2_MHL
3 6 D0+_HDMI2_JACK 0x60 C3237
15 DDC_SCL_1 16V RX1N 13 45 TX1P
NC D1-_HDMI2_JACK D0-_HDMI2_MHL 10uF
RX1P 14 44 TX1N 10V
14 VA3209 VA3211 VSS SDA D1+_HDMI2_JACK D0+_HDMI2_MHL
CE_REMOTE RX2N TX0P
ESD_HDMI 4 5 DDC_SDA_1 15 43
CEC_REMOTE ESD_HDMI D2-_HDMI2_JACK D1-_HDMI2_MHL
13 RX2P 16 42 TX0N
CK- D2+_HDMI2_JACK D1+_HDMI2_MHL
AVDD10_2 17 41 TXCP
12 EXTERNAL_EDID D2-_HDMI2_MHL
CK_GND FVDD10 TXCN
+1.0V_AVDD_ETC 18 40 D2+_HDMI2_MHL
EAG63530102
11 D3205 VDDIO33_1 AVDD10_DP
CK+ RCLAMP7534P
19 39
10 1
CK-_HDMI4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
9
D0-
5
CK+_HDMI4 SIL9679 +1.0V C3232 C3233
INT
GPIO0_CI2CA
GPIO1_PSCTL
GPIO2
VDD10_1
TMODE
NC_1
NC_2
NC_3
NC_4
GPIO3
GPIO4
GPIO5
VDDIO33_2
RESETN
VDD10_2
AVDD10_PLL
NC_5
TX_HPD
D0_GND C3234
8 2 OPT Vout=0.6*(1+R1/R2) 0.1uF
16V
0.1uF
16V
0.1uF
SPI FLASH For MHL3.0
D0+ 16V +3.3V_SIL9679
7 4
D0-_HDMI4
D1- +3.3V_NORMAL +1.0V_SIL9679
6 3 D0+_HDMI4
IC3200
AP2132MP-2.5TRG1 [EP] --> MAX 490mA
5
D1_GND IC3206
R3232
AR3207
1.8K
R3210
D3204 R3250 MX25L4006EM2I-12G
4.7K
1/16W
+3.3V_SIL9679 HDMI_HPD_2_MHL_OUT
D1+ R2
OPT
4.7K
RCLAMP7534P 1K
4 1
D1-_HDMI4 1 8 +1.0V_AVDD_PLL R3226 P3200
D2- R3207 12507WR-06L C3226
3 10K
THERMAL
5 D1+_HDMI4 PG GND CS# VCC 0.1uF
SPI_CS_MHL 1 8 16V
5%
4.7K
D2_GND 10K
R3211
R3267
SPI_CK_MHL
1.2K
9
2 2 OPT 2 7 R1 1
C3208 +3.3V_SIL9679 R3221
D2+ C3231
WP_MHL
EN ADJ SPI_CS_MHL SO/SIO1 HOL 4.7K
1 4
D2-_HDMI4 0.1uF 0.1uF 2 7
16V
2 SPI_DO_MHL 4MBIT
3 6 SIL9679_INT
5%
4.7K
R3216
3
D2+_HDMI4 SPI_DI_MHL
+5V_MHL VIN VOUT 3 WP# SCL
C3205 WP_MHL 3 6
JK3200 10uF
10V
4 2A 5 C3213
ZD3200
SIL9679_RESET
4
SPI_DO_MHL
SPI_CK_MHL
05008WR-H19C. VCTRL NC 10uF GND SI/S
10V 2.5V 4 5
EAN61387601 OPT 5 SPI_DI_MHL
HDMI4_HDMI2.0 C3207
1uF
MHL_DOWNLOAD
6
10V
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-03-24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LG1210D HDMI I/F
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
HP_OUT HP_OUT
JK3401
+3.3V_NORMAL JSTIB15 L3401 R3404
BLM18PG121SN1D 150
VIN
SPDIF OUT A HP_LOUT_AMP 1/10W JK3403
Fiber Optic
C3403 5% +3.3V_NORMAL PEJ038-3B61
From AMP 0.22uF GND 5
VCC B 10V
R3406
R3400 HP_OUT 10K L 4
33 GND C HP_OUT
SPDIF_OUT R3409
C3400 100 DETECT 3
4 HP_DET
C3402 0.1uF
1/16W
47pF 16V HP_OUT
SHIELD
HP_OUT 5% R 1
50V L3400 R3405
BLM18PG121SN1D 150
EAG61030015
HP_ROUT_AMP 1/10W
C3401 5%
PLACE NEAR TO MAIN SOC From AMP 0.22uF VA3405
10V
Place at JACK SIDE
COMPONENT 1 PHONE JACK CVBS 1 PHONE JACK
+3.3V_NORMAL
+3.3V_NORMAL
R3402
10K R3403
R3401 330K
100 R3408
COMP1_DET 100
1/16W AV1_CVBS_DET
5% 1/16W
VA3401 C3406 5%
VA3402
0.01uF
25V
JK3400 JK3402
PEJ038-3B6111 PEJ038-3B611
5 M5_GND 5 M5_GND
4 M4 COMP1_Y 4 M4
COMP1/AV1/DVI_L_IN
3 M3_DETECT 3 M3_DETECT C3404
VA3406 VA3403 0.01uF
1 M1 25V
1 M1
6 M6 6 M6
COMP1_Pb
COMP1/AV1/DVI_R_IN
VA3407 VA3404 C3405
0.01uF
25V
COMP1_Pr
AV1_CVBS_IN
VA3408
VA3409
SOC_RX2
SOC_TX2
OPT
+3.5V_ST P3401
12507WS-04L
OPT 1
R3407
10K
2
3
4
5
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H034-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JACK HIGH/MID 2012.10.09
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LOGO_LIGHT
AR4000
Place Near Micom 33
1/16W
LOGO_LIGHT_WAFER
LOGO_LIGHT C
B
LOGO_LIGHT
LOGO_LIGHT
1K Q4000
LOGO_LIGHT
R4002
R4001
E
C4000 LOGO_LIGHT MMBT3904(NXP)
10K
0.1uF
16V
WIFI POWER ENABLE CONTROL
+3.5V_WIFI
+3.5V_ST IC4000
AP2191WG-7
IN OUT
P4000 C4003
5 1
R4004
0.1uF GND
2 10K
WIFI/BT_NON_COMBO
WIFI_EN R4003 33 EN FLG
SMAW200-H26S1 R4000 C4004
4 3
10K 0.1uF
OPT
+3.5V_WIFI
GND 1 2 +3.5V_WIFI C4017
22uF
10V
C4006
0.1uF
R4014
100
BT_RESET 3 4 USB_DM R4022
10
BT_Reset WIFI_BT_DM
1/16W
5%
C4002
0.1uF
NC 5 6 USB_DP R4023
10
WIFI_BT_DP
WOW_WAKE_UP
R4005
10
WOL 7 8 GND +3.5V_ST
C4016
5pF
C4015
5pF
50V 50V
FOR EMI
R4012 C4005 SDA 9 10 GND FOR EMI
R4016
100 0.1uF
R4015
EYE_SDA
10K
10K
R4011
100
SCL 11 12 KEY1 R4018
100
EYE_SCL KEY1
+3.5V_ST VA4005 VA4006
INNOCHIPS TECHNOLOGY INNOCHIPS TECHNOLOGY GND 13 14 KEY2 R4017
R4008
1/16W
100
KEY_ESD KEY_ESD KEY2
10K
5%
VA4007 VA4008
IR 15 16 +3.5V_ST OPT OPT
IR KEY_ESD KEY_ESD C4007 C4008
INNOCHIPS TECHNOLOGY
INNOCHIPS TECHNOLOGY 0.1uF 0.1uF
LOGO_LIGHT_WAFER
LED_R
R4013 LED_R 17 18 GND +3.3V_NORMAL
LED_R
1.8K L4002
C4001
0.1uF
. 19 20 . BLM18PG121SN1D
L4001
+3.5V_ST
BLM18PG121SN1D
KEY_ESD
. 21 22 . VA4009
R4019
19 INNOCHIPS TECHNOLOGY
M_REMOTE_CTS
100 . 23 24 .
R4020
100 . 25 26 . +3.3V_NORMAL
M_RFMODULE_RESET
R4021
10K
OPT OPT
C4010 C4011
47pF 47pF
50V 50V 27 M_REMOTE_RTS
For EMI
M_REMOTE_TX
.
M_REMOTE_RX
C4012 C4013 C4014
1000pF47pF 47pF
50V 50V 50V AR4001
100
For EMI
P4003 1/16W
WIFI/BT_COMBO
SMAW200-H18S5
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H040-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS IR / KEY 2012.10.10
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
USB3 (3.0)
+5V_USB_3 MAX 1.2A
C4400 JK4400 JK4400-*1
C4402
ZD4401
10uF 22uF 5205-56209 PC2R009NJA1.
D4400
5V
10V 10V
OPT
IP4294CZ10-TBR VBUS
1
VBUS
1
1 10 D-
2
D-
2
USB3_DM
R4405
0
2 9
USB3.0_CNPLUS
D+ D+
M4400 ESD_READY USB3_DP 3 3
USB3.0_JAE
R4406
MDS62110214 0
3 8 GND
4
GND
4
M4401 ESD_READY 4 7 STDA_SSRX-
5
STDA_SSRX-
5
MDS62110214 USB3_RX0P
5 6 STDA_SSRX+
6
STDA_SSRX+
6
USB3_RX0M
M4402 ESD_USB
MDS62110214 GND_DRAIN GND_DRAIN
7 7
1 10 STDA_SSTX-
8
STDA_SSTX-
8
USB3_TX0M
2 9 STDA_SSTX+
9
STDA_SSTX+
9
USB3_TX0P
3 8 10 10
4 7 SHIELD SHIELD
5 6
D4401
IP4294CZ10-TBR
OCP USB3 USB1 (2.0) USB2 (2.0)
+5V_USB_1 +5V_USB_2
+3.3V_NORMAL +5V_NORMAL +5V_USB_3
MAX 1.0A MAX 1.0A
ZD4400
ZD4402
3AU04S-385-ZC-(LG). 3AU04S-385-ZC-(LG).
5V
5V
IC4400 JK4402 JK4401
OPT
OPT
BD2242G
1
1
USB DOWN STREAM
USB DOWN STREAM
R4401 VIN VOUT
10K 1 6
2
2
USB_DM1 USB_DM2
C4401 R4403 R4407
GND ILIM 0 0
0.1uF 2 5
16V
3
3
USB_DP1 USB_DP2
14K
R4402
1%
DF3D6.8MS
DF3D6.8MS
R4404 R4408
EN OC 0 0
/USB_OCD3 3 4
C4404
D4402
D4403
C4405
4
4
22uF
22uF
10V
5
5
USB_CTL3 10V
R4400
10K
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H044-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012-11-09
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
USB JACK
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Full Scart(18 Pin Gender)
+3.3V_NORMAL
EU
R4801 CLOSE TO JUNCTION
10K
EU
R4802
100
SC_DET
EU 1/16W
ZD4800
C4804 5%
VA4801
5V
0.1uF
SCART_VARISTOR
SC_CVBS_IN
VA4807
SHIELD
SCART_VARISTOR
19
AV_DET 75 R4800
18
COM_GND EU
VA4808 DTV/MNT_V_OUT
17
SYNC_IN OPT
16
SYNC_OUT
15
SYNC_GND
14
RGB_IO
13 SC_FB
R_OUT VA4802
12
R_GND SCART_VARISTOR
11
G_OUT
10
G_GND
9 SC_R
ID
8 VA4803
B_OUT
7
AUDIO_L_IN SCART_VARISTOR
6
B_GND
5 SC_G
AUDIO_GND
4 VA4804
AUDIO_L_OUT
3
AUDIO_R_IN SCART_VARISTOR
2
AUDIO_R_OUT
1
SC_B
VA4805
DA1R018H91E
SCART_VARISTOR
JK4800
EU
SC_ID
SC_L_IN
VA4800 VA4809
SCART_VARISTOR
SCART_VARISTOR
SC_R_IN
VA4806
SCART_VARISTOR
BLM18PG121SN1D
L4800
DTV/MNT_L_OUT
EU EU EU
C4800 C4802
1000pF 4700pF
50V
BLM18PG121SN1D
L4801
DTV/MNT_R_OUT
EU
EU EU C4803
C4801 4700pF
1000pF
50V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H048-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012.10.31
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART GENDER
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
LAN_JACK_POWER
C5100 C5101 C5102 C5103
0.1uF 0.01uF 0.1uF 0.01uF
16V 50V 16V 50V
JK5100
BS-RSD0303
P1[CT]
R1
P2[TD+]
R2
EPHY_TDP
P3[TD-]
R3
EPHY_TDN
P4[RD+]
R4
EPHY_RDP
P5[RD-]
R5
EPHY_RDN
P6[CT] VA5100 VA5101 VA5102 VA5103
R6
5.5V 5.5V 5.5V 5.5V
P7
R7
P8
R8
9
R9 EMI
R5100
P10[GND] 0
R10
P11 ETH_EMI
R11
YL_C
P1
YL_A
P2
GN_C
P3
GN_A
P4
16
SHIELD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LAN_VERTICAL 2011.12.09
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 50
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
+3.5V_WOL
3.3K
R5215
EPHY_ACTIVITY
ET_RXER
R5217 3.3K
LAN_JACK_POWER
Place this cap. near IC
+3.5V_WOL
C5208
ET_COL/SNI 0.1uF
C5200 C5201 C5203 C5212 16V
4.7uF 0.1uF 0.1uF 4.7uF
10V 16V 16V 10V
EPHY_ACTIVITY
EPHY_CRS_DV
Place 0.1uF close to each power pins
ET_COL/SNI
ET_RXER
X-TAL_1
GND_1
C5206
18pF +3.5V_WOL
50V
1M R5202
R5218
2
1
25MHz
X5200
R5210
0
OPT
3
4
X-TAL_2
GND_2
33
+3.5V_WOL
LED1/PHYAD[1]
Place this cap. near IC C5207
CRS/CRS_DV
DVDD10OUT
RXER/FXEN
18pF
AVDD33_2
CKXTAL2
CKXTAL1
50V
R5212
1/16W
R5219
1/16W
R5205
3.3K
[EP]
1.2K
C5205
COL
10K
Place this Res. near IC
1%
5%
0.1uF
16V
32
31
30
29
28
27
26
25
R5204
2.49K 1% RSET LED0/PHYAD[0]/PMEB
1 24 WOL_WAKE_UP
THERMAL
AVDD10OUT 2 33 23 MDIO EPHY_MDIO
Route Single 50 Ohm, Differential 100 Ohm MDI+[0] 3 22 MDC EPHY_MDC
EPHY_RDP
MDI-[0] IC5200 PHYRSTB
4 21 /RST_PHY (from SOC)
EPHY_RDN RTL8201F-VB-CG
MDI+[1] 5 20 TXEN
EPHY_TDP EPHY_EN
+3.5V_WOL MDI-[1] 6 19 TXD[3]
EPHY_TDN
AVDD33_1 7 18 TXD[2]
ETHERNET INTERFACE
- CROSS CONNECTION R5203 RXDV TXD[1]
8 17 EPHY_TXD1
(PATTERN ISSUE)
3.3K
10
11
12
13
14
15
16
9
RXD[0]
RXD[1]
RXD[2]/INTB
RXD[3]/CLK_CTL
RXC
DVDD33
TXC
0 TXD[0]
+3.5V_WOL
+3.5V_WOL
R5211
R5200
3.3K
C5211
0.1uF
C5209
16V
R5209
33pF
56
EPHY_TXD0
C5202
3.3K
EPHY_RXD1
EPHY_RXD0
Place near IC
5pF
R5208
WOL POWER ENABLE CONTROL EPHY_REFCLK
+3.5V_ST
+3.5V_WOL
IC5201
AP2151WG-7
IN OUT
5 1
ZD5200
C5204
R5207
0.1uF GND
2 100K
OPT
WOL_CTL R5206 33 EN FLG
4 3
R5201 C5210
10K 0.1uF
OPT OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-NC4_H052-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2012-09-12
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETHERNET
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
DUAL COMPONENT
AMP_RESET_N
Q1801 L5601 L5604
1ST : 0TRIY80001A 2ND : 0TR387500AA 10.0uH
BLM18PG121SN1D SPK_L+
NRS6045T100MMGK
50V
AUD_SCK
+18V_AMP
PGND1A 22000pF
R5603
C5604
3.3
+18V +18V_AMP 1/10W R5607
C5618
C5603 0.1uF 4.7K
50V
[EP]GND
0.1uF C5611
L5600 C5606 390pF
VDD_IO
GND_IO
PVDD1A
PVDD1B
UBW2012-121F 16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
25V
C5616
0.47uF
50V
AD
C5612
390pF
50V C5619 R5608
SPEAKER_L
AMP - MAIN, TWT R5604
3.3
0.1uF
50V 4.7K
40
39
38
37
36
35
34
33
32
31
1/10W
L5605
NC_1 1 30 OUT1B 10.0uH SPK_L+_TW
12
SPK_L-
NRS6045T100MMGK
VDD_PLL 2 29 PGND1B C5608
THERMAL 22000pF
SPK_L-_TW
11
NC_2 3 41 28 BST1B 50V
C5601
1uF SPK_R+_TW
10
10V GND 4 27 VDR1
NC_3 5 IC5600 26 NC_5 SPK_R-_TW
9
C5602
1uF
10V
DVDD 6 NTP7515 25 AGND SPK_L+ 8
AUD_LRCH
SDATA 7 24 VDR2 SPK_L- 7
WCK 0x54 BST2A
C5610
1uF
C5615
1uF
AUD_LRCK 8 23 10V 10V
SPK_R+ 6
NC_4 9 22 PGND2A C5609
22000pF
R5611
I2C_SDA1
100 SDA 10 21 OUT2A 50V SPK_R- 5
R5612
100
11
12
13
14
15
16
17
18
19
20
SPK_L+_WF
I2C_SCL1 4
C5622 C5623
33pF 33pF L5602 SPK_L-_WF
50V 3
50V 10.0uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+
NRS6045T100MMGK
SPK_R+_WF
2
+3.3V_NORMAL +18V_AMP
R5605 SPK_R-_WF
3.3 1
1/10W C5620 R5609
R5601 0.1uF 4.7K
C5613 C5617
10K
R5602
390pF
50V
0.47uF
50V
50V
SPEAKER_R P5600
C5607 SMAW250-12
10uF C5614 SPK_12PIN
C 100 390pF
25V 50V
R5600 C5600 C5621 R5610
B Q5600 C5605
AMP_MUTE 1000pF 0.1uF 4.7K
MMBT3904(NXP) R5606
10K 50V 22000pF 3.3 50V
L5603
E I2S_MAIN_OUT 50V 1/10W 10.0uH
SPK_R-
NRS6045T100MMGK
WOOFER_MUTE
+3.3V_NORMAL
+3.3V_NORMAL
AMP_RESET_N
L5620 L5621
10.0uH
4.7K R5613
BLM18PG121SN1D SPK_L+_TW
NRS6045T100MMGK
50V
AUD_SCK
+18V_AMP_TWT
PGND1A 22000pF
L5611
C5630
3.3
1/10W L5615
C5644
C5629 0.1uF 4.7K
50V
[EP]GND
0.1uF C5638
C5632 390pF
VDD_IO
GND_IO
PVDD1A
PVDD1B
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
25V
+18V +18V_AMP_TWT C5642
0.47uF
50V
AD
L5619
UBW2012-121F C5639
390pF
50V C5645 L5616
L5612 0.1uF
50V 4.7K
SPEAKER_L_TWITTER
3.3
40
39
38
37
36
35
34
33
32
31
1/10W
L5624
NC_1 1 30 OUT1B 10.0uH
SPK_L-_TW
NRS6045T100MMGK
VDD_PLL 2 29 PGND1B C5634
THERMAL 22000pF
NC_2 3 41 28 BST1B 50V
C5627
1uF
10V GND 4 27 VDR1
NC_3 5 IC5601 26 NC_5
C5628
1uF
10V
DVDD 6 NTP7515 25 AGND
AUD_LRCH_TW
SDATA 7 24 VDR2
WCK 0x56 BST2A
C5636
1uF
C5637
1uF
AUD_LRCK 8 23 10V 10V
NC_4 9 22 PGND2A C5635
22000pF
L5608
I2C_SDA1
100 SDA 10 21 OUT2A 50V
L5609
100
11
12
13
14
15
16
17
18
19
20
I2C_SCL1
C5625 C5626
33pF 33pF L5622
50V 50V 10.0uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+_TW
NRS6045T100MMGK
+18V_AMP_TWT
L5613
3.3
1/10W C5646 L5617
0.1uF 4.7K
C5640 C5643 50V
390pF 0.47uF
C5633 50V 50V
SPEAKER_R_TWITTER
10uF C5641
390pF
25V 50V
C5647 L5618
C5631
L5614 0.1uF 4.7K
22000pF 3.3 50V
L5623
50V 1/10W 10.0uH
SPK_R-_TW
NRS6045T100MMGK
WOOFER_MUTE
WOOFER_MUTE
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
AMP - Woofer
+18V +18V_AMP_WOOFER
+3.3V_NORMAL
L5900
UBW2012-121F
AMP_RESET_N
L5901 L5902
10.0uH
BLM18PG121SN1D SPK_L+_WF
NRS6045T100MMGK
50V
AUD_SCK
+18V_AMP_WOOFER
PGND1A 22000pF
R5902
C5905
3.3
1/10W R5906
C5919
C5904 0.1uF 4.7K
50V
[EP]GND
0.1uF C5913
C5907 390pF
VDD_IO
GND_IO
PVDD1A
PVDD1B
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
25V
C5917
0.47uF
50V
AD
C5914
390pF
50V C5920 R5907
R5903 0.1uF
50V 4.7K
SPEAKER_L_WOOFER
3.3
40
39
38
37
36
35
34
33
32
31
1/10W
L5905
NC_1 1 30 OUT1B 10.0uH
SPK_L-_WF
NRS6045T100MMGK
VDD_PLL 2 29 PGND1B C5909
THERMAL 22000pF
NC_2 3 41 28 BST1B 50V
C5902
1uF
10V GND 4 27 VDR1
NC_3 5 IC5900 26 NC_5
C5903
1uF
10V
DVDD 6 NTP7515 25 AGND
AUD_LRCH
SDATA 7 24 VDR2
WCK
0x54 BST2A
C5911
1uF
C5912
1uF
AUD_LRCK 8 23 10V 10V
NC_4 9 22 PGND2A C5910
22000pF
R5900
I2C_SDA5
100 SDA 10 21 OUT2A 50V
R5901
100
11
12
13
14
15
16
17
18
19
20
I2C_SCL5
C5900 C5901
33pF 33pF L5903
50V 50V 10.0uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+_WF
NRS6045T100MMGK
+18V_AMP_WOOFER
R5904
3.3
1/10W C5921 R5908
0.1uF 4.7K
C5915 C5918 50V
390pF 0.47uF
C5908 50V 50V
SPEAKER_R_WOOFER
10uF C5916
390pF
25V 50V
C5922 R5909
C5906
R5905 0.1uF 4.7K
22000pF 3.3 50V
L5904
50V 1/10W 10.0uH
SPK_R-_WF
NRS6045T100MMGK
WOOFER_MUTE
WOOFER_MUTE
I2S_WOOF_OUT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-059-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+12V
AUD_OUT >> EU/CHINA_HOTEL_OPT
EU
IC6000 L6000
AZ4580MTR-E1
EU
EU
2.2K R6000 OUT1 8 VCC C6004
DTV/MNT_L_OUT 1
0.1uF EU
EU
C6000 OPT 50V R6011 C6008
OPT R6002 EU IN1- OUT2 SIGN600002 2.2K
1uF 33K R6004 2 7
25V C6002 470K DTV/MNT_R_OUT
EU 6800pF
33pF C6003
IN1+ EU 6 IN2- R6008
EU
33K
OPT
R6010
OPT 1uF
EU 3
470K
C6007
6800pF
25V
[SCART AUDIO MUTE]
VEE 5 IN2+
4 C6005 EU
33pF DTV/MNT_L_OUT
SCART_AMP_L_FB
SCART_AMP_R_FB
EU
C
R6013
Q6000 B 1K
Near Place Scart AMP MMBT3904(NXP)
SCART_Lout EU_SCART_MUTE_ISAHAYA
SCART_Rout EU E EU Q6002
+12V EU
RT1P141C-T112
SCART_AMP_R_FB SCART_MUTE
C
E
10K
4.7uF 10V R6006
C6006
R6001
R6007
100K
100K
EU
EU
B
EU EU
SCART_AMP_L_FB
EU 10K DTV/MNT_R_OUT
4.7uF 10V PDTA114ET
SCART_Lout SCART_Lout_SOC C6001 R6005 Q6002-*1
C6009 EU
C
E
EU C
2.2uF R6014
SCART_Rout 10V Q6001 B 1K
SCART_Rout_SOC
C6010 MMBT3904(NXP)
R6003
R6009
B
100K
100K
EU
EU
2.2uF
10V E EU EU_SCART_MUTE_NXP
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS SCART AUDIO AMP 2011.11.21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 60
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
EARPHONE AMP
HP_OUT
IC6100
TPA6138A2
+INR +INL
HP_OUT C6104 1 14 C6109 HP_OUT
C6100 HP_OUT 15pF HP_OUT HP_OUT 15pF HP_OUT C6101
R6107 1uF R6100 R6106 R6104 R6101 1uF R6108
100 25V 10K 43K HP_OUT -INR -INL HP_OUT 43K 10K 25V 100
2 13
AUDA_OUTR AUDA_OUTL
R6103 1% C6108 C6106 1% R6102
From A-chip 10pF 10pF From A-chip
43K OUTR OUTL 43K
50V 3 12 50V
HP_LOUT_AMP
HP_ROUT_AMP
+3.3V_NORMAL GND_1 UVP
4 11
MUTE GND_2 +3.3V_NORMAL
3.3K 5 10
R6105
HP_OUT
SIDE_HP_MUTE VSS VDD
6 9
HP_OUT
C6102 HP_OUT HP_OUT
1uF C6105 C6107
CN CP 1uF 0.1uF
10V 7 8
10V 16V
HP_OUT
C6103
1uF
25V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. 2011.09.29
HEADPHONE AMP
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 61
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
B-CAS (SMART CARD) INTERFACE
+3.3V_NORMAL INT CMDVCC : STATUS
+3.3V_NORMAL ---------------------------------
HIGH HIGH CARD PRESENT
LOW HIGH CARD not PRESENT
SIGN630028
IC6300
TDA8024TT
2.7K
2.7K
R6301
R6303
R6305
JAPAN
JAPAN
CLKDIV1 CLKDIV2 : F_CRD_CLK
OPT
-----------------------------
1 0 CLKIN CLKDIV1 AUX2UC
1 28
JAPAN
JAPAN
JAPAN
R6317
R6318
R6315
R6319
R6316
OPT
OPT
1.2K
1.2K
1.2K
1.2K
1.2K
CLKDIV2 AUX1UC
2 27
R6300 33 5V/3V I/OUC
SMARTCARD_PWR_SEL 3 26
2.7K
JAPAN
R6302
R6304
R6306
JAPAN
OPT
OPT
PGND XTAL2
+5V_NORMAL 4 25
R6307 33 JAPAN
S2 XTAL1 SMARTCARD_DATA
JAPAN 5 24 R6308 33 JAPAN
SMARTCARD_CLK
L6300 R6309 33 JAPAN
SMARTCARD_DET
BLM18PG121SN1D VDDP OFF R6310 33 JAPAN
JAPAN 6 23 SMARTCARD_RST
JAPAN
C6301 C6303
10uF 0.1uF S1 GND JAPAN
10V 16V 7 22 R6311 33 SMARTCARD_VCC
L6301 JAPAN
+3.3V_NORMAL
JAPAN
VUP VDD BLM18PG121SN1D
8 21
JAPAN
JAPAN JAPAN
C6302 PRES RSTIN C6305 C6306
0.1uF 9 20 0.1uF 0.1uF
16V 16V 16V
B-CAS SLOT
PRES CMDVCC
10 19
P6300
I/O PORADJ 10057542-1311FLF(B CAS Slot)
11 18
AUX2 VCC JAPAN VCC
12 17 C1
C6307
0.33uF
AUX1 RST 16V RST
13 16 C2
CGND CLK Place CLK C3 far from C2,C7,C4 and C8 CLK
14 15 C3
JAPAN
C6304 RESERVED_1
0.1uF C4
16V
GND
C5
VPP JAPAN
C6
JAPAN
R6313
75 I/O
C7
75 ohm in I/O is for short circuit Protection
RESERVED
C8
SW1
S1
+3.3V_NORMAL
JAPAN
JAPAN
10K
R6312
R6314
1K SW2
S2
ZD6300 ZD6301
JAPAN
JAPAN
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JAPAN B-CAS 2011.04.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 63
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
MAX : 350mA
+3.3V_NORMAL
close to tuner pin
Global F/E Option Name L6500 1. should be guarded by ground
BLM18PG121SN1D close to Tuner 2. No via on both of them
1. TU
2. Tuner Name = TDS’S’,TDS’Q’... 1 +3.3V_LNA_TU C6507 C6519 OPT 3. Signal Width >= 12mils
0.1uF 0.1uF R6504 Signal to Signal Width = 12mils
3. Country Name = T,T2,S2,KR,US,BR ... OPT OPT 1K
RF_SWITCH_CTL_TU RF_SWITCH_CTL
Ground Width >= 24mils
2 C6502 R6502
Example of Option name close to Tuner 0.1uF 10K
TU_Q_T2 = apply TDSQ type tuner and T2 country
TU_M/W = apply TDSM&TDSW Type Tuner
TU_ALL_IntDemod R6503
IF_AGC_TU 100 IF_AGC
3 TU_ALL_IntDemod
13’ Tuner Type for Global C6500
0.1uF TU_I2C_200OHM
TDS’S’-G501D : T/C Half NIM Horizontal Type 16V +3.3V_NORMAL
BLM18PG121SN1D
TU_ALL_2178B
AR6501 AR6501-*1
TDS’Q’-G501D : T/C/S2 Combo Horizontal type 33 200
1/16W 1/16W
TDS’Q’-G601D : T2/C/S2 Combo Horizontal Type
L6504
TDS’Q’-G651D : T2/C/S2 Combo Vertical Type 4 I2C_SCL6_TU I2C_SCL6
C6503
TDS’M’-C601D : China NIM with Isolater Type 15pF
50V
TDS’W’-J551F : Japan Dual NIM 5 I2C_SDA6_TU I2C_SDA6
C6501 TU_M_AJ TU_I2C_33OHM
TDS’W’-B651F : Brazil 2Tuner 15pF TU_ALL_2178B
TDS’W’-A651F : Taiwan 2Tuner 50V
TU_M_AJ
C6516
0.1uF
TDS’W’-K651F : Colombia DVB-T2 2Tuner TU_ALL_IntDemod 16V 1608 perallel
because of derating
R6516 10 OPT IF_P
6 IF_P_TU
TU_ALL_IntDemod C6526 R6505 R6506 TU_ALL_2178B
33pF should be guarded by ground,Match GND VIA TU_ALL_2178B 200 200
R6517 10 IF_N
OPT 50V
7 IF_N_TU
C6525
33pF TU_CVBS
50V TU_SIF
TU_SIF
8
E
TU_CVBS_TU TU_ALL_2178B
9 L6501 +3.3V_NORMAL B Q6500
BLM18PG121SN1D MMBT3906(NXP)
C
11 +3.3V_TUNER
C6509 TU_M/W/Q
0.1uF MAX : 800mA
14 FE_DEMOD1_TS_CLK FE_DEMOD1_TS_CLK TU_M/W/Q
FE_DEMOD1_TS_DATA[0]
17 FE_DEMOD1_TS_DATA[0] FE_DEMOD1_TS_DATA[0]
18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[1-7]
FE_DEMOD1_TS_DATA[1]
19 FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
20 FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]
21 FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[6]
22 FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[7]
23 FE_DEMOD1_TS_DATA[6]
24 FE_DEMOD1_TS_DATA[7]
R6500
100 /TU_RESET1
25 /TU_RESET1_TU
L6503 +3.3V_NORMAL TU_M/W/Q
C6505
BLM18PG121SN1D 16V
26 +3.3V_DEMOD_TU 0.1uF
TU_M/W/Q TU_M/W/Q TU_M/W/Q
R6520 C6510
33 0.1uF
27 I2C_SCL4_TU TU_M/W/Q
D_DEMOD_CORE I2C_SCL4 MAX : 200mA
C6512
15pF
28 D_DEMOD_CORE 50V
OPT
29 LNB_TX1 LNB_TX1
TU_M/W/Q
R6519
33
30 I2C_SDA4_TU I2C_SDA4
C6511
15pF
LNB_OUT1 50V
31 LNB_OUT1 OPT
C6520 C6521
0.1uF 18pF
LNB1 LNB1
37 FE_DEMOD3_TS_CLK FE_DEMOD3_TS_CLK
L6502 +2.5V_Normal
BLM18PG121SN1D
38 +2.5V_DEMOD
C6506 TU_W_JP
0.1uF
FE_DEMOD3_TS_DATA FE_DEMOD3_TS_DATA TU_W_JP
40
R6501
100 /TU_RESET2
45 /TU_RESET2_TU
C6504 TU_W/Q_JP/EU
16V
0.1uF
TU_W/Q_JP/EU
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TUNER 2014.04.29
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 65
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
TDJW-J351F TDJM-A651D TDJQ_G151D TDJM_H351F TDJH_H351F
TU6700 TU6702 TU6704 TU6701 TU6703
TDJW-J351F TDJM-A651D TDJQ-G151D TDJM-H351F TDJH-H351F
+3.3V_LNA +3.3V_LNA +3.3V_LNA +3.3V +3.3V
1 1 1 1 1 +3.3V_LNA_TU
NC_1 NC_1 NC_1 NC_1 NC
2 2 2 2 2 RF_SWITCH_CTL_TU
NC_2 NC_2 NC_2 DIFAGC DIF_AGC
3 3 3 3 3 IF_AGC_TU
SCL_RF SCL_RF SCL_RF SCL_RF SCL_RF
4 4 4 4 4 I2C_SCL6_TU
SDA_RF SDA_RF SDA_RF SDA_RF SDA_RF
5 5 5 5 5 I2C_SDA6_TU
NC_3 NC_3 NC_3 DIF[P] DIF[P]
6 6 6 6 6 IF_P_TU
NC_4 NC_4 NC_4 DIF[N] DIF[N]
7 7 7 7 7 IF_N_TU
NC_5 SIF SIF SIF SIF
8 8 8 8 8 TU_SIF
NC_6 CVBS CVBS CVBS CVBS
9 9 9 9 9 TU_CVBS_TU
NC_7 NC_5 NC_5 NC_2 TU6700-*1
10 10 10 10 TDJW-H251F
TDJW-H251F
+3.3V_RF +3.3V_RF +3.3V_RF +3.3V_RF A1 B1 1
B1[+3.3V]
11 11 11 11 +3.3V_TUNER A1 B1 NC
3
NC_8 S_ERROR S_ERROR ERROR 47 4
DIF_AGC
12 12 LNB2 12 12 FE_DEMOD1_TS_ERROR
5
SCL_RF
SDA_RF
6
GND_1 GND LNB_OUT2 47 GND_1 GND 7
DIF[P]
13 13 GND_3 13 13 SHIELD 8
DIF[N]
SIF
9
S_MCLK 48 S_MCLK MCLK 10
CVBS
14 NC_6 14 14 FE_DEMOD1_TS_CLK
11
NC_1
B2[+3.3V]
12
S_SYNC 49 S_SYNC SYNC 13
ERROR
TU_GND_A
15 15 15 GND
TU_GND_B
14
NC_7 FE_DEMOD1_TS_SYNC
15
MCLK
S_VALID 50 S_VALID VALID 16
SYNC
16 GND_4 16 16 FE_DEMOD1_TS_VAL
17
VALID
DATA
18
S_D0 51 S_D0 DATA 19
NC_2
17 F22_M_DEMOD_2 17 17 FE_DEMOD1_TS_DATA[0]
20
NC_3
NC_4
21
S_D1 LNB_TX2
52 S_D1 NC_3 22
NC_5
18 M_D7 18 18 FE_DEMOD1_TS_DATA[1]
23
NC_6
NC_7
24
S_D2 FE_DEMOD2_TS_DATA[7]
53 S_D2 NC_4 25
RESET_DEMOD
19 M_D6 19 19 FE_DEMOD1_TS_DATA[2]
26
B3[+3.3V]
SCL_DEMOD
27
S_D3 FE_DEMOD2_TS_DATA[6]
54 S_D3 NC_5 28
B4[+1.2V]
20 M_D5 20 20 FE_DEMOD1_TS_DATA[3]
29
NC_8
SDA_DEMOD
30
S_D4 FE_DEMOD2_TS_DATA[5]
55 S_D4 NC_6
21 M_D4 21 21 FE_DEMOD1_TS_DATA[4]
A1
A1
47
B1
B1
S_D5 FE_DEMOD2_TS_DATA[4]
56 S_D5 NC_7 SHIELD
22 M_D3 22 22 FE_DEMOD1_TS_DATA[5]
S_D6 FE_DEMOD2_TS_DATA[3]
57 S_D6 NC_8
23 M_D2 23 23 FE_DEMOD1_TS_DATA[6]
S_D7 FE_DEMOD2_TS_DATA[2]
58 S_D7 NC_9
24 M_D1 24 24 FE_DEMOD1_TS_DATA[7] MAX : 1A
RESET_M_DEMOD RESET_DEMOD FE_DEMOD2_TS_DATA[1] 59 RESET_S_DEMOD RESET_DEMOD
25 25 M_D0 25 25 /TU_RESET1_TU R6712
10K
+3.3V_DEMOD +3.3V_DEMOD
FE_DEMOD2_TS_DATA[0]
60 +3.3V_DEMOD +3.3V_DEMOD POWER_ON/OFF2_2 TU_M/W/Q
IC6700 D_DEMOD_CORE
TU_M/W/Q_1.2VTU_M/W/Q_1.2V
26 26 26 26 1/16W
RESET_M_DEMOD +3.3V_DEMOD_TU TU_M/W/Q
AP2132MP-2.5TRG1 [EP]
TU_M/W/Q_1.1V TU_M/W/Q_1.1V
SCL_DEMOD SCL_DEMOD 61 SCL_DEMOD SCL_DEMOD.
R6711-*1 R6710-*1
/TU_RESET2_TU
R6710
1/16W
27 27 M_ERROR 27 27
10K
I2C_SCL4_TU
1/16W
1%
+1.2V_DEMOD +1.2V_DEMOD FE_DEMOD2_TS_ERROR 62 +1.2V_DEMOD +1.2V_DEMOD 1 8 R2
18K
1%
28 28 28 28
THERMAL
M_MCLK D_DEMOD_CORE PG GND
+3.3V_NORMAL
63
R6711
1/16W
NC_9 NC_6 F22_S_DEMOD_1 NC_10
9
FE_DEMOD2_TS_CLK 2 7 R1
29 29 29 29
10K
M_SYNC
1/16W
LNB_TX1
1%
L6700 EN ADJ
64 BLM18PG121SN1D
16K
SDA_DEMOD SDA_DEMOD FE_DEMOD2_TS_SYNC SDA_DEMOD SDA_DEMOD
1%
C6712 3 6
30 30 M_VALID 30 30 I2C_SDA4_TU TU_M/W/Q
TU_M/W/Q VIN VOUT
LNB 65 LNB1
TU_M/W/Q C6711 10uF
31 M_DATA
FE_DEMOD2_TS_VAL
31 LNB_OUT1
0.1uF 10V 4 2A 5
+5V_NORMAL NC
GND_2 FE_DEMOD2_TS_DATA[0] 66 GND_2 A1 B1 VCTRL
32 32 A1 B1 EAN61387601
NC_7 TU_M/W/Q
NC_10 67 47 C6714
33 TU_M/W/Q 10uF
FE_DEMOD2_TS_ERROR M_ERROR A1 B1 C6713 10V
M_ERROR 68 A1 B1 1uF
TU_GND_A
TU_GND_B
34 FE_DEMOD3_TS_ERROR FE_DEMOD2_TS_CLK M_MCLK SHIELD
69 68
GND_3
TU_GND_A
TU_GND_B
35 M_SYNC
FE_DEMOD2_TS_SYNC
70
36
M_SYNC SHIELD Vout=0.6*(1+R1/R2)
FE_DEMOD3_TS_SYNC
FE_DEMOD2_TS_VAL M_VALID
M_MCLK 71 TU6702-*1
TDJM-B651F TDJM-K651F
TU6702-*2
37 TDJM-C451D TDJM-B651F TDJM-K651F
FE_DEMOD3_TS_CLK TU6701-*1
TDJM-C451D
+2.5V_DEMOD 1
+3.3V_LNA
1
+3.3V_LNA
38 +2.5V_DEMOD A1 B1 1
B1[+3.3V]
2
NC_1
NC_2
2
NC_1
NC_2
3 3
M_VALID A1 B1 2
NC_1
4
SCL_RF
4
SCL_RF close to tuner pin
NC_2
39 FE_DEMOD3_TS_VAL 47
3
4
SCL_RF
5
SDA_RF
NC_3
5
SDA_RF
NC_3
6 6
SDA_RF
M_DATA 5
7
NC_4
7
NC_4
TU_GND_B
NC_3
TU_GND_A
40 6 SIF SIF
LNB_OUT2 LNB_OUT2
FE_DEMOD3_TS_DATA 7
NC_4
8
9
CVBS
8
9
CVBS
47
TU_GND_A
TU_GND_B
S_ERROR SHIELD 8
SIF
10
NC_5
10
NC_5 C6709 C6710
CVBS
41 9
11
+3.3V_RF
11
+3.3V_RF 0.1uF 18pF
FE_DEMOD1_TS_ERROR 10
NC_5
S_ERROR S_ERROR 52 LNB_TX2 LNB_TX2 LNB2
NC_6
12 12 LNB2
S_SYNC 11
ERROR
13
GND
13
GND
42 C6702-*1 12
14
S_MCLK
14
S_MCLK
FE_DEMOD1_TS_SYNC 0.022uF
GROUND
FE_DEMOD2_TS_DATA[7]
13
MCLK
15
S_SYNC
15
S_SYNC
53
S_MCLK 630V 14
16
S_VALID
16
S_VALID
SYNC
43 TU_M_KR/AJ_22nF 15
17
S_D0
17
S_D0
FE_DEMOD1_TS_CLK 16
VALID
S_D1 S_D1
DATA0
18 18
54 FE_DEMOD2_TS_DATA[6]
S_VALID 17
DATA1
19
S_D2
19
S_D2
44 FE_DEMOD1_TS_VAL NON_EU/KR/AJ NON_EU/KR/AJ
18
19
DATA2
20
S_D3
S_D4
20
S_D3
S_D4
21 21
C6704 C6702 C6700 R6702 C6701 C6703 C6705 C6707 DATA3
55 FE_DEMOD2_TS_DATA[5] FE_DEMOD2_TS_DATA[7]
S_RESET_DEMOD 0.022uF 1000pF 1000pF 0 1000pF 1000pF 3300pF 1000pF
20
DATA4
22
S_D5
22
S_D5
45 21
23
S_D6
23
S_D6 FE_DEMOD2_TS_DATA[6]
/TU_RESET2_TU 630V 630V 630V 630V 630V 630V 630V 22
DATA5
S_D7 S_D7
24 24
TU_M_KR/AJ_22nF TU_ALL_1000pF TU_NON_AJ OPT TU_W_AJ_1000pF DATA6 FE_DEMOD2_TS_DATA[5]
S_DATA NON_EU/KR/BR/TW 23
25
RESET_DEMOD
25
RESET_DEMOD
56 FE_DEMOD2_TS_DATA[4]
DATA7
FE_DEMOD2_TS_DATA[4]
46 FE_DEMOD1_TS_DATA[0]
24
25
RESET_DEMOD
26
+3.3V_DEMOD
SCL_DEMOD
26
+3.3V_DEMOD
SCL_DEMOD
B2[+3.3V]
27 27 FE_DEMOD2_TS_DATA[3]
C6700-*1 26 +1.2V_DEMOD +1.2V_DEMOD
0.022uF 27
SCL_DEMOD
28
NC_6
28
NC_6
57 FE_DEMOD2_TS_DATA[3]
FE_DEMOD2_TS_DATA[2]
29 29
630V C6701-*1 C6703-*1 28
B3[+1.2V]
SDA_DEMOD SDA_DEMOD
0.022uF 0.022uF NC_7
30 30 FE_DEMOD2_TS_DATA[1]
A1 B1 TU_M_AJ_22nF 29
M_DATA M_DATA
630V 630V SDA_DEMOD 66 66
58 FE_DEMOD2_TS_DATA[2] FE_DEMOD2_TS_DATA[0]
A1 B1 TU_M_KR_22nF TU_M_KR_22nF
30
NC_7
67
NC_7
67
A1 B1 M_ERROR M_ERROR
TU_GND_A
TU_GND_B
68 68
47 A1
47
B1
M_MCLK
69
M_MCLK
69
59 FE_DEMOD2_TS_DATA[1]
SHIELD
M_SYNC
70
M_SYNC
70 FE_DEMOD2_TS_DATA[0-7]
TU_GND_A
TU_GND_B
M_VALID M_VALID
71 71
SHIELD A1
A1 B1
B1 A1
A1 B1
B1
60 FE_DEMOD2_TS_DATA[0]
47 47
SHIELD SHIELD
C6706 C6708 C6715 C6716 C6717 C6718 C6719
3300pF 3300pF 3300pF 0.022uF 0.022uF 0.022uF 0.022uF
630V 630V 630V 630V 630V 630V 630V
TU_M/Q_AJ/EU TU_M/Q_AJ/EU TU_M_AJ OPT OPT OPT OPT
C6716-*1 C6718-*1 C6719-*1
3300pF 3300pF 3300pF
630V 630V 630V
TU_Q_EU TU_M_AJ
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES TU_M_AJ
BSD-14Y-UD-067-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TU_SYMBOL 2012.09.14
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
RS-232C Control INTERFACE _ Phone
JK6800
R6820
100
R 1
R6821 DETECT 3
100
L 4
OPT OPT GND 5
ZD6802 ZD6803 PEJ038-3B61
ADUC 20S 02 010L ADUC 20S 02 010L
20V 20V
+3.5V_ST
IC6801
MAX3232CDR
C1+ VCC C6813
1 16
0.1uF
C6808
0.1uF V+ GND
2 15
C6809
0.1uF C1- DOUT1
3 14
C2+ RIN1
4 13
C6810
0.1uF C2- ROUT1
5 12 SOC_RX
V- DIN1
6 11 SOC_TX
C6811
0.1uF DOUT2 DIN2
7 10
RIN2 ROUT2
8 9
EAN41348201
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-068-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C 68
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DVB-S2 LNB1 Part Allegro
(Option:LNB1) Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A
3A
+12V
2A
Max 1.3A
D6902
3.0A
LNB1 D6904
30V 40V
LPH6050T-150M-R
15uH
LNB1
L6900
LNB1
C6909
10uF
C6903 C6905 C6906 C6907 25V
0.01uF 10uF 10uF 10uF LNB1
50V 25V 25V 25V
LNB1 LNB1 LNB1 LNB1
C6908 0.1uF
close to Boost pin(#1) A_GND
A_GND
LNB1
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND
BOOST
GNDLX
R6904
NC_3
NC_2
C6910 0
A_GND
LX
0.1uF
50V LNB1
20
19
18
17
16
LNB1
D6901 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT1 21
30V LNB1
D6903 NC_1 3 13 VREG
LNB1 C6904
0.1uF LNB1 IC6900 R6903
C6900 C6901 R6900 TDI A8303SESTR-T ISET 39K
LNB1 50V 40V 4 12
15pF 33pF 2.2K
D6900 1W LNB1 1/16W
LNB1 LNB1 C6902 TDO 5 11 TCAP C6912
LNB1 LNB1 0.22uF 1%
LNB1 25V
10
LNB1
6
7
8
9
0.1uF
IRQ
SCL
SDA
ADD
TONECTRL
0.22uF
Close to Tuner A_GND
A_GND
Surge protectioin
LNB1
+12V
C6911
LNB1
R6906
9.1K
R6905
LNB1
0
R6907
R6908
JAPAN
EU
0
0
I2C_SCL4
I2C_SDA4
LNB_TX1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
LNB1 2014.04.29
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
69
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DVB-S2 LNB2 Part Allegro
(Option:LNB2) Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A
3A
+12V
2A
Max 1.3A
D7002
3.0A
LNB2 D7004
30V 40V
LPH6050T-150M-R
15uH
L7000
LNB2
LNB2
C7009
10uF
C7003 C7005 C7006 C7007 25V
0.01uF 10uF 10uF 10uF LNB2
50V 25V 25V 25V
LNB2 LNB2 LNB2 LNB2
C7008 0.1uF
close to Boost pin(#1) A_GND
A_GND
LNB2
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND
BOOST
GNDLX
R7004
NC_3
NC_2
C7010 0
A_GND
LX
0.1uF
50V LNB2
20
19
18
17
16
LNB2
D7001 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT2 21
30V LNB2
D7003 NC_1 3 13 VREG
LNB2 C7004
0.1uF LNB2 IC7000 R7003
C7000 C7001 R7000 TDI A8303SESTR-T ISET 39K
LNB2 50V 40V 4 12
15pF 33pF 2.2K
D7000 1W LNB2 1/16W
LNB2 LNB2 C7002 TDO 5 11 TCAP C7012
LNB2 LNB2 0.22uF 1%
LNB2 25V
10
LNB2
6
7
8
9
0.1uF
IRQ
SCL
SDA
ADD
TONECTRL
0.22uF
Close to Tuner A_GND
A_GND
Surge protectioin
LNB2
+12V
C7011
R7001
LNB2
9.1K
R7002
4.7K
LNB2
I2C_SCL4
I2C_SDA4
LNB_TX2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
LNA2 2014.04.29
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 70
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
eMMC I/F
EMMC_VCCQ
R8117
R8116
10K
10K
1/16W
10K
AR8104
1/16W
10K
AR8103
IC8100-*2
IC8100-*1 THGBMBG5D1KBAIL
IC8100
THGBMBG7D2KBAIL
THGBMBG6D1KBAIL
EMMC_DATA[0-7] AR8100
0 A3 C7
1/16W DAT0 NC_22
A3 C8 A4 C8
EMMC_DATA[0] A3 C8 DAT0 NC_23 DAT1 NC_23
DAT0 NC_23 A4 C9 A5 C9
EMMC_DATA[1] A4 C9 DAT1 NC_24 DAT2 NC_24
DAT1 NC_24 A5 C10 B2 C10
EMMC_DATA[2] A5 C10 DAT2 NC_25 DAT3 NC_25
DAT2 NC_25 B2 C11 B3 C11
EMMC_DATA[3] B2 C11 DAT3 NC_26 DAT4 NC_26
EMMC_DATA[4] DAT3 NC_26 B3 C12 B4 C12
B3 C12 DAT4 NC_27 DAT5 NC_27
EMMC_DATA[5] DAT4 NC_27 B4 C13 B5 C13
B4 C13 DAT5 NC_28 DAT6 NC_28
EMMC_DATA[6] DAT5 NC_28 B5 C14 B6 C14
B5 C14 DAT6 NC_29 DAT7 NC_29
EMMC_DATA[7] AR8101 DAT6 NC_29 B6 D1 D1
0 B6 D1 DAT7 NC_30 NC_30
1/16W DAT7 NC_30 DAT5 D2 D2
D2 NC_31 NC_31
NC_31 D3 M6 D3
D3 NC_32 CLK NC_32
NC_32 M6 D4 M5 D4
M6 D4 CLK NC_33 CMD NC_33
CLK NC_33 M5 D12 D12
M5 D12 CMD NC_34 NC_34
CMD NC_34 D13 D13
D13 NC_35 NC_35
eMMC V5.0 GND NC_35 D14 A7 D14
D14 NC_36 RFU_2 NC_36
NC_36 A6 E1 E5 E1
A6 E1 VSS_1 NC_37 RFU_4 NC_37
VSS_1 NC_37 A7 E2 E8 E2
A7 E2 RFU_2 NC_38 RFU_5 NC_38
RFU_2 NC_38 C5 E3 E3
C5 E3 NC_21 NC_39 NC_39
NC_21 NC_39 E5 E12 G3 E12
E5 E12 RFU_4 NC_40 RFU_9 NC_40
RFU_4 NC_40 E8 E13 G10 E13
E8 E13 RFU_5 NC_41 RFU_10 NC_41
RFU_5 NC_41 E9 E14 K6 E14
AR8102 0 E9 E14 VSF_1 NC_42 RFU_13 NC_42
EMMC_CLK VSF_1 NC_42 E10 F1 K7 F1
E10 F1 VSF_2 NC_43 RFU_14 NC_43
DAT7
EMMC_CMD VSF_2 NC_43 DAT6 F10 F2 K10 F2
F10 F2 VSF_3 NC_44 RFU_15 NC_44
VSF_3 NC_44 G3 F3 P7 F3
G3 F3 RFU_9 NC_45 RFU_16 NC_45
TOSHIBA_EMMC5.0_16GB
TOSHIBA_EMMC5.0_4GB
SOC_EMMC_STRB EMMC_STRB RFU_9 NC_45 G10 F12 P10 F12
G10 F12 RFU_10 NC_46 RFU_17 NC_46
R8100
RFU_10 NC_46 H5 F13 F13
H5 F13 DS NC_47 NC_47
10K
EMMC_STRB DS NC_47 J5 F14 H5 F14
J5 F14 VSS_5 NC_48 DS NC_48
VSS_5 NC_48 K6 G1 G1
K6 G1 RFU_13 NC_49 NC_49
RFU_13 NC_49 K7 G2 E9 G2
K7 G2 RFU_14 NC_50 VSF_1 NC_50
RFU_14 NC_50 K10 G12 E10 G12
K10 G12 RFU_15 NC_51 VSF_2 NC_51
RFU_15 NC_51 P7 G13 F10 G13
P7 G13 RFU_16 NC_52 VSF_3 NC_52
RFU_16 NC_52 P10 G14 G14
P10 G14 RFU_17 NC_53 NC_53
RFU_17 NC_53 H1 H1
H1 NC_54 NC_54
NC_54 EMMC_STRB H2 K5 H2
H2 NC_55 RSTN NC_55
NC_55 K5 H3 H3
K5 H3 RSTN NC_56 NC_56
RSTN NC_56 H12 H12
TOSHIBA_EMMC5.0_8GB
H12 NC_57 NC_57
NC_57 H13 C6 H13
H13 NC_58 VCCQ_1 NC_58
NC_58 C6 H14 M4 H14
C6 H14 VCCQ_1 NC_59 VCCQ_2 NC_59
VCCQ_1 NC_59 M4 J1 N4 J1
EMMC_VCCQ 3.3V_EMMC M4 J1 VCCQ_2 NC_60 VCCQ_3 NC_60
VCCQ_2 NC_60 N4 J2 P3 J2
N4 J2 VCCQ_3 NC_61 VCCQ_4 NC_61
VCCQ_3 NC_61 P3 J3 P5 J3
P3 J3 VCCQ_4 NC_62 VCCQ_5 NC_62
VCCQ_4 NC_62 P5 J12 J12
P5 J12 VCCQ_5 NC_63 NC_63
VCCQ_5 NC_63 J13 J13
EMMC_CLK_BALL
EMMC_CMD_BALL
EMMC_RESET_BALL
DAT3
DAT4
DAT5
DAT6
J13 NC_64 NC_64
NC_64 J14 E6 J14
J14 EMMC_RESET_BALL NC_65 VCC_1 NC_65
NC_65 E6 K1 F5 K1
E6 K1 VCC_1 NC_66 VCC_2 NC_66
VCC_1 NC_66 F5 K2 J10 K2
F5 K2 VCC_2 NC_67 VCC_3 NC_67
VCC_2 NC_67 J10 K3 K9 K3
J10 K3 VCC_3 NC_68 VCC_4 NC_68
VCC_3 NC_68 K9 K12 K12
K9 K12 VCC_4 NC_69 NC_69
VCC_4 NC_69 K13 K13
K13 NC_70 NC_70
NC_70 K14 C2 K14
EMMC_VDDI K14 NC_71 VDDI NC_71
NC_71 C2 L1 L1
C2 L1 VDDI NC_72 NC_72
VDDI NC_72 L2 L2
L2 NC_73 NC_73
C8100 C8104 NC_73 L3 C4 L3
0.1uF 2.2uF L3 NC_74 VSSQ_1 NC_74
NC_74 E7 L12 N2 L12
16V 10V E7 L12 VSS_2 NC_75 VSSQ_2 NC_75
VSS_2 NC_75 G5 L13 N5 L13
G5 L13 VSS_3 NC_76 VSSQ_3 NC_76
VSS_3 NC_76 H10 L14 P4 L14
H10 L14 VSS_4 NC_77 VSSQ_4 NC_77
VSS_4 NC_77 K8 M1 P6 M1
K8 M1 VSS_6 NC_78 VSSQ_5 NC_78
VSS_6 NC_78 C4 M2 A6 M2
C4 M2 VSSQ_1 NC_79 VSS_1 NC_79
VSSQ_1 NC_79 N2 M3 E7 M3
N2 M3 EMMC_CLK_BALL VSSQ_2 NC_80 VSS_2 NC_80
VSSQ_2 NC_80 N5 M7 G5 M7
N5 M7 VSSQ_3 NC_81 VSS_3 NC_81
VSSQ_3 NC_81 P4 M8 H10 M8
P4 M8 VSSQ_4 NC_82 VSS_4 NC_82
VSSQ_4 NC_82 P6 M9 J5 M9
P6 M9 VSSQ_5 NC_83 VSS_5 NC_83
VSSQ_5 NC_83 M10 K8 M10
M10 NC_84 VSS_6 NC_84
NC_84 M11 M11
M11 NC_85 NC_85
NC_85 M12 M12
M12 NC_86 NC_86
NC_86 A1 M13 A1 M13
A1 M13 NC_1 NC_87 NC_1 NC_87
DAT3 NC_1 NC_87 A2 M14 A2 M14
A2 M14 NC_2 NC_88 NC_2 NC_88
DAT4 NC_2 NC_88 A8 N1 A8 N1
A8 N1 NC_3 NC_89 NC_3 NC_89
DAT7 NC_3 NC_89 A9 N3 A9 N3
A9 N3 EMMC_CMD_BALL NC_4 NC_90 NC_4 NC_90
NC_4 NC_90 A10 N6 A10 N6
A10 N6 NC_5 NC_91 NC_5 NC_91
NC_5 NC_91 A11 N7 A11 N7
A11 N7 NC_6 NC_92 NC_6 NC_92
NC_6 NC_92 A12 N8 A12 N8
A12 N8 NC_7 NC_93 NC_7 NC_93
NC_7 NC_93 A13 N9 A13 N9
A13 N9 NC_8 NC_94 NC_8 NC_94
NC_8 NC_94 A14 N10 A14 N10
A14 N10 NC_9 NC_95 NC_9 NC_95
NC_9 NC_95 B1 N11 B1 N11
B1 N11 NC_10 NC_96 NC_10 NC_96
NC_10 NC_96 B7 N12 B7 N12
B7 N12 NC_11 NC_97 NC_11 NC_97
NC_11 NC_97 B8 N13 B8 N13
B8 N13 NC_12 NC_98 NC_12 NC_98
NC_12 NC_98 B9 N14 B9 N14
B9 N14 NC_13 NC_99 NC_13 NC_99
NC_13 NC_99 B10 P1 B10 P1
B10 P1 NC_14 NC_100 NC_14 NC_100
NC_14 NC_100 B11 P2 B11 P2
B11 P2 NC_15 NC_101 NC_15 NC_101
NC_15 NC_101 B12 P8 B12 P8
B12 P8 NC_16 NC_102 NC_16 NC_102
NC_16 NC_102 B13 P9 B13 P9
Don’t Connect Power At VDDI EMMC_VDDI B13
B14
NC_17
NC_18
NC_103
NC_104
P9
P11
B14
C1
NC_17
NC_18
NC_103
NC_104
P11
P12
B14
C1
NC_17
NC_18
NC_103
NC_104
P11
P12
C1 P12 NC_19 NC_105 NC_19 NC_105
NC_19 NC_105 C3 P13 C3 P13
(Just Interal LDO Capacitor) DAT5
C3
C7
NC_20 NC_106
P13
P14
C7
NC_20
NC_22
NC_106
NC_107
P14 C5
NC_20
NC_21
NC_106
NC_107
P14
NC_22 NC_107
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS eMMC 11.09.29
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
81
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
VDDP
L2100
BLM18PG121SN1D
C13308 C2106 C2111 C2120 C2128 C2143 C2145
22uF 10uF 22uF 10uF 1uF 0.1uF 0.1uF
10V 10V 10V 10V 10V 16V 16V
IC2500
LGE7411(URSA9) 4th Layer
AG2
RB0N
AG1 AVDD_PLL
RB0P
AH3 L2101
RB1N
AH1 BLM18PG121SN1D
RB1P
AH2
RB2N
AJ3
RB2P
AJ2
RBCKN C2105 C2109 C2151
AK2 C13302
RBCKP 10uF 0.1uF 1uF
AK1 AM17 0.1uF
RB3N VX1_0-
10V 16V 10V
AL1
RB3P VX1_0+
AK17 16V
AM2 AL18
RB4N VX1_1-
AL2 AK18
RB4P VX1_1+
AM19
VX1_2-
AL19
4th Layer
VX1_2+
AK3 AL20
RC0N VX1_3-
AL3 AM20
RC0P VX1_3+
AK4 AK22 0.1uF C13008 TXDBN7_L
RC1N VX1_4- AVDD_MOD
AL4 AL21 0.1uF C13009 TXDBP7_L
RC1P VX1_4+
AM4 AK23 0.1uF C13010 TXDBN6_L L2102
RC2N VX1_5- BLM18PG121SN1D
AK5 AM22 0.1uF C13011 TXDBP6_L
RC2P VX1_5+
AM5 AK24 0.1uF C13012 TXDBN5_L
RCCKN VX1_6-
AL5 AL23 0.1uF C13013 TXDBP5_L
RCCKP VX1_6+
AK6 AL25 0.1uF C13014 TXDBN4_L C2104 C2110 C2119 C2127 C2138 C2142 C13306
RC3N VX1_7-
AL6
RC3P VX1_7+
AK25 0.1uF C13015 TXDBP4_L 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF
AK7 AM26 0.1uF C13016 TXDBN3_L 10V 10V 10V 10V 16V 16V 16V
RC4N VX1_8-
AL7 AK26 0.1uF C13017 TXDBP3_L
RC4P VX1_8+
AL27 0.1uF C13018 TXDBN2_L
VX1_9-
AK27 0.1uF C13019 TXDBP2_L
4th Layer
VX1_9+
AM7 AM28 0.1uF C13020 TXDBN1_L 4th Layer
RD0N VX1_10-
AK8 AL28 0.1uF C13021 TXDBP1_L
RD0P VX1_10+
AM8 AL29 0.1uF C13022 TXDBN0_L
RD1N VX1_11-
AL8 AM29 0.1uF C13023 TXDBP0_L
RD1P VX1_11+
AK9 AM31 0.1uF C13024 TXDAN7_L
RD2N VX1_12-
AL9 AL30 0.1uF C13025 TXDAP7_L
RD2P VX1_12+ VDDC
AK10 AL32 0.1uF C13026 TXDAN6_L VDDC
RDCKN VX1_13-
AL10 AL31 0.1uF C13027 TXDAP6_L
RDCKP VX1_13+
AM10 AK31 0.1uF C13028 TXDAN5_L
RD3N VX1_14-
AK11 AK32 0.1uF C13029 TXDAP5_L
RD3P VX1_14+
AM11 AJ30 0.1uF C13030 TXDAN4_L
RD4N VX1_15-
AL11 AJ31 0.1uF C13031 TXDAP4_L
RD4P VX1_15+
VX1_16-
AH30 0.1uF C13064 TXDAN3_L C2100 C2101 C2114 C2122 C2132 C2137 C2147 C2148 C2149 C13307 C2150
AH32 10uF
VX1_16+
0.1uF C13065 TXDAP3_L 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
AK12 AG30
RE0N VX1_17-
0.1uF C13066 TXDAN2_L 10V 10V 10V 10V 10V 10V 16V 16V 16V 16V 10V
AL12 AG31
RE0P VX1_17+
0.1uF C13067 TXDAP2_L OPT OPT OPT OPT
AK13 AE31 0.1uF C13068 TXDAN1_L
RE1N VX1_18-
AL13 AF30 0.1uF C13069 TXDAP1_L
RE1P VX1_18+
AM13 AD32 0.1uF C13070 TXDAN0_L
RE2N VX1_19- AVDDL_MOD 4th Layer
AK14 AE30 0.1uF C13071 TXDAP0_L
RE2P VX1_19+
AM14
RECKN
AL14
RECKP L2104
AK15 AH29 BLM18PG121SN1D
RE3N VX1_HTDPN HTPDAn
AL15 AG29
RE3P VX1_LOCKN
AK16
AL16
RE4N R1938 C2115 C2123 C13305
RE4P
10K C2154
0.1uF 0.1uF 0.1uF 10uF
16V 16V 16V 10V
OPT OPT
TXA0P/VX1_11P 0.1uF C13036 AE2
VBY1_RXM[0]
TXA0N/VX1_11N 0.1uF C13037 AE1
VBY1_RXP[0]
4th Layer
TXA1P/VX1_10P 0.1uF C13038 AD2 LOCKAn
VBY1_RXM[1] AVDDL_DRV
TXA1N/VX1_10N 0.1uF C13039 AE3
VBY1_RXP[1]
TXA2P/VX1_9P 0.1uF C13040 AC2
VBY1_RXM[2] +3.3V_NORMAL
TXA2N/VX1_9N 0.1uF C13041 AD3 L2105
VBY1_RXP[2] BLM18PG121SN1D
TXACLKP/VX1_8P 0.1uF C13042 AC3
VBY1_RXM[3]
0.1uF C13043 AC1
VIDEO
TXACLKN/VX1_8N VBY1_RXP[3]
C2116 C2124 C13304 C2153
0.1uF C13044 AB2
TXA3P/VX1_7P VBY1_RXM[4] 0.1uF 0.1uF 0.1uF 10uF
TXA3N/VX1_7N 0.1uF C13045 AB1
R1952
VBY1_RXP[4] 16V 16V 16V 10V
0.1uF C13046 AA2
22
TXA4P/VX1_6P VBY1_RXM[5]
0.1uF C13047 AB3 OPT OPT
TXA4N/VX1_6N
A1[GN]
A2[RD]
VBY1_RXP[5]
0.1uF C13048 Y2
TXB0P/VX1_5P VBY1_RXM[6]
TXB0N/VX1_5N 0.1uF C13049 AA3
VBY1_RXP[6] 4th Layer
SAM2333
LD1900
0.1uF C13050 Y3
TXB1P/VX1_4P VBY1_RXM[7]
0.1uF C13051 Y1
TXB1N/VX1_4N VBY1_RXP[7] DVDD_DDR
C
0.1uF C13052 W2
TXB2P/VX1_3P VBY1_RXM[8]
0.1uF C13053 W1 R1939 L2106
TXB2N/VX1_3N VBY1_RXP[8] 10K BLM18PG121SN1D
0.1uF C13054 V2
TXBCLKP/VX1_2P VBY1_RXM[9]
R1943
W3
OSD
0.1uF C13055
220
TXBCLKN/VX1_2N VBY1_RXP[9]
C2152
1%
U2 C2125 C13303
TXB3P/VX1_1P 0.1uF C13056
VBY1_RXM[10] C2117
V3 10uF
TXB3N/VX1_1N 0.1uF C13057
VBY1_RXP[10] 0.1uF 0.1uF 0.1uF
U3 E
TXB4P/VX1_0P 0.1uF C13058
VBY1_RXM[11]
Q1901
16V 16V 10V 16V
0.1uF C13059 U1 MMBT3906(NXP)
TXB4N/VX1_0N VBY1_RXP[11] OPT OPT
B
C
4th Layer
AVDDL_HDMI_TX_RX
VDD18
H15 :1.8V Domain
L2107
BLM18PG121SN1D
C2118 C2126 C2131 C2133
0.1uF 0.1uF 0.1uF 10uF
R12804
16V 16V 16V 10V
10K
+3.3V_NORMAL
Vx1_LOCKn_V/O
R12802
10K
R12803 C
Q13003
10K B
MMBT3904(NXP)
4th Layer
R12800
10K
AVDDL_LVDSRX
C E
R12801 Q13001
10K B
URSA_LOCK_V/O MMBT3904(NXP)
L13300
BLM18PG121SN1D
E
C13300 C13301
10uF 0.1uF
10V 16V
4th Layer
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
BSD-14Y-UD-128-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_LVDS INPUT
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
Vx1 LOCKAn/HTPDn
R1506
10K
R1507
[51P Vx1 VDD18
10K
C
LOCKAn
output wafer] B
R1505 Q1405
10K
C MMBT3904(NXP) E
R1504
P13000
SP14-11592-01-51Pin
100 B [41P Vx1
LOCKn_IN Q1404
MMBT3904(NXP) E output wafer]
1
2 TXDAP7_L VDD18 P13001
3 SP14-11592-01-41Pin
TXDAN7_L
4
URSA_TX_HTPD_Pullup
URSA_TX_HTPD_Pullup
+3.3V_NORMAL
5 TXDAP6_L 1
6 TXDAN6_L 2
R212 R213 R222
7 4.7K 1.5K 10K
3
URSA_TX_HTPD_Pullup
8 TXDAP5_L 4
9
G
TXDAN5_L 5
10
HTPDAn 6
S
D
11 HTPDn_IN R221
TXDAP4_L 0 Q203 7
URSA_TX_HTPD_Pullup AO3438
12 TXDAN4_L URSA_TX_HTPD_Pullup 8
13
9
14 TXDAP3_L R220
0 10
15 OPT
TXDAN3_L 11
16
12
17 TXDAP2_L 13
18 TXDAN2_L +3.3V_NORMAL 14
L/D_EN(Pin30)
19 - T-Con L/D Function
R13034 15
10K Non_AUO_Module HIGH : Enable
20 TXDAP1_L LOW or NC : Disable 16
+3.3V_NORMAL *LGD_120Hz: T240 module (UB98/95,D9)
21 R13037 0
TXDAN1_L 3D&L_DIM_EN 17
Non_AUO_Module
22 R13003 18 TXDBP7_L
10K R13007
23 TXDAP0_L OPT 10K
+3.3V_NORMAL TCON_I2C_EN 19 TXDBN7_L
OPT
24 TXDAN0_L 20
25 R13060
R13004 R13018 10K 21 TXDBP6_L
G
10K 4.7K
26 LOCKn_IN LGD_Module
OPT 22 TXDBN6_L
R13013 0 R13061 0
27 HTPDn_IN I2C_SCL1
23
S
D
R13011 10K UHD_LCD NON_AUO
28 EL_VDD_DETECT_22V Q13004
2N7002KA 24 TXDBP5_L
Non_INX_Module
29 R13055
25 TXDBN5_L
30 33 OPT
L13001 26
OPT *Pin31(BIT_SEL) BLM18PG121SN1D +3.3V_NORMAL
31 HIGH or NC : 10Bit OLED
27 TXDBP4_L
R13033 10K LOW : 8Bit
32 R13019
4.7K 28 TXDBN4_L
G
33 OPT
29
R13012 0 R13062 0
34 I2C_SDA1 30
S
D
R13006 0 R13000 10K *Pin35(PCID) UHD_LCD NON_AUO TXDBP3_L
35 3D&L_DIM_EN High:PCID enable Q13005
31
3D_EN_LGD_120Hz Low or NC : PCID diable +3.3V_NORMAL 2N7002KA TXDBN3_L
36
OPT R13056 0 R13059 32
37
*Pin38 UHD_OLED 33 OPT 33 TXDBP2_L
GND : LGD UHD 120Hz R13005 0
38 R13057 0
NC : LGD UHD 60Hz & FHD DH(16:14) 34 TXDBN2_L
R13020 0 UHD_LCD 120Hz
39 UHD_OLED
R13022 0 35
UHD_LCD T_CON_SYS_POWER_OFF R13044
40 R13021 0 10K
OLED 36
UHD_LCD R13001 0 OPT TXDBP1_L
41 INV_CTL R13016 0 37 TXDBN1_L
OLED R13002 0 Data_Format_1
42 COMPENSATION_DONE 38
Non_OLED & Non_AUO_Module
LGD_LCD
Non_OLED & Non_AUO_Module
OLED
43
R13009 R13010 39
0 0 TXDBP0_L
44 R13045 40 TXDBN0_L
10K Data Input Format[1:0]
45 LGD_LCD 41
*Mode 3 (4 Division)
46 - Data Format 0(Pin37) = Low
R13023 0
Data Format 1(Pin36) = High 42
47 +3.3V_NORMAL
T_CON_SYS_POWER_OFF OLED LED_R *Mode 2 (2 Division)
48 - Data Format 0(Pin37) = High
PANEL_VCC Data Format 1(Pin36) = Low
49 R13040
10K
50 OPT
51 R13015 0
Data_Format_0
L13000 LGD_LCD
52 51pin_12V
MLB-201209-0120P-N2
R13041
10K
LGD_LCD
EL_VDD_DETECT_22V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-130-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Output_wafer
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
LGE7411(URSA9)
F14 H27 B_DDR3_A[0]
B_DDR3_A[0-15] DDR PHY VREF
A_DDR3_A[0] A_DDR3_A0 B_DDR3_A0
B13 G31 B_DDR3_A[1] +1.5V_U_DDR +1.5V_U_DDR
A_DDR3_A[1] A_DDR3_A1 B_DDR3_A1 U_MVREFCA_A0 U_MVREFCA_A1
E13 G28 B_DDR3_A[2]
A_DDR3_A[2] A_DDR3_A2 B_DDR3_A2
D13 G29 B_DDR3_A[3]
A_DDR3_A[3] A_DDR3_A3 B_DDR3_A3 URSA_DDR_HYNIX
C14 H30 B_DDR3_A[4]
A_DDR3_A[4] A_DDR3_A4 B_DDR3_A4 R13110 R13120 DDR_VTT_URSA_1
F13 G27 B_DDR3_A[5] 1K
A_DDR3_A[5] A_DDR3_A5 B_DDR3_A5 1%
1K IC2600 URSA_DDR_HYNIX
C13 G30 B_DDR3_A[6] 1%
A_DDR3_A[6] A_DDR3_A6 B_DDR3_A6 H5TQ1G63EFR-RDC
B10 D31 B_DDR3_A[7] U_MVREFCA_A0
AR13100 AR13102 AR13104 AR13106 AR13108 AR13110 AR13112
IC2700
A_DDR3_A[7] A_DDR3_A7 B_DDR3_A7
A12 F32 B_DDR3_A[8] 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
A_DDR3_A[8] A_DDR3_A8 B_DDR3_A8 R13111 C13202 C13210 R13121 C13222 C13230 U_MVREFCA_A1
C10 D30 B_DDR3_A[9]
1K
A_DDR3_A[9] A_DDR3_A9 B_DDR3_A9 0.1uF 1000pF 1K 0.1uF 1000pF N3 M8
A14 H32 B_DDR3_A[10] 1% 1% A_DDR3_A[0] A0 VREFCA
A_DDR3_A[10] A_DDR3_A10 B_DDR3_A10 P7
B12 F31 B_DDR3_A[11] A_DDR3_A[1] A1 N3 M8
A_DDR3_A[11] A_DDR3_A11 B_DDR3_A11 P3 A_DDR3_A[0] A0 VREFCA
F15 J27 B_DDR3_A[12] A_DDR3_A[2] A2 P7
A_DDR3_A[12] A_DDR3_A12 B_DDR3_A12 N2 H1 A_DDR3_A[1] A1
C11 E30 B_DDR3_A[13] A_DDR3_A[3] A3 VREFDQ P3
A_DDR3_A[13] A_DDR3_A13 B_DDR3_A13 P8 A_DDR3_A[2] A2
C12 F30 B_DDR3_A[14] A_DDR3_A[4] A4 N2 H1
A_DDR3_A[14] A_DDR3_A14 B_DDR3_A14 P2 A_DDR3_A[3] A3 VREFDQ
D17 L29 B_DDR3_A[15] A_DDR3_A[5] A5 P8
A_DDR3_A[15] A_DDR3_A15 B_DDR3_A15 R8 L8 R13126 240 A_DDR3_A[4] A4
E14 H28 A_DDR3_A[6] A6 ZQ P2
A_DDR3_BA[0] A_DDR3_BA0 B_DDR3_BA0 B_DDR3_BA[0] R2 1% A_DDR3_A[5] A5
B14 H31 A_DDR3_A[7] A7 R8 L8 R13134 240
T8 +1.5V_U_DDR A_DDR3_A[6] A6 ZQ
A_DDR3_BA[1] A_DDR3_BA1 B_DDR3_BA1 B_DDR3_BA[1] A_DDR3_A[8]
E15 J28 A8 R2 1% +1.5V_U_DDR
A_DDR3_BA[2] A_DDR3_BA2 B_DDR3_BA2 B_DDR3_BA[2] R3 B2 A_DDR3_A[7] A7
A_DDR3_A[9] A9 VDD_1 T8
L7 D9 A_DDR3_A[8] A8
E17 L28 A_DDR3_A[10] A10/AP VDD_2 R3 B2
A_DDR3_RASZ A_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ R7 G7 A_DDR3_A[9] A9 VDD_1
C17 L30 A_DDR3_A[11] A11 VDD_3 L7 D9
A_DDR3_CASZ A_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ N7 K2 A_DDR3_A[10] A10/AP VDD_2
C16 K30 A_DDR3_A[12] A12/BC VDD_4 R7 G7
A_DDR3_WEZ A_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ T3 K8 A_DDR3_A[11] A11 VDD_3
F17 L27 A_DDR3_A[13] NC_7 VDD_5 N7 K2
A_DDR3_ODT A_DDR3_ODT B_DDR3_ODT B_DDR3_ODT N1 A_DDR3_A[12] A12/BC VDD_4
C15 J30 VDD_6 T3 K8
A_DDR3_CKE A_DDR3_CKE B_DDR3_CKE B_DDR3_CKE M7 N9 A_DDR3_A[13] NC_7 VDD_5
B11 E31 A_DDR3_A[15] NC_5 VDD_7 N1
A_DDR3_RESET A_DDR3_RESETB B_DDR3_RESETB B_DDR3_RESET R1 A_DDR3_A[14] VDD_6
B16 K31 VDD_8 M7 N9
A_DDR3_MCLK A_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK +1.5V_U_DDR +1.5V_U_DDR M2 R9 A_DDR3_A[15] NC_5 VDD_7
A16 K32 A_DDR3_BA[0] BA0 VDD_9 R1
A_DDR3_MCLKZ B_DDR3_MCLKZ +1.5V_U_DDR N8 VDD_8
A_DDR3_MCLKZ B_DDR3_MCLKZ U_MVREFCA_B0 U_MVREFCA_B1
C9 C30 A_DDR3_BA[1] BA1 +1.5V_U_DDR M2 R9
M3
R13123R13122
A_DDR3_CSB1 A_DDR3_CSB1 B_DDR3_CSB1 B_DDR3_CSB1 A_DDR3_MCLK A_DDR3_BA[0] BA0 VDD_9
A9 C32 A_DDR3_BA[2] BA2 N8
56
A1 +1.5V_U_DDR
A_DDR3_CSB2 A_DDR3_CSB2 B_DDR3_CSB2 B_DDR3_CSB2 C13120
C13233 A_DDR3_BA[1] BA1
VDDQ_1 M3
A_DDR3_DQ[0-15] B_DDR3_DQ[0-15] R13108 0.1uF 0.01uF J7 A8 A_DDR3_BA[2] BA2
R13118
56
A_DDR3_DQ[0] D23 U29 B_DDR3_DQ[0] CK VDDQ_2 A1
1K 1K K7 C1 VDDQ_1
A_DDR3_DQ0 B_DDR3_DQ0
A_DDR3_DQ[1] A19 N32 B_DDR3_DQ[1] 1% 1% A_DDR3_MCLKZ CK VDDQ_3 J7 A8
A_DDR3_DQ1 B_DDR3_DQ1 K9 C9 A_DDR3_MCLK CK VDDQ_2
A_DDR3_DQ[2] E22 T28 B_DDR3_DQ[2] A_DDR3_CKE CKE VDDQ_4 K7 C1
A_DDR3_DQ2 B_DDR3_DQ2 D2 A_DDR3_MCLKZ CK VDDQ_3
A_DDR3_DQ[3] B18 M31 B_DDR3_DQ[3] VDDQ_5 K9 C9
A_DDR3_DQ3 B_DDR3_DQ3 Place CLOSE TO MCLK VIA L2 E9 A_DDR3_CKE CKE VDDQ_4
A_DDR3_DQ[4] C23 U30 B_DDR3_DQ[4] R13109 C13201 C13209 R13119 C13221 C13229 A_DDR3_CSB1 CS VDDQ_6 D2
A_DDR3_DQ4 B_DDR3_DQ4 1K 0.1uF 1000pF 1K K1 F1 VDDQ_5
A_DDR3_DQ[5] C18 M30 B_DDR3_DQ[5] 0.1uF 1000pF APPLYING URSA9 DDR CLK EMI SIMUALTION A_DDR3_ODT ODT VDDQ_7 L2 E9
1% 1% J3 H2
A_DDR3_DQ5 B_DDR3_DQ5 A_DDR3_CSB2 CS VDDQ_6
A_DDR3_DQ[6] B22 T31 B_DDR3_DQ[6] A_DDR3_RASZ RAS VDDQ_8 K1 F1
A_DDR3_DQ6 B_DDR3_DQ6 K3 H9 A_DDR3_ODT ODT VDDQ_7
A_DDR3_DQ[7] A18 M32 B_DDR3_DQ[7] A_DDR3_CASZ CAS VDDQ_9 J3 H2
A_DDR3_DQ7 B_DDR3_DQ7 L3 A_DDR3_RASZ RAS VDDQ_8
A_DDR3_DQ[8] E19 N28 B_DDR3_DQ[8] A_DDR3_WEZ WE K3 H9
A_DDR3_DQ8 B_DDR3_DQ8 J1 A_DDR3_CASZ CAS VDDQ_9
A_DDR3_DQ[9] B21 R31 B_DDR3_DQ[9] NC_1 L3
A_DDR3_DQ9 B_DDR3_DQ9 T2 J9 A_DDR3_WEZ WE
A_DDR3_DQ[10] F18 M27 B_DDR3_DQ[10] A_DDR3_RESET RESET NC_2 J1
A_DDR3_DQ10 B_DDR3_DQ10 L1 NC_1
A_DDR3_DQ[11] C22 T30 B_DDR3_DQ[11] NC_3 T2 J9
A_DDR3_DQ11 B_DDR3_DQ11 L9 A_DDR3_RESET RESET NC_2
A_DDR3_DQ[12] D20 P29 B_DDR3_DQ[12] NC_4 L1
A_DDR3_DQ12 B_DDR3_DQ12 F3 T7 NC_3
A_DDR3_DQ[13] F22 T27 B_DDR3_DQ[13] A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14] L9
A_DDR3_DQ13 B_DDR3_DQ13 G3 URSA_DDR_NANYA
NC_4 URSA_DDR_NANYA
A_DDR3_DQ[14] E18 M28 B_DDR3_DQ[14] A_DDR3_DQS0B DQSL IC2600-*1
NT5CB64M16FP-EK
F3 T7 IC2700-*1
NT5CB64M16FP-EK
A_DDR3_DQ14 B_DDR3_DQ14 A_DDR3_DQS2 DQSL NC_6 A_DDR3_A[14]
A_DDR3_DQ[15] D22 T29 B_DDR3_DQ[15] G3
A_DDR3_DQ15 B_DDR3_DQ15 C7 A9 N3
A0 VREFCA
M8 A_DDR3_DQS2B DQSL N3
A0 VREFCA
M8
B19 N31 A_DDR3_DQS1 DQSU VSS_1 P7
A1
P7
A1
A_DDR3_DM0 A_DDR3_DM0 B_DDR3_DM0 B_DDR3_DM0 B7 B3 P3
N2
A2
H1
P3
N2
A2
H1
E21 R28 A_DDR3_DQS1B DQSU VSS_2 P8
A3 VREFDQ C7 A9 P8
A3 VREFDQ
A_DDR3_DM1 A_DDR3_DM1 B_DDR3_DM1 B_DDR3_DM1 E1 P2
A4
A5 A_DDR3_DQS3 DQSU VSS_1 P2
A4
A5
VSS_3 R8
A6 ZQ
L8
B7 B3 R8
A6 ZQ
L8
E7 G8 R2
T8
A7 A_DDR3_DQS3B DQSU VSS_2 R2
T8
A7
A21 R32 A_DDR3_DM0 DML VSS_4 R3
A8
B2 E1 R3
A8
B2
A_DDR3_DQS0 A_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_DQS0 D3 J2 L7
A9
A10/AP
VDD_1
VDD_2
D9 VSS_3 L7
A9
A10/AP
VDD_1
VDD_2
D9
B20 P31 A_DDR3_DM1 DMU VSS_5 R7
A11 VDD_3
G7
E7 G8 R7
A11 VDD_3
G7
A_DDR3_DQS0B A_DDR3_DQS0B B_DDR3_DQS0B B_DDR3_DQS0B J8 N7
T3
A12/BC VDD_4
K2
K8 A_DDR3_DM2 DML VSS_4 N7
T3
A12/BC VDD_4
K2
K8
C20 P30 A_DDR3_DQ[0-15] VSS_6 NC_6 VDD_5
N1 D3 J2 NC_6 VDD_5
N1
A_DDR3_DQS1 A_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_DQS1
A_DDR3_DQ[0] E3 M1 M7
NC_5
VDD_6
VDD_7
N9 A_DDR3_DM3 DMU VSS_5 M7
NC_5
VDD_6
VDD_7
N9
C19 N30 DQL0 VSS_7 VDD_8
R1
J8 VDD_8
R1
A_DDR3_DQS1B A_DDR3_DQS1B B_DDR3_DQS1B B_DDR3_DQS1B
A_DDR3_DQ[1] F7 M9 M2
N8
BA0 VDD_9
R9
A_DDR3_DQ[16-31] VSS_6 M2
N8
BA0 VDD_9
R9
DQL1 VSS_8 M3
BA1 A_DDR3_DQ[16] E3 M1 M3
BA1
A_DDR3_DQ[16-31] B_DDR3_DQ[16-31]
A_DDR3_DQ[2] F2 P1 BA2
VDDQ_1
A1 DQL0 VSS_7 BA2
VDDQ_1
A1
A_DDR3_DQ[16] B27 AA31 B_DDR3_DQ[16] DQL2 VSS_9 J7
CK VDDQ_2
A8 A_DDR3_DQ[17] F7 M9 J7
CK VDDQ_2
A8
A_DDR3_DQ16 B_DDR3_DQ16
A_DDR3_DQ[3] F8 P9 K7
K9
CK VDDQ_3
C1
C9 DQL1 VSS_8 K7
K9
CK VDDQ_3
C1
C9
A_DDR3_DQ[17] A24 V32 B_DDR3_DQ[17] DQL3 VSS_10 CKE VDDQ_4
D2
A_DDR3_DQ[18] F2 P1 CKE VDDQ_4
D2
A_DDR3_DQ17 B_DDR3_DQ17
A_DDR3_DQ[4] H3 T1 L2
CS
VDDQ_5
VDDQ_6
E9 DQL2 VSS_9 L2
CS
VDDQ_5
VDDQ_6
E9
A_DDR3_DQ[18] C27 AA30 B_DDR3_DQ[18] DQL4 VSS_11 K1
ODT VDDQ_7
F1 A_DDR3_DQ[19] F8 P9 K1
ODT VDDQ_7
F1
A_DDR3_DQ18 B_DDR3_DQ18
A_DDR3_DQ[5] H8 T9 J3
K3
RAS VDDQ_8
H2
H9 DQL3 VSS_10 J3
K3
RAS VDDQ_8
H2
H9
A_DDR3_DQ[19] C24 V30 B_DDR3_DQ[19] DQL5 VSS_12 L3
CAS VDDQ_9 A_DDR3_DQ[20] H3 T1 L3
CAS VDDQ_9
A_DDR3_DQ19 B_DDR3_DQ19
A_DDR3_DQ[6] G2 WE
NC_1
J1 DQL4 VSS_11 WE
NC_1
J1
A_DDR3_DQ[20] A28 AB32 B_DDR3_DQ[20] DQL6 T2
RESET NC_2
J9 A_DDR3_DQ[21] H8 T9 T2
RESET NC_2
J9
A_DDR3_DQ20 B_DDR3_DQ20
A_DDR3_DQ[7] H7 NC_3
L1
L9 DQL5 VSS_12 NC_3
L1
L9
A_DDR3_DQ[21] E24 V28 B_DDR3_DQ[21] DQL7 F3
NC_4
T7
A_DDR3_DQ[22] G2 F3
NC_4
T7
A_DDR3_DQ21 B_DDR3_DQ21 +1.5V_U_DDR A_DDR3_CKE B1 G3
DQSL
DQSL
NC_7
DQL6 G3
DQSL
DQSL
NC_7
A_DDR3_DQ[22] B28 AB31 B_DDR3_DQ[22] VSSQ_1 A_DDR3_DQ[23] H7
A_DDR3_DQ22 B_DDR3_DQ22
A_DDR3_DQ[8] D7 B9 C7
B7
DQSU VSS_1
A9
B3 DQL7 C7
B7
DQSU VSS_1
A9
B3
A_DDR3_DQ[23] B23 U31 B_DDR3_DQ[23] R13112 DQU0 VSSQ_2 DQSU VSS_2
E1 B1 DQSU VSS_2
E1
A_DDR3_DQ23 B_DDR3_DQ23
R13102
1K
A_DDR3_DQ[9] C3 D1 E7
DML
VSS_3
VSS_4
G8 VSSQ_1 E7
DML
VSS_3
VSS_4
G8
1K DQU1 VSSQ_3 A_DDR3_DQ[24] D7 B9
A_DDR3_DQ[24] D25 W29 B_DDR3_DQ[24] D3
DMU VSS_5
J2 D3
DMU VSS_5
J2
A_DDR3_DQ24 B_DDR3_DQ24
A_DDR3_DQ[10] C8 D8 E3
VSS_6
J8
M1 DQU0 VSSQ_2 E3
VSS_6
J8
M1
A_DDR3_DQ[25] E27 AA28 B_DDR3_DQ[25] A_DDR3_RESET DQU2 VSSQ_4 F7
DQL0 VSS_7
M9
A_DDR3_DQ[25] C3 D1 F7
DQL0 VSS_7
M9
A_DDR3_DQ25 B_DDR3_DQ25
A_DDR3_DQ[11] C2 E2 F2
DQL1
DQL2
VSS_8
VSS_9
P1 DQU1 VSSQ_3 F2
DQL1
DQL2
VSS_8
VSS_9
P1
A_DDR3_DQ[26] C25 W30 B_DDR3_DQ[26] DQU3 VSSQ_5 F8
DQL3 VSS_10
P9 A_DDR3_DQ[26] C8 D8 F8
DQL3 VSS_10
P9
A_DDR3_DQ26 B_DDR3_DQ26
A_DDR3_DQ[12] A7 E8 H3
H8
DQL4 VSS_11
T1
T9 DQU2 VSSQ_4 H3
H8
DQL4 VSS_11
T1
T9
A_DDR3_DQ[27] D28 AB29 B_DDR3_DQ[27] DQU4 VSSQ_6 G2
DQL5 VSS_12 A_DDR3_DQ[27] C2 E2 G2
DQL5 VSS_12
A_DDR3_DQ27 B_DDR3_DQ27
A_DDR3_DQ[13] A2 F9 H7
DQL6
DQL7 DQU3 VSSQ_5 H7
DQL6
DQL7
A_DDR3_DQ[28] E26 Y28 B_DDR3_DQ[28] DQU5 VSSQ_7 VSSQ_1
B1 A_DDR3_DQ[28] A7 E8 VSSQ_1
B1
A_DDR3_DQ28 B_DDR3_DQ28
A_DDR3_DQ[14] B8 G1 D7
C3
DQU0 VSSQ_2
B9
D1 DQU4 VSSQ_6 D7
C3
DQU0 VSSQ_2
B9
D1
A_DDR3_DQ[29] E28 AB28 B_DDR3_DQ[29] DQU6 VSSQ_8 C8
DQU1 VSSQ_3
D8
A_DDR3_DQ[29] A2 F9 C8
DQU1 VSSQ_3
D8
A_DDR3_DQ29 B_DDR3_DQ29
A_DDR3_DQ[15] A3 G9 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2 DQU5 VSSQ_7 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
A_DDR3_DQ[30] E25 W28 B_DDR3_DQ[30] DQU7 VSSQ_9 A7
A2
DQU4 VSSQ_6
E8
F9
A_DDR3_DQ[30] B8 G1 A7
A2
DQU4 VSSQ_6
E8
F9
A_DDR3_DQ30 B_DDR3_DQ30 B8
DQU5 VSSQ_7
G1 DQU6 VSSQ_8 B8
DQU5 VSSQ_7
G1
A_DDR3_DQ[31] C28 AB30 B_DDR3_DQ[31] A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
A_DDR3_DQ[31] A3 G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
A_DDR3_DQ31 B_DDR3_DQ31 +1.5V_U_DDR B_DDR3_CKE DQU7 VSSQ_9
B24 V31
A_DDR3_DM2 A_DDR3_DM2 B_DDR3_DM2 B_DDR3_DM2
B26 Y31
A_DDR3_DM3 A_DDR3_DM3 B_DDR3_DM3 B_DDR3_DM3 R13113
R13103 1K
1K
B25 W31
A_DDR3_DQS2 A_DDR3_DQS2 B_DDR3_DQS2 B_DDR3_DQS2
A25 W32 B_DDR3_RESET
A_DDR3_DQS2B A_DDR3_DQS2B B_DDR3_DQS2B B_DDR3_DQS2B
D26 Y29
A_DDR3_DQS3 A_DDR3_DQS3 B_DDR3_DQS3 B_DDR3_DQS3
C26 Y30
A_DDR3_DQS3B A_DDR3_DQS3B B_DDR3_DQS3B B_DDR3_DQS3B
* DDR_VTT
DDR_VTT_URSA_0
FOR NARROW PCB PATTERN SIZE
URSA_DDR_HYNIX
+1.5V_U_DDR +3.3V_NORMAL
IC13100 URSA_DDR_HYNIX AR13101 AR13103 AR13105 AR13107 AR13109 AR13111 AR13113
IC2900
AP2303MPTR-G1 [EP] 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
L13101
C13114 IC2800 U_MVREFCA_B1
10uF
VIN
1 8
NC_3 CIS21J121 10V H5TQ1G63EFR-RDC
C13123
U_MVREFCA_B0
THERMAL
DDR_VTT_URSA 10uF N3 M8
GND NC_2 B_DDR3_A[0] A0 VREFCA
9
10V 2 7
P7
N3 M8 B_DDR3_A[1] A1
L13100 VREFEN VCNTL B_DDR3_A[0] A0 VREFCA P3
3 6 B_DDR3_A[2]
CIS21J121 P7 A2
1% 100K B_DDR3_A[1] A1 N2 H1
R13100 VOUT NC_1 P3 B_DDR3_A[3] A3 VREFDQ
4 5 B_DDR3_A[2] A2 P8
B_DDR3_A[4] A4
1% 100K
N2 H1
R13101
C13110 C13111 C13113 P2
C13122
B_DDR3_A[3] A3 VREFDQ
0.1uF
10uF 10uF 10uF B_DDR3_A[5]
16V
P8 A5
10V 10V 10V B_DDR3_A[4] A4 R8 L8 R13135 240
P2 B_DDR3_A[6] A6 ZQ
B_DDR3_A[5] A5 R2 1%
R8 L8 R13127 240 B_DDR3_A[7] A7 +1.5V_U_DDR
B_DDR3_A[6] A6 ZQ T8
R2 1% B_DDR3_A[8] A8
B_DDR3_A[7] A7 R3 B2
T8 +1.5V_U_DDR B_DDR3_A[9] A9 VDD_1
B_DDR3_A[8] A8 L7 D9
R3 B2 B_DDR3_A[10] A10/AP VDD_2
B_DDR3_A[9] A9 VDD_1 R7 G7
L7 D9 B_DDR3_A[11] A11 VDD_3
B_DDR3_A[10] A10/AP VDD_2 N7 K2
R7 G7 B_DDR3_A[12] A12/BC VDD_4
B_DDR3_A[11] A11 VDD_3 T3 K8
N7 K2 B_DDR3_A[13] NC_7 VDD_5
B_DDR3_A[12] A12/BC VDD_4 N1
T3 K8 B_DDR3_A[14] VDD_6
B_DDR3_A[13] NC_7 VDD_5 M7 N9
DDR_VTT_URSA N1 B_DDR3_A[15] NC_5 VDD_7
DDR_VTT_URSA_0
VDD_6 R1
L13102 VDD_8
M7 N9
BLM18PG121SN1D
B_DDR3_A[15] NC_5 VDD_7 M2 R9
+1.5V_U_DDR R1 B_DDR3_BA[0] BA0 VDD_9
VDD_8 N8 +1.5V_U_DDR
C13181 C13179 C13189 C13151 C13105 M2 R9 B_DDR3_BA[1] BA1
1uF 0.1uF 0.1uF 0.1uF B_DDR3_BA[0] BA0 VDD_9 M3
0.1uF
10V 16V 16V 16V 16V N8 B_DDR3_BA[2] BA2
B_DDR3_BA[1] BA1 A1
M3 +1.5V_U_DDR VDDQ_1
R13125R13124
C13121 B_DDR3_MCLK J7 A8
B_DDR3_BA[2] BA2
56
0.1uF C13234 A1 B_DDR3_MCLK CK VDDQ_2
VDDQ_1 K7 C1
0.01uF J7 A8 B_DDR3_MCLKZ CK VDDQ_3
K9 C9
56
DDR_VTT_URSA DDR_VTT_URSA_1 CK VDDQ_2
K7 C1 B_DDR3_CKE CKE VDDQ_4
L13103 B_DDR3_MCLKZ CK VDDQ_3 D2
BLM18PG121SN1D K9 C9 VDDQ_5
B_DDR3_CKE CKE VDDQ_4 L2 E9
Place CLOSE TO MCLK VIA D2 B_DDR3_CSB2 CS VDDQ_6
VDDQ_5 K1 F1
C13112 C13132 C13158 C13174 C13106
1uF 0.1uF 0.1uF
C13118 C13119 L2 E9 B_DDR3_ODT ODT VDDQ_7
0.1uF 0.1uF 0.1uF 0.1uF APPLYING URSA9 DDR CLK EMI SIMUALTION B_DDR3_CSB1 CS VDDQ_6 J3 H2
10V 16V 16V 16V 16V 16V 16V K1 F1 B_DDR3_RASZ RAS VDDQ_8
B_DDR3_ODT ODT VDDQ_7 K3 H9
J3 H2 B_DDR3_CASZ CAS VDDQ_9
B_DDR3_RASZ RAS VDDQ_8 L3
K3 H9 B_DDR3_WEZ WE
B_DDR3_CASZ CAS VDDQ_9 J1
L3 NC_1
B_DDR3_WEZ WE T2 J9
J1 B_DDR3_RESET RESET NC_2
NC_1 L1
T2 J9 NC_3
B_DDR3_RESET RESET NC_2 L9
L1 NC_4
NC_3 F3 T7
L9 B_DDR3_DQS2 DQSL NC_6 B_DDR3_A[14]
NC_4
URSA_DDR_NANYA
G3 URSA_DDR_NANYA
F3 T7 IC2800-*1
NT5CB64M16FP-EK
B_DDR3_DQS2B DQSL IC2900-*1
NT5CB64M16FP-EK
B_DDR3_DQS0 DQSL NC_6 B_DDR3_A[14]
Decap removed G3
C7 A9
B_DDR3_DQS0B DQSL N3
A0 VREFCA
M8 N3
A0 VREFCA
M8
P7
A1 B_DDR3_DQS3 DQSU VSS_1 P7
A1
P3
N2
A2
H1
B7 B3 P3
N2
A2
H1
C7 A9 P8
A3 VREFDQ B_DDR3_DQS3B DQSU VSS_2 P8
A3 VREFDQ
B_DDR3_DQS1 DQSU VSS_1 P2
A4
A5
E1 P2
A4
A5
B7 B3 R8
A6 ZQ
L8 VSS_3 R8
A6 ZQ
L8
B_DDR3_DQS1B DQSU VSS_2
R2
T8
A7 E7 G8 R2
T8
A7
E1 R3
A8
B2 B_DDR3_DM2 DML VSS_4 R3
A8
B2
VSS_3 L7
A9
A10/AP
VDD_1
VDD_2
D9 D3 J2 L7
A9
A10/AP
VDD_1
VDD_2
D9
E7 G8 R7
A11 VDD_3
G7
B_DDR3_DM3 DMU VSS_5 R7
A11 VDD_3
G7
B_DDR3_DM0 DML VSS_4
N7
T3
A12/BC VDD_4
K2
K8
J8 N7
T3
A12/BC VDD_4
K2
K8
D3 J2 NC_6 VDD_5
N1 B_DDR3_DQ[16-31] VSS_6 NC_6 VDD_5
N1
B_DDR3_DM1 DMU VSS_5 M7
NC_5
VDD_6
VDD_7
N9
B_DDR3_DQ[16] E3 M1 M7
NC_5
VDD_6
VDD_7
N9
J8 VDD_8
R1 DQL0 VSS_7 VDD_8
R1
B_DDR3_DQ[0-15] VSS_6
M2
N8
BA0 VDD_9
R9 B_DDR3_DQ[17] F7 M9 M2
N8
BA0 VDD_9
R9
B_DDR3_DQ[0] E3 M1 M3
BA1 DQL1 VSS_8 M3
BA1
DQL0 VSS_7
BA2
VDDQ_1
A1
B_DDR3_DQ[18] F2 P1 BA2
VDDQ_1
A1
B_DDR3_DQ[1] F7 M9 J7
CK VDDQ_2
A8 DQL2 VSS_9 J7
CK VDDQ_2
A8
DQL1 VSS_8
K7
K9
CK VDDQ_3
C1
C9
B_DDR3_DQ[19] F8 P9 K7
K9
CK VDDQ_3
C1
C9
B_DDR3_DQ[2] F2 P1 CKE VDDQ_4
D2 DQL3 VSS_10 CKE VDDQ_4
D2
DQL2 VSS_9 L2
CS
VDDQ_5
VDDQ_6
E9
B_DDR3_DQ[20] H3 T1 L2
CS
VDDQ_5
VDDQ_6
E9
+1.5V_U_DDR B_DDR3_DQ[3] F8 P9 K1
ODT VDDQ_7
F1 DQL4 VSS_11 K1
ODT VDDQ_7
F1
DQL3 VSS_10
J3
K3
RAS VDDQ_8
H2
H9
B_DDR3_DQ[21] H8 T9 J3
K3
RAS VDDQ_8
H2
H9
Close to DDR Power pin B_DDR3_DQ[4] H3 T1 L3
CAS VDDQ_9 DQL5 VSS_12 L3
CAS VDDQ_9
DQL4 VSS_11
WE
NC_1
J1
B_DDR3_DQ[22] G2 WE
NC_1
J1
B_DDR3_DQ[5] H8 T9 T2
RESET NC_2
J9 DQL6 T2
RESET NC_2
J9
DQL5 VSS_12 NC_3
L1
L9
B_DDR3_DQ[23] H7 NC_3
L1
L9
B_DDR3_DQ[6] G2 F3
NC_4
T7 DQL7 F3
NC_4
T7
DQL6 G3
DQSL
DQSL
NC_7 B1 G3
DQSL
DQSL
NC_7
B_DDR3_DQ[7] H7 VSSQ_1
DQL7
C7
DQSU VSS_1
A9 B_DDR3_DQ[24] D7 B9 C7
DQSU VSS_1
A9
C13104 C13109 C13117 C13128 C13137 C13146 C13156 C13164 C13172 C13178 C13186 C13194 C13198 C13206 C13214 C13218 C13226 C13517 B1
B7
DQSU VSS_2
B3
DQU0 VSSQ_2
B7
DQSU VSS_2
B3
C13518 C13519 C13520 VSSQ_1 E7
VSS_3
E1
G8
B_DDR3_DQ[25] C3 D1 E7
VSS_3
E1
G8
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 10pF B_DDR3_DQ[8] D7 B9 D3
DML VSS_4
J2 DQU1 VSSQ_3 D3
DML VSS_4
J2
10pF 10pF 10pF DQU0 VSSQ_2
DMU VSS_5
VSS_6
J8 B_DDR3_DQ[26] C8 D8 DMU VSS_5
VSS_6
J8
16V 16V 16V 16V 16V 16V 16V 16V 10V 16V 16V 10V 16V 16V 16V 16V 10V 50V B_DDR3_DQ[9] C3 D1
E3
DQL0 VSS_7
M1
DQU2 VSSQ_4
E3
DQL0 VSS_7
M1
50V 50V 50V DQU1 VSSQ_3
F7
F2
DQL1
DQL2
VSS_8
VSS_9
M9
P1
B_DDR3_DQ[27] C2 E2
F7
F2
DQL1
DQL2
VSS_8
VSS_9
M9
P1
B_DDR3_DQ[10] C8 D8 F8
DQL3 VSS_10
P9 DQU3 VSSQ_5 F8
DQL3 VSS_10
P9
DQU2 VSSQ_4
H3
H8
DQL4 VSS_11
T1
T9
B_DDR3_DQ[28] A7 E8 H3
H8
DQL4 VSS_11
T1
T9
B_DDR3_DQ[11] C2 E2 G2
DQL5 VSS_12 DQU4 VSSQ_6 G2
DQL5 VSS_12
DQU3 VSSQ_5 H7
DQL6
DQL7
B_DDR3_DQ[29] A2 F9 H7
DQL6
DQL7
B_DDR3_DQ[12] A7 E8 VSSQ_1
B1 DQU5 VSSQ_7 VSSQ_1
B1
DQU4 VSSQ_6
D7
C3
DQU0 VSSQ_2
B9
D1
B_DDR3_DQ[30] B8 G1 D7
C3
DQU0 VSSQ_2
B9
D1
B_DDR3_DQ[13] A2 F9 C8
DQU1 VSSQ_3
D8 DQU6 VSSQ_8 C8
DQU1 VSSQ_3
D8
DQU5 VSSQ_7 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
B_DDR3_DQ[31] A3 G9 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
B_DDR3_DQ[14] B8 G1 A7
A2
DQU4 VSSQ_6
E8
F9
DQU7 VSSQ_9 A7
A2
DQU4 VSSQ_6
E8
F9
DQU6 VSSQ_8 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1
B_DDR3_DQ[15] A3 G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
DQU7 VSSQ_9
+1.5V_U_DDR
Close to DDR Power pin
C13102 C13107 C13115 C13126 C13135 C13144 C13154 C13162 C13170 C13176 C13184 C13192 C13196 C13204 C13212 C13216 C13224 C13232 C13100 C13101
0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
16V 16V 10V 16V 16V 16V 16V 10V 16V 16V 16V 16V 16V 16V 10V 16V 16V 16V 10V 10V
4th layer
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13103 C13108 C13116
0.1uF 0.1uF 0.1uF
16V 16V 16V
BSD-14Y-UD-131-HD
+1.5V_U_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
Close to DDR Power pin SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
Decap removed FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
C13195 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
0.1uF THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
16V
2013.12.17
4th layer
URSA7_DDR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
URSA Option
+3.3V_NORMAL
GPIO PORT CAPACITORS -> FOR PREVENT 680MHz EMISSION NOISE FROM URSA9’S GPIO PORTS
Clock for URSA9 +3.3V_NORMAL URSA Reset
URSA_RX_LVDS
DIV_BIT(1/0) MODULE DIVISION +3.3V_NORMAL
URSA_BIT0_1
LGD_Module
URSA_BIT1_1
URSA_BIT2_1
R1911 10K
R1913 10K
R1915 10K
R1917 10K
R1909 10K
0/0 NON DIVISION
C1903
SW1901 0/1 2 DIVISION
URSA_PRINT_OFF
JTP-1127WEM +3.3V_NORMAL
5pF
50V
DIV_BIT0_1
DIV_BIT1_1
4 DIVISION
R1964 10K
R1966 10K
R1968 10K
R1970 10K
1/0
R1962 10K
1 2 OPT URSA_OPT_0
X-TAL_1
Rx Interface
OPT
OPT
C1902 1/1 8 DIVISION
XIN_URSA URSA_OPT_1
GND_1
22uF R1919
Module Type
3 4 10K HIGH ;Debug PRINT_OFF URSA_BIT0
10V URSA9_RST_PULLUP URSA_OPT_4
LOW ; Debug PRINT_ON DIV_BIT0
URSA_BIT1
Tx Lane
R1925
DIV_BIT1
URSA_RESET
2
1
URSA_BIT2
24MHz
X1900
0
1N4148W
URSA_OPT_4
1M
R1924
D1900
URSA_OPT_5 BIT [2/1/0] Tx Lane
C1904
R1923
100V
URSA_RESET_MICOM
3
4
5pF
50V
10K
URSA_BIT1_0
URSA_OPT_6
URSA_BIT2_0
0 0/0/0 4K@120 (16lane)
URSA_RX_VX1
URSA_BIT0_0
10K
10K
10K
10K
10K
OS_Module
X-TAL_2
GND_2
R1930 0/0/1 4k@60 (8lane)
XO_URSA 0/1/0 5k@120 (20lane)
R1916
R1910
R1918
R1912
R1914
0/1/1 OLED ULTRA HD
URSA_PRINT_ON
10K
DIV_BIT1_0
10K
10K
DIV_BIT0_0
10K
10K
1/0/0 FHD@120 (4lane)
1/0/1 FHD@60 (2lane)
R1969
R1963
R1971
R1965
R1967
1/1/0 Reserved
1/1/1 Reserved
IC2500
LGE7411(URSA9)
AF29 AG25
URSA_RESET RESET I2C_HSC_SDA/VSYNC_LIKE2
AH25
I2C_HSC_SCL/VSYNC_LIKE3
R3
XIN_URSA XTALO
R4 AH28
SPI Flash XO_URSA XTALI SPI1_CK/PWM2/GPIO58 URSA_OPT_0
URSA9_PQ_DEBUG
AJ27
SPI1_DI/PWM3/GPIO59 DIV_BIT0
AJ24 AJ29
+3.3V_NORMAL I2CS_SDA SPI2_CK/PWM0/GPIO56 DIV_BIT1 +3.3V_NORMAL
I2CS_SDA AR13201 AH24 AF27
I2CS_SCL 33 I2CS_SCL SPI2_DI/PWM1/GPIO57 URSA_OPT_4
URSA9_PQ_DEBUG AG28 OPT
R13211
C1927 C1928 SPI3_CK/DIM10/GPIO54 URSA_OPT_5 R1936
P1906 56pF 56pF AH26 AH27 10K
12507WS-04L 50V 50V I2CM_SDA SPI3_DI/DIM11/GPIO55 URSA_OPT_6
10K
OPT AG24 AG27
I2CM_SCL/VSYNC_LIKE1 SPI4_CK/DIM8/GPIO52
AG26 R1935 33
R1937
IC1901 1
B4
SPI4_DI/DIM9/GPIO53 10K
+3.3V_NORMAL R13212
MX25L3235E 33 A4
GPIO[0][UART2_TX]
AF28
2
GPIO[1][UART2_RX] VSYNC_LIKE/PWM5/GPIO40
URSA9_PQ_DEBUG
CS VCC C1901
3 B5
1 8 0.1uF R13213 GPIO[2][UART1_TX]
SPI_CZ 16V 33
A5 AG23 +3.3V_NORMAL
4 GPIO[3][UART1_RX] DIM0/GPIO[32] DIM0
AG20
SO/SIO1 HOLD/SIO3 URSA9_PQ_DEBUG Change pin from A5 to C4
DIM1/GPIO[33] DIM1 OPT
R1904 33 5 C1905 AH23 R13204
2 7
SPI_DO 0.1uF DIM2/GPIO[34] DIM2 10K
10K R1903 16V AD28 AH20
URSA9_PQ_DEBUG SPI_CZ SPI_CZ DIM3/GPIO[35]
1K WP/SIO2 SCLK AD30 AG21
R1905 3 6 SPI_CK SPI_CK DIM4/GPIO[36] URSA_OPT_1
FLASH_WP_URSA SPI_CK AR13200 AC31 AH22 R13205
URSA_BIT0 10K
U_SPI_WP_f_URSA SPI_DI 33 SPI_DI DIM5/GPIO[37]
URSA9_SYS_DEBUG
AD29 AG22
URSA_BIT1
GND SI/SIO0 +3.3V_NORMAL SPI_DO SPI_DO DIM6/GPIO[38]
R1932 1K 4 5 SPI_DI URSA9_SYS_DEBUG R13215 33 AH21
URSA_BIT2
FRC_FLASH_WP DIM7/GPIO[39]
R13214
P1907 AE28
U_SPI_WP_f_SoC 12507WS-04L URSA9_SYS_DEBUG INT_R21/GPIO[41]
AE27
10K
INT_R20/GPIO[42]
A3
1 GPIO43/TCON0
B3
R13216 GPIO44/TCON1
2 33 A2
GPIO45/TCON2
URSA9_SYS_DEBUG C4 C3 Not Used Net (UB98/D9)
IRE GPIO46/TCON3
3 B2
GPIO47/TCON4 RXASCL_URSA9
URSA9 UART1_RX B1 RXASDA_URSA9
4 GPIO48/TCON5
TCON_I2C_EN Ready C2 RXBSCL_URSA9
URSA9_SYS_DEBUG GPIO49/TCON6 RXBSDA_URSA9
5
C1906
AC27 C1
0.1uF GND_1 GPIO50/TCON7
16V
AD27
GND_2
AG4
GPIO[18]/TCON8
A7 AG5 HDMI OUTPUT_1 DDC to URSA9
NC_1 GPIO[19]/TCON9
B6 AH4
Chip Config B7
NC_2 GPIO[20]/TCON10
AH5
RXASCL_URSA9
RXASDA_URSA9
NC_3 GPIO[21]/TCON11
C5 AH6
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98) Debugging for URSA9 C6
NC_4
NC_5
GPIO[22]/TCON12
GPIO[23]/TCON13
AJ4
CHIP_CONF:{DIM2,DIM1,DIM0} C7 AJ5 Data_Format_1
CHIP_CONF=3’d7:111:boot from SPI Flash I2C_S Port NC_6 GPIO24/TCON14
D4 AJ6 Data_Format_0
NC_7 GPIO25/TCON15
P1905 D5
12507WS-04L NC_8 C1915 C1916
D6 AH16 0.01uF 0.01uF
WAFER-STRAIGHT
URSA_DEBUG
NC_9 GPIO[4] 25V 25V
D7 AG16
+3.3V_NORMAL DIM0 1 SW1902 NC_10 GPIO[5] HDMI OUTPUT_0 DDC to URSA9
JS2235S E4 Y5
NC_11 GPIO[6] RXBSCL_URSA9
OPT 10K E5 Y4
2 RXBSDA_URSA9
NC_12 GPIO[7]
10K R1908 I2C_SCL3 1 6 I2C_SDA3 E6 AB4
DIM1 R1922 R1958 R1959 NC_13 GPIO[8]
R1902 3 33
SCL2_+3.3V_DB 0 0 E7 AB5 For DFT JIG
URSA_MP URSA_MP
OPT 10K URSA_DEBUG
I2CS_SCL 2 5 I2CS_SDA NC_14 GPIO[9] OPT
R1960 URSA_DEBUG_SW R1961
F4 AG17 R13207 33
R13206 R13209
R1921 33 0 0 NC_15 GPIO[10]/PWM_DIM_IN[0] OPT 100K 100K
4 SDA2_+3.3V_DB
10K R1907 URSA_DEBUG
OPT
3 4
OPT F5 AH17 R13208 33
SCL2_+3.3V_DB SDA2_+3.3V_DB NC_16 GPIO[11]/PWM_DIM_IN[1]
R1901 DIM2 5 M5 AG18 10K R13201
NC_17 GPIO[12]
OPT 10K M6 AJ20 10K R13200 URSA9_Vx1_RX_HTPD_GPIO
NC_18 GPIO[13] MUST CONNECTED PULL-DOWN
M7 AH18 R13210 33
10K R1906 NC_19 GPIO[14] URSA9_CONNECT
N5 AG19 C1917
R1900 0.01uF
NC_20 GPIO[15] 25V
R7 AH19
NC_21 GPIO[16]
P7 AJ21
NC_22 GPIO[17]
N7 URSA_LOCK_V/O
NC_23
N6 C1918
FLASH_WP_URSA
C1920
NC_24 100pF 0.01uF
50V 25V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-132-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC2500
IC2500 LGE7411(URSA9)
LGE7411(URSA9)
D18 D24
A8 T13 VSS_285 VSS_389
VSS_81 VSS_186 G18 F24
B8 R13 VSS_286 VSS_390
VSS_82 VSS_187 H18 G24
C8 P13 VSS_287 VSS_391
VSS_83 VSS_188 J18 H24
D8 N13 VSS_288 VSS_392
VSS_84 VSS_189 L18 J24
E8 M13 VSS_289 VSS_393
VSS_85 VSS_190 N18 K24
F8 U13 VSS_290 VSS_394
VSS_86 VSS_191 P18 L24
G8 V13 VSS_291 VSS_395
VSS_87 VSS_192 R18 M24
H8 W13 VSS_292 VSS_396
VSS_88 VSS_193 T18 N24
J8 Y13 VSS_293 VSS_397
VSS_89 VSS_194 U18 P24
K8 AA13 VSS_294 VSS_398
IC2500 VSS_90 VSS_195 V18 R24
L8 AB13 VSS_295 VSS_399
LGE7411(URSA9) VSS_91 VSS_196 W18 T24
M8 AD13 VSS_296 VSS_400
VSS_92 VSS_197 Y18 U24
VDDC N8 AE13 VSS_297 VSS_401
VSS_93 VSS_198 AA18 V24
P8 AF13 VSS_298 VSS_402
VSS_94 VSS_199 AB18 W24
A6 K1 R8 AG13 VSS_299 VSS_403
VDDC_1 VSS_1 VSS_95 VSS_200 AE18 Y24
M9 T1 T8 AH13 VSS_300 VSS_404
VDDC_2 VSS_2 VSS_96 VSS_201 AF18 AA24
M10 K2 U8 AJ13 VSS_301 VSS_405
VDDC_3 VSS_3 VSS_97 VSS_202 AJ18 AB24
M11 P2 V8 G14 VSS_302 VSS_406
VDDC_4 VSS_4 VSS_98 VSS_203 F19 AC24
N9 T2 W8 H14 VSS_303 VSS_407
VDDC_5 VSS_5 VSS_99 VSS_204 G19 AD24
N10 AF2 Y8 J14 VSS_304 VSS_408
VDDC_6 VSS_6 VSS_100 VSS_205 H19 AE24
N11 K3 AA8 K14 VSS_305 VSS_409
VDDC_7 VSS_7 VSS_101 VSS_206 J19 AF24
P9 T3 L14 VSS_306 VSS_410
VDDC_8 VSS_8 VSS_207 K19
P10 AF3 AC8 P14 VSS_307
VDDC_9 VSS_9 VSS_102 VSS_208 L19 AL24
P11 AG3 AD8 R14 VSS_308 VSS_411
VDDC_10 VSS_10 VSS_103 VSS_209 N19 F25
R9 G4 AE8 T14 VSS_309 VSS_412
VDDC_11 VSS_11 VSS_104 VSS_210 P19 G25
R10 H4 AF8 U14 VSS_310 VSS_413
VDDC_12 VSS_12 VSS_105 VSS_211 R19 H25
R11 J4 AG8 V14 VSS_311 VSS_414
VDDC_13 VSS_13 VSS_106 VSS_212 T19 J25
T9 K4 AH8 W14 VSS_312 VSS_415
VDDC_14 VSS_14 VSS_107 VSS_213 U19 K25
T10 P4 AJ8 Y14 VSS_313 VSS_416
VDDC_15 VSS_15 VSS_108 VSS_214 V19 L25
T11 T4 B9 AA14 VSS_314 VSS_417
VDDC_16 VSS_16 VSS_109 VSS_215 W19 M25
U9 U4 D9 AB14 VSS_315 VSS_418
VDDC_17 VSS_17 VSS_110 VSS_216 Y19 N25
U10 V4 E9 AE14 VSS_316 VSS_419
VDDC_18 VSS_18 VSS_111 VSS_217 AB19 P25
U11 W4 F9 AF14 VSS_317 VSS_420
VDDC_19 VSS_19 VSS_112 VSS_218 AC19 R25
V9 AA4 G9 AG14 VSS_318 VSS_421
VDDC_20 VSS_20 VSS_113 VSS_219 AD19 T25
V10 AC4 H9 AH14 VSS_319 VSS_422
VDDC_21 VSS_21 VSS_114 VSS_220 AE19 U25
V11 AD4 J9 AJ14 VSS_320 VSS_423
VDDC_22 VSS_22 VSS_115 VSS_221 AF19 V25
W9 AE4 K9 A15 VSS_321 VSS_424
VDDC_23 VSS_23 VSS_116 VSS_222 AK19 W25
W10 AF4 L9 B15 VSS_322 VSS_425
VDDC_24 VSS_24 VSS_117 VSS_223 A20 Y25
W11 G5 D15 VSS_323 VSS_426
VDDC_25 VSS_25 VSS_224 E20 AA25
Y9 H5 VSS_324 VSS_427
VDDC_26 VSS_26 F20 AB25
J5 AD9 G15 VSS_325 VSS_428
VSS_27 VSS_118 VSS_225 G20 AC25
K5 AE9 H15 VSS_326 VSS_429
AVDDL_HDMI_TX_RX VSS_28 VSS_119 VSS_226 H20 AD25
L5 AF9 J15 VSS_327 VSS_430
VSS_29 VSS_120 VSS_227 J20 AE25
AG9 K15 VSS_328 VSS_431
VSS_121 VSS_228 L20 AF25
L3 P5 AH9 L15 VSS_329 VSS_432
AVDDL_HDMITX_1 VSS_30 VSS_122 VSS_229 N20 AM25
AVDDL_LVDSRX L4 R5 AJ9 M15 VSS_330 VSS_433
AVDDL_HDMITX_2 VSS_31 VSS_123 VSS_230 P20 A26
AA9 T5 N15 VSS_331 VSS_434
AVDDL_RX_1 VSS_32 VSS_231 R20 F26
AA10 U5 D10 P15 VSS_332 VSS_435
AVDDL_RX_2 VSS_33 VSS_124 VSS_232 T20 G26
AB9 V5 E10 R15 VSS_333 VSS_436
AVDDL_RX_3 VSS_34 VSS_125 VSS_233 U20 H26
F10 T15 VSS_334 VSS_437
VSS_126 VSS_234 V20 J26
Y10 W5 G10 U15 VSS_335 VSS_438
AVDDL_DVI_1 VSS_35 VSS_127 VSS_235 W20 K26
Y11 AA5 H10 V15 VSS_336 VSS_439
AVDDL_DVI_2 VSS_36 VSS_128 VSS_236 AE20 L26
DVDD_DDR AC5 J10 W15 VSS_337 VSS_440
VSS_37 VSS_129 VSS_237 AF20 M26
M14 AD5 K10 Y15 VSS_338 VSS_441
DVDD_DDR_1 VSS_38 VSS_130 VSS_238 AK20 N26
N14 AE5 L10 AA15 VSS_339 VSS_442
AVDDL_MOD DVDD_DDR_2 VSS_39 VSS_131 VSS_239 P26
AF5 AB10 AE15 VSS_443
VSS_40 VSS_132 VSS_240 D21 R26
Y20 F6 AC10 AF15 VSS_340 VSS_444
AVDDL_MOD_1 VSS_41 VSS_133 VSS_241 F21 T26
Y21 G6 AD10 AG15 VSS_341 VSS_445
AVDDL_MOD_2 VSS_42 VSS_134 VSS_242 G21 U26
Y22 H6 AE10 AH15 VSS_342 VSS_446
AVDDL_MOD_3 VSS_43 VSS_135 VSS_243 H21 V26
AA19 J6 AF10 AJ15 VSS_343 VSS_447
AVDDL_MOD_4 VSS_44 VSS_136 VSS_244 J21 W26
AA20 K6 AG10 E16 VSS_344 VSS_448
AVDDL_DRV AVDDL_MOD_5 VSS_45 VSS_137 VSS_245 K21 Y26
AA21 L6 AH10 F16 VSS_345 VSS_449
AVDDL_DRV_1 VSS_46 VSS_138 VSS_246 L21 AA26
AA22 AJ10 G16 VSS_346 VSS_450
AVDDL_DRV_2 VSS_139 VSS_247 T21 AB26
AB20 P6 A11 H16 VSS_347 VSS_451
AVDDL_DRV_3 VSS_47 VSS_140 VSS_248 U21 AC26
AB21 R6 D11 J16 VSS_348 VSS_452
AVDDL_DRV_4 VSS_48 VSS_141 VSS_249 V21 AD26
AB22 T6 E11 VSS_349 VSS_453
AVDDL_DRV_5 VSS_49 VSS_142 W21 AE26
U6 F11 L16 VSS_350 VSS_454
AVDD_MOD VSS_50 VSS_143 VSS_250 AE21 AF26
AC20 V6 G11 N16 VSS_351 VSS_455
AVDD_MOD_1 VSS_51 VSS_144 VSS_251 AF21 AJ26
AC21 W6 H11 P16 VSS_352 VSS_456
AVDD_MOD_2 VSS_52 VSS_145 VSS_252 AK21 AL26
AD21 Y6 J11 R16 VSS_353 VSS_457
AVDD_MOD_3 VSS_53 VSS_146 VSS_253 D27
AD20 AA6 K11 T16 VSS_458
AVDD_MOD_LDO VSS_54 VSS_147 VSS_254 F27
VDDP AB6 L11 U16 VSS_459
VSS_55 VSS_148 VSS_255 K27
AC18 AC6 AA11 V16 VSS_460
VDDP_1 VSS_56 VSS_149 VSS_256 G22 N27
AD17 AD6 AB11 W16 VSS_354 VSS_461
VDDP_2 VSS_57 VSS_150 VSS_257 H22 P27
AD18 AE6 AC11 Y16 VSS_355 VSS_462
VDDP_3 VSS_58 VSS_151 VSS_258 J22 R27
AF6 AE11 AA16 VSS_356 VSS_463
VSS_59 VSS_152 VSS_259 U27
AD11 AG6 AF11 AE16 VSS_464
AVDD_DVI_1 VSS_60 VSS_153 VSS_260 L22 V27
AD12 AG11 AF16 VSS_357 VSS_465
AVDD_DVI_2 VSS_154 VSS_261 M22 W27
AC12 F7 AH11 VSS_358 VSS_466
AVDD_HDMITX_1 VSS_61 VSS_155 T22 Y27
AC13 G7 AJ11 VSS_359 VSS_467
AVDD_HDMITX_2 VSS_62 VSS_156 U22 AA27
AD15 H7 AJ16 VSS_360 VSS_468
AVDD_RX_1 VSS_63 VSS_262 V22 AB27
AC16 J7 D12 AM16 VSS_361 VSS_469
AVDD_RX_2 VSS_64 VSS_157 VSS_263 W22
AC17 K7 E12 A17 VSS_362
AVDD_RX_3 VSS_65 VSS_158 VSS_264 AC22 F28
AD16 L7 F12 B17 VSS_363 VSS_470
AVDD_RX_4 VSS_66 VSS_159 VSS_265 AD22 K28
AVDD_PLL G12 G17 VSS_364 VSS_471
VSS_160 VSS_266 AE22 P28
AD14 H12 H17 VSS_365 VSS_472
AVDD_XTAL VSS_161 VSS_267 AF22 U28
AC14 J12 J17 VSS_366 VSS_473
AVDD_PLL_1 VSS_162 VSS_268 AL22 AC28
+1.5V_U_DDR
AC15 T7 K12 K17 VSS_367 VSS_474
AVDD_PLL_2 VSS_67 VSS_163 VSS_269 AK28
M18 U7 L12 L17 VSS_475
AVDD_DDR0_1 VSS_68 VSS_164 VSS_270 A29
M19 V7 M12 N17 VSS_476
AVDD_DDR0_2 VSS_69 VSS_165 VSS_271 A23 C29
M20 W7 N12 P17 VSS_368 VSS_477
AVDD_DDR0_3 VSS_70 VSS_166 VSS_272 E23 D29
M21 Y7 P12 R17 VSS_369 VSS_478
AVDD_DDR0_4 VSS_71 VSS_167 VSS_273 F23 E29
M16 AA7 R12 T17 VSS_370 VSS_479
AVDD_DDR0_5 VSS_72 VSS_168 VSS_274 G23 F29
M17 AB7 T12 U17 VSS_371 VSS_480
AVDD_DDR0_6 VSS_73 VSS_169 VSS_275 H23 J29
AC7 U12 V17 VSS_372 VSS_481
VSS_74 VSS_170 VSS_276 J23 M29
P21 AD7 V12 W17 VSS_373 VSS_482
AVDD_DDR1_1 VSS_75 VSS_171 VSS_277 K23 R29
R21 AE7 W12 Y17 VSS_374 VSS_483
AVDD_DDR1_2 VSS_76 VSS_172 VSS_278 V29
P22 AF7 Y12 AA17 VSS_484
AVDD_DDR1_3 VSS_77 VSS_173 VSS_279 M23 AA29
R22 AG7 AA12 AB17 VSS_375 VSS_485
AVDD_DDR1_4 VSS_78 VSS_174 VSS_280 AC29
N21 AH7 AB12 AE17 VSS_486
AVDD_DDR1_5 VSS_79 VSS_175 VSS_281 P23 AK29
N22 AJ7 AE12 AF17 VSS_376 VSS_487
AVDD_DDR1_6 VSS_80 VSS_176 VSS_282 A30
AF12 VSS_488
VSS_177 T23 B30
AG12 VSS_377 VSS_489
VSS_178 V23 AC30
AH12 AJ17 VSS_378 VSS_490
VSS_179 VSS_283 W23 AK30
AJ12 AL17 VSS_379 VSS_491
VSS_180 VSS_284 Y23 AM30
VSS_380 VSS_492
AA23 A31
VSS_381 VSS_493
AB23 B31
G13 VSS_382 VSS_494
VSS_181 AC23 C31
H13 VSS_383 VSS_495
VSS_182 AD23 J31
J13 VSS_384 VSS_496
VSS_183 AE23 L31
K13 VSS_385 VSS_497
VSS_184 AF23 AD31
L13 VSS_386 VSS_498
VSS_185 AJ23 AF31
VSS_387 VSS_499
AM23 AH31
VSS_388 VSS_500
B32
VSS_501
E32
VSS_502
J32
VSS_503
L32
VSS_504
P32
VSS_505
U32
VSS_506
Y32
VSS_507
AE32
VSS_508
AG32
VSS_509
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-14Y-UD-133-HD
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_Power
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
MAX 4.7A
+12V
+1.5V URSA DDR +1.15V URSA9 Core
+1.5V_U_DDR
L13411 POWER_ON/OFF2_1
BLM18PG121SN1D
R13404
10K
C13443
10uF R13407
R13408
1/16W
25V 39K
IC13403
5.1K
R13424 R1
1%
BD9D321EFJ [EP] 1/16W
10K 5%
1%
1/16W
91K
R13406
C13403
R13411R13409
[EP]
GND2
GND1
NC_3
TRIP
EN VIN
1/16W 1/16W
1 8 1000pF
5.1K
VO
16V 50V R2
1%
1/16W
27K
R13405
THERMAL
1%
R13410
0.1uF
1%
1/16W
20K
R13421 R13422 FB BOOT C13447
28
27
26
25
24
9
2 7
RF FB
0
R1 1 23
5%
18K 3.6K L13412
1% 1% 2.2uH THERMAL
VREG SW PGOOD 2 29 22 GND
3 6 +12V
C13444 R13401 1K
100pF PS064T-2R2MS EN 3 21 MODE
50V POWER_ON/OFF2_3 16V
SS GND 0.1uF IC13402
4
3A 5 C13448
22uF
C13449
22uF
ZD13401 VBST 4
TPS53513RVER
20 VREG L13402
R13403
10V 10V 2.5V
R13423 C13405 NC_1 VDD
OPT 5 19
4.7
22K C13445 C13446 C13402 R13400
1uF 2200pF 2K SW_1 NC_2
1% 6 18
10V 50V
0.1uF 1/16W C13408 C13407 C13409
SW_2 7 17 VIN_3
R2 16V 5% 1uF 10uF 10uF
VDDC
25V 25V 25V
L13403 SW_3 8 16 VIN_2
Vout=0.765*(1+R1/R2)=1.516V 1.0uH
SW_4 9
8A 15 VIN_1
R13402
10
11
12
13
14
1/10W
C13451
ZD13400
3.3
C13450 C13400 C13401 C13411
5%
C13406
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
2.5V
0.1uF 22uF 22uF
OPT
22uF 2200pF
150uF 50V
6.3V
C13404
470pF
50V
Vout=0.6*(1+R1/R2)=1.19V_FOR 1.17V at URSA9 VIA
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-134-HD
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
M3 CLIP M4 CLIP M5 OPT M6 CLIP
EAG64250901 EAG64250901 EAG64250901 EAG64250901
M7 OPT M8 CLIP M10 CLIP
EAG64250901 EAG64250901 EAG64250901
CLIP 1 - PUSH TYPE
M13535 ESD_READY M13508 ESD_READY M13514 ESD_READY M13517 ESD_USB M13520ESD_AV_COMP M13523 ESD_READY M13526 EMI_URSA
MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214
M13506 ESD_READY M13509 ESD_READY M13515 ESD_READY M13518 ESD_READY M13521 ESD_READY M13524ESD_AV_COMP M13527 ESD_READY
MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214
M13534 ESD_READY M13507 ESD_READY M13510 ESD_READY M13513 ESD_USB M13516 ESD_READY M13519 ESD_READY M13522 ESD_READY M13525 ESD_READY
MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214 MDS62110214
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 14.06.10
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CLIP TYPE
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
M13500 EMI_URSA M13502 EMI_URSA M13504 OPT
MDS62110214 MDS62110214 MDS62110214
M13501 EMI_URSA M13503 OPT M13505 M13505_BR/TW
MDS62110214 MDS62110214 MDS62110214
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
3 A. Video error Picture broken/ Freezing 3
4 Color error 4
Vertical/Horizontal bar, residual image,
5 5
light spot, external device color error
6 No power 6
B. Power error Off when on, off while viewing, power
7 7
auto on/off
8 No audio/Normal video 8
C. Audio error
9 Wrecked audio/discontinuation/noise 9
10 Remote control & Local switch checking 10
11 MR15 operating checking 11
D. Function error
12 Wifi operating checking 12
13 External device recognition error 13
14 E. Noise Circuit noise, mechanical noise 14
15 F. Exterior error Exterior defect 15
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date
symptom
No video/ Normal audio Revised date 1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, Vx1 Cable, Speaker Cable, IR B/D Cable,,,)
☞A1 ☞A18
No video Normal Y Check Back Light Y Check Power Normal Y Replace T-con/Main
Normal audio On Board or module
audio On with naked eye Board voltage
24V, 12V,3.5V etc. And Adjust VCOM
N N N
Move to No Check Power Board 24V output Repair Power
☞A18
video/No audio Board or parts
Replace Inverter
Normal Y
or module
voltage
End
N
Repair Power
Board or parts
※Precaution ☞A4 & A2
Always check & record S/W Version and White
Replace Main Board Re-enter White Balance value
Balance value before replacing the Main Board
1
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date
symptom
No video/ No audio Revised date 2/16
☞A18
Check various Check and
Y
No Video/ voltages of Power Normal
replace
No audio Board ( 3.5V,12V,20V voltage?
MAIN B/D
or 24V…)
N End
Replace Power
Board and repair
parts
2
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date
symptom
Picture broken/ Freezing Revised date 3/16
. By using Digital signal level meter
☞ A3
. By using Diagnostics menu on OSD
Check RF Signal level ( Advanced→ Programmes → Programme Tuning →Signal Test )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Y Check whether other equipments have problem or not.
Normal
(By connecting RF Cable at other equipment)
Signal?
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
☞ A4
Check RF Cable
Normal Y Check SVC N Check Y
Connection Close
1. Reconnection Picture? S/W Version Bulletin? Tuner soldering
2. Install Booster
Y N
N
S/W Upgrade
N Contact with signal distributor
Normal
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture? Replace
Main B/D
Y
Close
Close
3
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date
symptom
Color error Revised date 4/16
☞A6 ☞ A7
※ Check Y
Check color by input
and replace
-External Input Y Y
Color Link Cable Color Color
-COMPONENT Replace Main B/D Replace module
error? (V by one) error? error?
-AV
and contact
-HDMI N N N
condition
Check error End
color input
mode
☞A8 Check
External Input/ External Y
external
Check Test pattern Component device/Cable Replace Main B/D
device and
error normal
cable
N
Request repair
for external
device/cable
N
Check external External Y
HDMI
device and device/Cable Replace Main B/D
error
cable normal
4
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
A. Video error Established
Error date
symptom Vertical / Horizontal bar, residual image,
light spot, external device color error Revised date 5/16
Vertical/Horizontal bar, residual image, light spot Replace
Module
☞A6
☞ A7 N
Check color condition by input Check external
Check and
-External Input Screen Y device Y Screen N Screen
-Component Normal? replace Link Replace Main B/D
normal? connection normal? (adjust VCOM) normal?
-HDMI Cable
condition
N N For LGD panel Y
Y
Replace Main B/D
Replace Request repair End End
module for external
☞A8 device
Check Test pattern
For other panel
External device screen error-Color error
Check screen
Check S/W Version N condition by input External
Check
-External Input Input Connect other external N
version
-Component error device and cable Screen Replace
-HDMI/DVI (Check normal operation of normal? Main B/D
Y External Input, Component,
Component RGB and HDMI/DVI by
Y
S/W Upgrade error connecting Jig, pattern
Generator ,Set-top Box etc.
Request repair for
external device
Y
Connect other external
Normal N HDMI/
device and cable N
screen? DVI
(Check normal operation of Screen Replace
External Input, Component, normal? Main B/D
Y RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
End
5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date
symptom
No power Revised date 6/16
☞A17 ☞A18
DC Power on Replace
Check Power LED Y Normal N Check Power Y
by pressing Power Key OK? Power
Logo LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red or Turn On
N Y
. Operating: Turn Off
Check Power cord Replace Main B/D
was inserted properly
☞A18
N Measure voltage of each output of Power B/D
Normal?
Y
Y Y
※ Normal
voltage?
Replace Main B/D
Close Normal
Check ST-BY 3.5V
Y
voltage? N
☞A18 Replace Power B/D
N
Replace Power
B/D
6
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date
symptom
Off when on, off while viewing, power auto on/off Revised date 7/16
Check outlet
☞A19
N Y
Check A/C cord Error? Check Power Off CPU
Replace Main B/D Normal? End
Mode Abnormal
N
Check for all 3- phase
power out Y Abnormal Replace Power B/D
1
Fix A/C cord & Outlet ☞A18
and check each 3
(If Power Off mode
phase out
is not displayed) Normal Y
Replace Main B/D
Check Power B/D voltage?
voltage
N
※ Caution
Check and fix exterior Replace Power B/D
of Power B/D Part
* Please refer to the all cases which Status Power off List Explanation
"POWEROFF_REMOTEKEY" Power off by REMOTE CONTROL
can be displayed on power off mode.
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
Normal "POWEROFF_ONTIMER" Power off by ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF_UNKNOWN" Power off by unknown status except listed case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
7
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date
symptom
No audio/ Normal video Revised date 8/16
☞A20 ☞A21+A18
No audio
Check user N Check audio B+
Normal Y
menu > Off 24V of Power
Screen normal voltage
Speaker off Board
Y N
Cancel OFF Replace Power Board and repair parts
Check N
Disconnection Replace MAIN Board End
Speaker
disconnection
Y
Replace Speaker
8
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date
symptom
Wrecked audio/ discontinuation/noise Revised date 9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Wrecked audio/
☞A21+A18
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (18V)
connector
Check input all audio
signal Y
Signal
-RF Y
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV N
Wrecked audio/
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
Request repair to external Wrecked audio/ Replace Main B/D End
cable/ANT provider Discontinuation/
Noise only
for External Input
(In case of N
External Input Connect and check Normal
signal error) other external audio?
Check and fix device
external device Y
Check and fix external device
9
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
D. Function error Established
Error date
symptom
Remote control & Local switch checking Revised date 10/16
1. Remote control(R/C) operating error Replace
Main B/D
☞A22 ☞A22 ☞A22
Check & Repair N Check B+ Y Y
Check R/C itself Normal Y Normal Normal Check IR Normal
operating? Cable connection operating? 3.5V Voltage? Signal?
Operation Output signal
Connector solder On Main B/D
N
Y N N
☞A18
Check R/C Operating Check & Replace Close Check 3.5v on Power B/D Repair/Replace
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal Y
operating? Close
Explain the customer
cause is interference
from light in room. N
Replace R/C
10
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
D. Function error Established
Error date
symptom
MR15 operating checking Revised date 11/16
2. MR15(Magic Remocon) operating error
☞A4
Check the N Check MR15
RF Receiver ver Normal Y Press the Is show ok N Turn off/on the
INSTART menu is “00.00”? itself Operation operating? set and press
wheel message?
the wheel
N
Y
Y
☞A23
Check & Replace Close
Check & Repair Battery of MR15
RF assy
connection
Normal Y
☞A4 operating? Close
Is show ok N Press the back
RF Receiver ver N message? key about 5sec
Close N
is “00.00”?
Y
Replace
MR15
Y Close
Down load the Firmware
* If you conduct the loop at 3times, change the MR15.
* INSTART MENU12.RF
Remocon Test3. Receiver
Firmware download
11
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
D. Function error Established
Error date
symptom
Wifi operating checking Revised date 12/16
3.Wifi operating error
☞A4 ☞A24
Check the Wi-Fi MAC value N Check the Wifi wafer Normal N Replace
INSTART menu is “NG”? Voltage?
18pin Main B/D
Y
☞A24 Y
Check & Repair Close
Wifi cable
connection
☞A4
Wi-Fi MAC value N
is “NG”? Close
Y
Change the Wifi
assy
12
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error D. Function error date
symptom
External device recognition error Revised date 14/16
Y Check technical
Check External Input and
Signal information Technical N
input Component Replace Main B/D
input? - Fix information information?
Recognition error
signal
- S/W Version
N Y
HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information
14
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error E. Noise date
symptom
Circuit noise, mechanical noise Revised date 15/16
Identify Check
Circuit
nose location of Replace PSU
noise
type noise
Mechanical Check location of
noise noise
※ When the nose is severe, replace the module
※ Mechanical noise is a natural (For models with fix information, upgrade the
phenomenon, and apply the 1st level S/W or provide the description)
OR
description. When the customer does not
agree, apply the process by stage. ※ If there is a “Tak Tak” noise from the
※ Describe the basis of the description cabinet, refer to the KMS fix information and
in “Part related to nose” in the Owner’s then proceed as shown in the solution manual
Manual. (For models without any fix information,
provide the description)
15
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error F. Exterior defect date
symptom
Exterior defect Revised date 16/16
Zoom part with Module
Replace module
exterior damage damage
Cabinet
Replace cabinet
damage
Remote
controller Replace remote controller
damage
Stand
Replace stand
dent
16
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of Standard Repair Process Detail Technical Manual
No. Error symptom Content Page Remarks
1 A. Video error_ No video/Normal Check LCD back light with naked eye A1
2 audio Check White Balance value A2
TUNER input signal strength checking
4 A3
method
A. Video error_ video error /Video
5 lag/stop Version checking method A4
6 Tuner Checking Part A5
A. Video error _Vertical/Horizontal bar,
7 Connection diagram A6
residual image, light spot
Check Link Cable (Vx1) reconnection
8 A7
A. Video error_ Color error condition
9 Adjustment Test pattern - ADJ Key A8
10 Exchange Main Board (1) A-1/5
11 Exchange Main Board (2) A-2/5
12 Defected Type caused by T-Con/ Exchange Power Board (PSU) A-3/5
Inverter/ Module
13 Exchange Module (1) A-4/5
14 Exchange Module (2) A-5/5
Continue to the next page
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of Standard Repair Process Detail Technical Manual
Continued from previous page
No. Error symptom Content Page Remarks
16 Check front Power Indicator A17
B. Power error_ No power
17 Check power input Voltage & ST-BY 3.5V A18
B. Power error_Off when on, off
18 POWER OFF MODE checking method A19
while viewing
Checking method in menu when there is
19 A20
C. Audio error_ No audio/Normal no audio
video Voltage and speaker checking method
20 A21
when there is no audio
Remote controller operation checking
21 A22
method
D. Function error
Motion Remote /Wifi operation checking
22 A23
method
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom A. Video error_No video/Normal audio date
Revised
Content Check LCD back light with naked eye A1
date
<55/65UF95>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from locations.
A1
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom A. Video error_No video/Normal audio date
Revised
Content Check White Balance value A2
date
Entry
Entrymethod
method
1.1.Press
Pressthe
theADJ
ADJbutton
buttonononthe
theremote
remotecontroller
controllerforforadjustment.
adjustment.
2.2.Enter
Enterinto
intoWhite
WhiteBalance
Balanceofofitem
item6.11.
3.3.After
Afterrecording
recordingthe
theR,R,G,G,B B(GAIN,
(GAIN,Cut)
Cut)value
valueofofColor
ColorTemp
Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm),re-enterre-enterthe
thevalue
valueafter
afterreplacing
replacingthe
theMAIN
MAINBOARD.
BOARD.
A2
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom Established
A. Video error_Video error, video lag/stop date
TUNER input signal strength checking method Revised
Content date A3
Advanced Programmes Programme Tunning
Signal Test
When the signal is strong, use the
attenuator (-10dB, -15dB, -20dB etc.)
A3
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom A. Video error_Video error, video lag/stop date
Version checking method Revised
Content date A4
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller for adjustment
A4
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom A. Video error_Video error, video lag/stop Established
date
Revised
Content TUNER checking part A5
date
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.
A5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom A. Video error _Vertical/Horizontal bar, Established
residual image, light spot date
Revised
Content Connection diagram (1) date A6
As the part connecting to the external input, check
the screen condition by signal
A6
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom A. Video error_Color error date
Revised
Content Check Link Cable (Vx1) reconnection condition date A7
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom A. Video error_Color error Established
date
Adjustment Test pattern - ADJ Key Revised
Content date A8
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
Solder defect, CNT Broken T-Con
T-Con Defect,
Defect,
Solder
T-Con CNT
CNT
defect,CNT
Defect, Broken
Broken
CNTBroken
Broken Abnormal Power Section
Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack
A - 1/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Main Board (2)
Abnormal Power Section Abnormal Power Section Solder defect, Short/Crack
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
GRADATION Noise GRADATION
A - 2/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange Power Board (PSU)
No Light Dim Light
Dim Light Dim Light
No picture/Sound Ok
A - 3/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (1)
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Crosstalk Press damage Crosstalk
Un-repairable Cases
In this case please exchange the module.
Press damage
A - 4/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (2)
Vertical Block Vertical Line Vertical Block
Source TAB IC Defect Source TAB IC Defect Source TAB IC Defect
Horizontal
TAB ICBlock
Horizontal Block Horizontal line
Gate Defect Gate TAB IC Defect
Gate TAB IC Defect Gate TAB IC Defect Gate TAB IC Defect
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom B. Power error _No power date
Revised
Content Check front Power Indicator date A17
<55/65UF95>
ST-BY condition: On or Off
Power ON condition: Turn Off
A17
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom B. Power error _No power Established
date
Revised
Content Check power input voltage and ST-BY 3.5V A18
date
Check the DC 24V, 12V, 3.5V.
’15 28Pin map (LPB)
UHD
Pin Pin
No LED No
49,55,65,79
1 PWR_ON DRV_ON 2
3 P_DIM#1 P_DIM#2 4
5 3.5V GND 6
7 3.5V 3.5V 8
9 GND GND 10
11 12V 12V 12
13 12V 12V 14
15 12V GND 16
17 GND 24V 18
19 24V 24V 20
21 24V 24V 22
23 GND GND 24
25 SCLK GND 26
27 SIN V_SYNC 28
A18
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Standard Repair Process Detail Technical Manual
Error symptom B. Power error _Off when on, off whiling viewing Established
date
Revised
Content POWER OFF MODE checking method date A19
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
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Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error symptom C. Audio error_No audio/Normal video Established
date
Revised
Content Checking method in menu when there is no audio date A20
Checking method
1. Press the Setting button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Out
4. Select Internal TV Speaker or Internal TV Speaker+Audio Out
A20
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Established
Error symptom C. Audio error_No audio/Normal video date
Voltage and speaker checking method Revised
Content date A21
when there is no audio
1 PWR ON 2 DVR_ON
3 P_DIM #1 4 PDIM #2
5 3.5V 6 GND
7 3.5V 8 3.5V
② ② 9 GND 10 GND
11 12V 12 12V
13 12V 14 12V
15 12V 16 GND ①
17 GND 18 24V
③
19 24V 20 24V
21 24V 22 24V
23 GND 24 GND
25 SCLK 26 GND
27 SIN 28 VSYNC
Checking order when there is no audio
1.Check the contact condition of or 24V connector of Main Board
2. Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
3.Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
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Standard Repair Process Detail Technical Manual
Error symptom Established
D. Function error date
Revised
Content Remote controller operation checking method date A22
P4000
10 GND
12 KEY1
14 KEY2
③ 16 +3.5V_ST
18 GND
17 LED
15 IR
13 GND
④ 11 EYE_SCL
9 EYE_SDA
①
②
Checking order
1.Check IR cable condition between IR & Main board.( Check picture number① and ②)
2.Check the standby 3.5V on the terminal 4, 7
3.AS checking the Pre-Amp(IR LED light) , the power is in ON condition, an Analog Tester
needle should move slowly, otherwise, it’s defective.
A22
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Standard Repair Process Detail Technical Manual
Error symptom Established
D. Function error date
Revised
Content Motion Remote /Wifi operation checking method date A23
③ P4000
1 +3.5V_WIFI
2 USB_DM
3 USB_DP
4 GND
5 WOL
6 NC
7 BT_RESET
8 GND
①
② ②
Checking order to check motion remote/wifi
Checking order
1.Check BT/Wifi cable condition between BT/Wifi assy & Main board.
2.Check the 3.5V on the terminal 2
A23
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Only for training and service purposes
